================ @@ -830,3 +830,16 @@ def : RISCVRegisterClass<[XLenVT], 32, (add SF_VCIX_STATE)> { let RegInfos = XLenRI; let isAllocatable = 0; } + +//===----------------------------------------------------------------------===// +// XSfmmbase tiles +//===----------------------------------------------------------------------===// +foreach Index = 0-15 in + def T#Index : RISCVReg<Index, "mt"#Index, []>, + DwarfRegNum<[!add(Index, 3072)]>; + +let RegInfos = XLenRI in { + def TR : RISCVRegisterClass<[untyped], 32, (add (sequence "T%u", 0, 15))>; ---------------- wangpc-pp wrote:
> The tiles here are scalable in two dimensions which TypeSize can't represent. Yeah, we encountered the same problem and this is why XuanTie's AME is designed as that two dimensions are related IIRC. https://github.com/llvm/llvm-project/pull/133031 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits