Re: [PATCH v6] RISC-V:Optimize the MASK opt generation

[Kito Cheng]

Hi Jeff:

Could you take a look for this? RISC-V part is ok to me.

Thanks :)

Feng Wang  於 2023年9月12日 週二 17:18 寫道：

> New patch add some comments and update docs for this new usage.
> ---
> Accoring to Kito's advice, using "MASK(name) Var(other_flag_name)"
> to generate MASK and TARGET MACRO automatically.
> This patch improve the MACRO generation of MASK_* and TARGET_*.
> Due to the more and more riscv extensions are added, the default
> target_flag
> is full.
> Before this patch,if you want to add new MACRO,you should define the
> MACRO in the riscv-opts.h manually.
> After this patch, you just need two steps:
> 1.Define the new TargetVariable.
> 2.Define "MASK(name) Var(new_target_flag).
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-opts.h (MASK_ZICSR):
> (MASK_ZIFENCEI): Delete;
> (MASK_ZIHINTNTL):Ditto;
> (MASK_ZIHINTPAUSE):  Ditto;
> (TARGET_ZICSR):  Ditto;
> (TARGET_ZIFENCEI):   Ditto;
> (TARGET_ZIHINTNTL):  Ditto;
> (TARGET_ZIHINTPAUSE):Ditto;
> (MASK_ZAWRS):Ditto;
> (TARGET_ZAWRS):  Ditto;
> (MASK_ZBA):  Ditto;
> (MASK_ZBB):  Ditto;
> (MASK_ZBC):  Ditto;
> (MASK_ZBS):  Ditto;
> (TARGET_ZBA):Ditto;
> (TARGET_ZBB):Ditto;
> (TARGET_ZBC):Ditto;
> (TARGET_ZBS):Ditto;
> (MASK_ZFINX):Ditto;
> (MASK_ZDINX):Ditto;
> (MASK_ZHINX):Ditto;
> (MASK_ZHINXMIN): Ditto;
> (TARGET_ZFINX):  Ditto;
> (TARGET_ZDINX):  Ditto;
> (TARGET_ZHINX):  Ditto;
> (TARGET_ZHINXMIN):   Ditto;
> (MASK_ZBKB): Ditto;
> (MASK_ZBKC): Ditto;
> (MASK_ZBKX): Ditto;
> (MASK_ZKNE): Ditto;
> (MASK_ZKND): Ditto;
> (MASK_ZKNH): Ditto;
> (MASK_ZKR):  Ditto;
> (MASK_ZKSED):Ditto;
> (MASK_ZKSH): Ditto;
> (MASK_ZKT):  Ditto;
> (TARGET_ZBKB):   Ditto;
> (TARGET_ZBKC):   Ditto;
> (TARGET_ZBKX):   Ditto;
> (TARGET_ZKNE):   Ditto;
> (TARGET_ZKND):   Ditto;
> (TARGET_ZKNH):   Ditto;
> (TARGET_ZKR):Ditto;
> (TARGET_ZKSED):  Ditto;
> (TARGET_ZKSH):   Ditto;
> (TARGET_ZKT):Ditto;
> (MASK_ZTSO): Ditto;
> (TARGET_ZTSO):   Ditto;
> (MASK_VECTOR_ELEN_32):   Ditto;
> (MASK_VECTOR_ELEN_64):   Ditto;
> (MASK_VECTOR_ELEN_FP_32):Ditto;
> (MASK_VECTOR_ELEN_FP_64):Ditto;
> (MASK_VECTOR_ELEN_FP_16):Ditto;
> (TARGET_VECTOR_ELEN_32): Ditto;
> (TARGET_VECTOR_ELEN_64): Ditto;
> (TARGET_VECTOR_ELEN_FP_32):Ditto;
> (TARGET_VECTOR_ELEN_FP_64):Ditto;
> (TARGET_VECTOR_ELEN_FP_16):Ditto;
>  (MASK_ZVBB):   Ditto;
> (MASK_ZVBC):   Ditto;
> (TARGET_ZVBB): Ditto;
> (TARGET_ZVBC): Ditto;
> (MASK_ZVKG):   Ditto;
> (MASK_ZVKNED): Ditto;
> (MASK_ZVKNHA): Ditto;
> (MASK_ZVKNHB): Ditto;
> (MASK_ZVKSED): Ditto;
> (MASK_ZVKSH):  Ditto;
> (MASK_ZVKN):   Ditto;
> (MASK_ZVKNC):  Ditto;
> (MASK_ZVKNG):  Ditto;
> (MASK_ZVKS):   Ditto;
> (MASK_ZVKSC):  Ditto;
> (MASK_ZVKSG):  Ditto;
> (MASK_ZVKT):   Ditto;
> (TARGET_ZVKG): Ditto;
> (TARGET_ZVKNED):   Ditto;
> (TARGET_ZVKNHA):   Ditto;
> (TARGET_ZVKNHB):   Ditto;
> (TARGET_ZVKSED):   Ditto;
> (TARGET_ZVKSH):Ditto;
> (TARGET_ZVKN): Ditto;
> (TARGET_ZVKNC):Ditto;
> (TARGET_ZVKNG):Ditto;
> (TARGET_ZVKS): Ditto;
> (TARGET_ZVKSC):Ditto;
> (TARGET_ZVKSG):Ditto;
> (TARGET_ZVKT): Ditto;
> (MASK_ZVL32B): Ditto;
> (MASK_ZVL64B): Ditto;
> (MASK_ZVL128B):Ditto;
> (MASK_ZVL256B):Ditto;
> (MASK_ZVL512B):Ditto;
> (MASK_ZVL1024B):   Ditto;
> (MASK_ZVL2048B):   Ditto;
> (MASK_ZVL4096B):   Ditto;
> (MASK_ZVL8192B):   Ditto;
> (MASK_ZVL16384B):  Ditto;
> (MASK_ZVL32768B):  Ditto;
> (MASK_ZVL65536B):  Ditto;
> (TARGET_ZVL32B):   Ditto;
> (TARGET_ZVL64B):   Ditto;
> (TARGET_ZVL128B):  Ditto;
> (TARGET_ZVL256B):  Ditto;
> (TARGET_ZVL512B):  Ditto;
> (TARGET_ZVL1024B): Ditto;
> (TARGET_ZVL2048B): Ditto;
> (TARGET_ZVL4096B): Ditto;
> (

Re: [PATCH v6] RISC-V:Optimize the MASK opt generation

[Kito Cheng]

Committed to trunk, thanks Feng :)

On Sat, Sep 30, 2023 at 3:34 AM Jeff Law  wrote:
>
>
>
> On 9/12/23 03:18, Feng Wang wrote:
> > New patch add some comments and update docs for this new usage.
> > ---
> > Accoring to Kito's advice, using "MASK(name) Var(other_flag_name)"
> > to generate MASK and TARGET MACRO automatically.
> > This patch improve the MACRO generation of MASK_* and TARGET_*.
> > Due to the more and more riscv extensions are added, the default target_flag
> > is full.
> > Before this patch,if you want to add new MACRO,you should define the
> > MACRO in the riscv-opts.h manually.
> > After this patch, you just need two steps:
> > 1.Define the new TargetVariable.
> > 2.Define "MASK(name) Var(new_target_flag).
> >
> > gcc/ChangeLog:
> >
> >  * config/riscv/riscv-opts.h (MASK_ZICSR):
> >  (MASK_ZIFENCEI): Delete;
> >  (MASK_ZIHINTNTL):Ditto;
> >  (MASK_ZIHINTPAUSE):  Ditto;
> >  (TARGET_ZICSR):  Ditto;
> >  (TARGET_ZIFENCEI):   Ditto;
> >  (TARGET_ZIHINTNTL):  Ditto;
> >  (TARGET_ZIHINTPAUSE):Ditto;
> >  (MASK_ZAWRS):Ditto;
> >  (TARGET_ZAWRS):  Ditto;
> >  (MASK_ZBA):  Ditto;
> >  (MASK_ZBB):  Ditto;
> >  (MASK_ZBC):  Ditto;
> >  (MASK_ZBS):  Ditto;
> >  (TARGET_ZBA):Ditto;
> >  (TARGET_ZBB):Ditto;
> >  (TARGET_ZBC):Ditto;
> >  (TARGET_ZBS):Ditto;
> >  (MASK_ZFINX):Ditto;
> >  (MASK_ZDINX):Ditto;
> >  (MASK_ZHINX):Ditto;
> >  (MASK_ZHINXMIN): Ditto;
> >  (TARGET_ZFINX):  Ditto;
> >  (TARGET_ZDINX):  Ditto;
> >  (TARGET_ZHINX):  Ditto;
> >  (TARGET_ZHINXMIN):   Ditto;
> >  (MASK_ZBKB): Ditto;
> >  (MASK_ZBKC): Ditto;
> >  (MASK_ZBKX): Ditto;
> >  (MASK_ZKNE): Ditto;
> >  (MASK_ZKND): Ditto;
> >  (MASK_ZKNH): Ditto;
> >  (MASK_ZKR):  Ditto;
> >  (MASK_ZKSED):Ditto;
> >  (MASK_ZKSH): Ditto;
> >  (MASK_ZKT):  Ditto;
> >  (TARGET_ZBKB):   Ditto;
> >  (TARGET_ZBKC):   Ditto;
> >  (TARGET_ZBKX):   Ditto;
> >  (TARGET_ZKNE):   Ditto;
> >  (TARGET_ZKND):   Ditto;
> >  (TARGET_ZKNH):   Ditto;
> >  (TARGET_ZKR):Ditto;
> >  (TARGET_ZKSED):  Ditto;
> >  (TARGET_ZKSH):   Ditto;
> >  (TARGET_ZKT):Ditto;
> >  (MASK_ZTSO): Ditto;
> >  (TARGET_ZTSO):   Ditto;
> >  (MASK_VECTOR_ELEN_32):   Ditto;
> >  (MASK_VECTOR_ELEN_64):   Ditto;
> >  (MASK_VECTOR_ELEN_FP_32):Ditto;
> >  (MASK_VECTOR_ELEN_FP_64):Ditto;
> >  (MASK_VECTOR_ELEN_FP_16):Ditto;
> >  (TARGET_VECTOR_ELEN_32): Ditto;
> >  (TARGET_VECTOR_ELEN_64): Ditto;
> >  (TARGET_VECTOR_ELEN_FP_32):Ditto;
> >  (TARGET_VECTOR_ELEN_FP_64):Ditto;
> >  (TARGET_VECTOR_ELEN_FP_16):Ditto;
> >   (MASK_ZVBB):   Ditto;
> >  (MASK_ZVBC):   Ditto;
> >  (TARGET_ZVBB): Ditto;
> >  (TARGET_ZVBC): Ditto;
> >  (MASK_ZVKG):   Ditto;
> >  (MASK_ZVKNED): Ditto;
> >  (MASK_ZVKNHA): Ditto;
> >  (MASK_ZVKNHB): Ditto;
> >  (MASK_ZVKSED): Ditto;
> >  (MASK_ZVKSH):  Ditto;
> >  (MASK_ZVKN):   Ditto;
> >  (MASK_ZVKNC):  Ditto;
> >  (MASK_ZVKNG):  Ditto;
> >  (MASK_ZVKS):   Ditto;
> >  (MASK_ZVKSC):  Ditto;
> >  (MASK_ZVKSG):  Ditto;
> >  (MASK_ZVKT):   Ditto;
> >  (TARGET_ZVKG): Ditto;
> >  (TARGET_ZVKNED):   Ditto;
> >  (TARGET_ZVKNHA):   Ditto;
> >  (TARGET_ZVKNHB):   Ditto;
> >  (TARGET_ZVKSED):   Ditto;
> >  (TARGET_ZVKSH):Ditto;
> >  (TARGET_ZVKN): Ditto;
> >  (TARGET_ZVKNC):Ditto;
> >  (TARGET_ZVKNG):Ditto;
> >  (TARGET_ZVKS): Ditto;
> >  (TARGET_ZVKSC):Ditto;
> >  (TARGET_ZVKSG):Ditto;
> >  (TARGET_ZVKT): Ditto;
> >  (MASK_ZVL32B): Ditto;
> >  (MASK_ZVL64B): Ditto;
> >  (MASK_ZVL128B):Ditto;
> >  (MASK_ZVL256B):Ditto;
> >  (MASK_ZVL512B):Ditto;
> >  (MASK_ZVL1024B):   Ditto;
> >  (MASK_ZVL2048B):   Ditto;
> >  (MASK_ZVL4096B):   Ditto;
> >  (MASK_ZVL8192B):   Ditto;
> >  (MASK_ZVL16384B):  Ditto;
> >  (MASK_ZVL32768B):  Ditto;
> >  (MASK_ZVL65536B): 

Re: [PATCH v6] RISC-V:Optimize the MASK opt generation

[Kito Cheng]

Hi Gerald:

Thanks for reporting this issue, I just realized multidimensional
arrays are gawk extensions, could you try the attached patch to see if
it can resolve the issue?

On Mon, Oct 2, 2023 at 4:56 AM Gerald Pfeifer  wrote:
>
> On Sun, 1 Oct 2023, Kito Cheng wrote:
> > Committed to trunk, thanks Feng :)
>
> Hmm, my nightly FreeBSD 12 tester now fails as follows:
>
>   nawk -f /scratch/tmp/gerald/GCC-HEAD/gcc/opt-functions.awk \
> -f /scratch/tmp/gerald/GCC-HEAD/gcc/opt-read.awk \
> -f /scratch/tmp/gerald/GCC-HEAD/gcc/opth-gen.awk \
>< optionlist > tmp-options.h
>   nawk: syntax error at source line 67 source file
> /scratch/tmp/gerald/GCC-HEAD/gcc/opt-read.awk
>   context is
> >>>other_masks[var_index][
> <<< n_other_mask[var_index]++] = name
>   nawk: illegal statement at source line 67 source file
>   /scratch/tmp/gerald/GCC-HEAD/gcc/opt-read.awk
>   nawk -f /scratch/tmp/gerald/GCC-HEAD/gcc/opt-functions.awk \
> -f /scratch/tmp/gerald/GCC-HEAD/gcc/opt-read.awk \
>-f /scratch/tmp/gerald/GCC-HEAD/gcc/optc-save-gen.awk \
>-v header_name="config.h system.h coretypes.h tm.h" < optionlist \
>> options-save.cc
>   nawk: syntax error at source line 386 source file
>   /scratch/tmp/gerald/GCC-HEAD/gcc/opth-gen.awk
>   nawk: syntax error at source line 67 source file
>   /scratch/tmp/gerald/GCC-HEAD/gcc/opt-read.awk
>   context is
> >>>other_masks[var_index][
> <<< n_other_mask[var_index]++] = name
>   nawk: illegal statement at source line 67 source file
>   /scratch/tmp/gerald/GCC-HEAD/gcc/opt-read.awk
>   gmake[3]: *** [Makefile:2477: s-options-h] Error 2
>
> Gerald
From a2a621ed6a3eaf136e917d10f4970a6bf7240d5a Mon Sep 17 00:00:00 2001
From: Kito Cheng 
Date: Mon, 2 Oct 2023 10:50:42 +0800
Subject: [PATCH] options: Prevent multidimensional arrays

Multidimensional arrary is gawk extension, and we accidentally
introduced that in recent commit[1].

[1] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=e4a4b8e983bac865eb435b11798e38d633b98942

gcc/ChangeLog:

	* opt-read.awk: Drop multidimensional arrays.
	* opth-gen.awk: Ditto.
---
 gcc/opt-read.awk | 2 +-
 gcc/opth-gen.awk | 8 
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/gcc/opt-read.awk b/gcc/opt-read.awk
index fcf92853957..b6b4c01888d 100644
--- a/gcc/opt-read.awk
+++ b/gcc/opt-read.awk
@@ -131,7 +131,7 @@ BEGIN {
 	{
 		target_vars[n_target_vars++] = target_var
 	}
-	other_masks[var_index][n_other_mask[var_index]++] = name
+	other_masks[var_index "," n_other_mask[var_index]++] = name
 }
 else
 {
diff --git a/gcc/opth-gen.awk b/gcc/opth-gen.awk
index 70ca3d37719..c4398be2f3a 100644
--- a/gcc/opth-gen.awk
+++ b/gcc/opth-gen.awk
@@ -412,9 +412,9 @@ for (i = 0; i < n_target_vars; i++)
 		continue
 	for (j = 0; j < n_other_mask[i]; j++)
 	{
-		print "#define MASK_" other_masks[i][j] " (1U << " other_masknum[i][""]++ ")"
+		print "#define MASK_" other_masks[i "," j] " (1U << " other_masknum[i]++ ")"
 	}
-	if (other_masknum[i][""] > 32)
+	if (other_masknum[i] > 32)
 		print "#error too many target masks for" extra_target_vars[i]
 }
 
@@ -437,8 +437,8 @@ for (i = 0; i < n_target_vars; i++)
 		continue
 	for (j = 0; j < n_other_mask[i]; j++)
 	{
-		print "#define TARGET_" other_masks[i][j] \
-		  " ((" target_vars[i] " & MASK_" other_masks[i][j] ") != 0)"
+		print "#define TARGET_" other_masks[i "," j] \
+		  " ((" target_vars[i] " & MASK_" other_masks[i "," j] ") != 0)"
 	}
 }
 print ""
-- 
2.40.1

[PATCH] options: Prevent multidimensional arrays

[Kito Cheng]

Multidimensional arrary is gawk extension, and we accidentally
introduced that in recent commit[1].

[1] 
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=e4a4b8e983bac865eb435b11798e38d633b98942

gcc/ChangeLog:

* opt-read.awk: Drop multidimensional arrays.
* opth-gen.awk: Ditto.
---
 gcc/opt-read.awk | 4 ++--
 gcc/opth-gen.awk | 8 
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/gcc/opt-read.awk b/gcc/opt-read.awk
index fcf92853957..f74d8478f72 100644
--- a/gcc/opt-read.awk
+++ b/gcc/opt-read.awk
@@ -123,7 +123,7 @@ BEGIN {
}
else {
target_var = opt_args("Var", $0)
-if (target_var)
+   if (target_var)
{
target_var = opt_args("Var", $1)
var_index = find_index(target_var, 
target_vars, n_target_vars)
@@ -131,7 +131,7 @@ BEGIN {
{
target_vars[n_target_vars++] = 
target_var
}
-   
other_masks[var_index][n_other_mask[var_index]++] = name
+   other_masks[var_index "," 
n_other_mask[var_index]++] = name
}
else
{
diff --git a/gcc/opth-gen.awk b/gcc/opth-gen.awk
index 70ca3d37719..c4398be2f3a 100644
--- a/gcc/opth-gen.awk
+++ b/gcc/opth-gen.awk
@@ -412,9 +412,9 @@ for (i = 0; i < n_target_vars; i++)
continue
for (j = 0; j < n_other_mask[i]; j++)
{
-   print "#define MASK_" other_masks[i][j] " (1U << " 
other_masknum[i][""]++ ")"
+   print "#define MASK_" other_masks[i "," j] " (1U << " 
other_masknum[i]++ ")"
}
-   if (other_masknum[i][""] > 32)
+   if (other_masknum[i] > 32)
print "#error too many target masks for" extra_target_vars[i]
 }
 
@@ -437,8 +437,8 @@ for (i = 0; i < n_target_vars; i++)
continue
for (j = 0; j < n_other_mask[i]; j++)
{
-   print "#define TARGET_" other_masks[i][j] \
- " ((" target_vars[i] " & MASK_" other_masks[i][j] ") != 
0)"
+   print "#define TARGET_" other_masks[i "," j] \
+ " ((" target_vars[i] " & MASK_" other_masks[i "," j] ") 
!= 0)"
}
 }
 print ""
-- 
2.40.1

Re: [PATCH] RISC-V: Use stdint-gcc.h in rvv testsuite

[Kito Cheng]

> > On Tue, Sep 26, 2023 at 10:59 AM Patrick O'Neill  
> > wrote:
> >> stdint.h can be replaced with stdint-gcc.h to resolve some missing
> >> system headers in non-multilib installations.
> >>
> >> Tested using glibc rv32gcv and rv64gcv on r14-4258-gc9837443075.
> >>
> >> gcc/ChangeLog:
> >>
> >>  * config/riscv/riscv_vector.h (__RISCV_VECTOR_H): Replace
> >>  stdint.h with stdint-gcc.h
> > I don't think this will work when testing an installed compiler which I do.
> >
> > Thanks,
> > Andrew
> In the riscv target testsuite (gcc.target/riscv) all occurrences of
> #include  are currently constrained to the rvv/ subdirectory.
> All non-vector tests use #include  rather than
> #include . Have you encountered any issues when testing
> installations with non-vector tests?

I think the concern is to replace stdint.h with stdint-gcc.h for riscv_vector.h,
that means users MAY include stdint-gcc.h *AND* stdint.h, stdint.h the later
one generally is provided by libc, and stdint-gcc.h typically are not included.

Other than the changes in "riscv_vector.h", everything else looks fine to me.

Re: [PATCH v2] RISC-V: Implement TLS Descriptors.

[Kito Cheng]

Just one nit and one more comment for doc:

Could you add some doc something like that? mostly I grab from other
target, so you can just included in the patch.

diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 31f2234640f..39396668da2 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -1174,6 +1174,9 @@ Specify the default TLS dialect, for systems
were there is a choice.
For ARM targets, possible values for @var{dialect} are @code{gnu} or
@code{gnu2}, which select between the original GNU dialect and the GNU TLS
descriptor-based dialect.
+For RISC-V targets, possible values for @var{dialect} are @code{trad} or
+@code{desc}, which select between the traditional GNU dialect and the GNU TLS
+descriptor-based dialect.

@item --enable-multiarch
Specify whether to enable or disable multiarch support.  The default is
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 4085fc90907..459e266d426 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1239,7 +1239,8 @@ See RS/6000 and PowerPC Options.
-minline-atomics  -mno-inline-atomics
-minline-strlen  -mno-inline-strlen
-minline-strcmp  -mno-inline-strcmp
--minline-strncmp  -mno-inline-strncmp}
+-minline-strncmp  -mno-inline-strncmp
+-mtls-dialect=desc  -mtls-dialect=trad}

@emph{RL78 Options}
@gccoptlist{-msim  -mmul=none  -mmul=g13  -mmul=g14  -mallregs
@@ -29538,6 +29539,17 @@ which register to use as base register for
reading the canary,
and from what offset from that base register. There is no default
register or offset as this is entirely for use within the Linux
kernel.
+
+@opindex mtls-dialect=desc
+@item -mtls-dialect=desc
+Use TLS descriptors as the thread-local storage mechanism for dynamic accesses
+of TLS variables.  This is the default.
+
+@opindex mtls-dialect=trad
+@item -mtls-dialect=traditional
+Use traditional TLS as the thread-local storage mechanism for dynamic accesses
+of TLS variables.
+
@end table

@node RL78 Options




> +(define_insn "@tlsdesc"
> +  [(set (reg:P A0_REGNUM)
> +   (unspec:P
> +   [(match_operand:P 0 "symbolic_operand" "")
> +(match_operand:P 1 "const_int_operand")]
> +   UNSPEC_TLSDESC))
> +   (clobber (reg:SI T0_REGNUM))]

P rather than SI here.

> +  "TARGET_TLSDESC"
> +  {
> +return ".LT%1: auipc\ta0, %%tlsdesc_hi(%0)\;"
> +   "\tt0,%%tlsdesc_load_lo(.LT%1)(a0)\;"
> +   "addi\ta0,a0,%%tlsdesc_add_lo(.LT%1)\;"
> +   "jalr\tt0,t0,%%tlsdesc_call(.LT%1)";
> +  }
> +  [(set_attr "type" "multi")
> +   (set_attr "length" "16")
> +   (set_attr "mode" "")])
> +
>  (define_insn "auipc"
>[(set (match_operand:P   0 "register_operand" "=r")
> (unspec:P

[PATCH] RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512.

[Kito Cheng]

riscv_legitimize_poly_move was expected to ensure the poly value is at most 32
times smaller than the minimal VLEN (32 being derived from '4096 / 128').
This assumption held when our mode modeling was not so precisely defined.
However, now that we have modeled the mode size according to the correct minimal
VLEN info, the size difference between different RVV modes can be up to 64
times. For instance, comparing RVVMF64BI and RVVMF1BI, the sizes are [1, 1]
versus [64, 64] respectively.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_legitimize_poly_move): Bump
max_power to 64.

gcc/testsuite/ChangeLog:

* g++.target/riscv/rvv/autovec/bug-01.C: New.
* g++.target/riscv/rvv/rvv.exp: Add autovec folder.
---
 gcc/config/riscv/riscv.cc |  7 ++--
 .../g++.target/riscv/rvv/autovec/bug-01.C | 33 +++
 gcc/testsuite/g++.target/riscv/rvv/rvv.exp|  3 ++
 3 files changed, 40 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index d5446b63dbf..6468702e3a3 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2386,9 +2386,10 @@ riscv_legitimize_poly_move (machine_mode mode, rtx dest, 
rtx tmp, rtx src)
 }
   else
 {
-  /* FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096.  */
-  int max_power = exact_log2 (4096 / 128);
-  for (int i = 0; i < max_power; i++)
+  /* The size difference between different RVV modes can be up to 64 times.
+e.g. RVVMF64BI vs RVVMF1BI on zvl512b, which is [1, 1] vs [64, 64].  */
+  int max_power = exact_log2 (64);
+  for (int i = 0; i <= max_power; i++)
{
  int possible_div_factor = 1 << i;
  if (factor % (vlenb / possible_div_factor) == 0)
diff --git a/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C 
b/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C
new file mode 100644
index 000..fd10009ddbe
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C
@@ -0,0 +1,33 @@
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3" } */
+
+class c {
+public:
+  int e();
+  void j();
+};
+float *d;
+class k {
+  int f;
+
+public:
+  k(int m) : f(m) {}
+  float g;
+  float h;
+  void n(int m) {
+for (int i; i < m; i++) {
+  d[0] = d[1] = d[2] = g;
+  d[3] = h;
+  d += f;
+}
+  }
+};
+c l;
+void o() {
+  int b = l.e();
+  k a(b);
+  for (;;)
+if (b == 4) {
+  l.j();
+  a.n(2);
+}
+}
diff --git a/gcc/testsuite/g++.target/riscv/rvv/rvv.exp 
b/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
index 249530580d7..c30d6e93144 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
@@ -40,5 +40,8 @@ set CFLAGS "-march=$gcc_march -O3"
 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.C]] \
"" $CFLAGS
 
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[C\]]] \
+"" $CFLAGS
+
 # All done.
 dg-finish
-- 
2.40.1

Re: [PATCH v3] RISC-V:Optimize the MASK opt generation

[Kito Cheng]

Proposed fix, and verified with "mawk" and "gawk -P" (gawk with posix
mode) on my linux also some other report it work on freebsd, just wait
review :)

https://gcc.gnu.org/pipermail/gcc-patches/2023-October/631785.html

On Tue, Oct 3, 2023 at 2:07 AM Jeff Law  wrote:
>
>
>
> On 10/2/23 12:03, David Edelsohn wrote:
> > On Mon, Oct 2, 2023 at 1:59 PM Jeff Law  > > wrote:
> >
> >
> >
> > On 10/2/23 11:20, David Edelsohn wrote:
> >  > Wang,
> >  >
> >  > The AWK portions of this patch broke bootstrap on AIX.
> >  >
> >  > Also, the AWK portions are common code, not RISC-V specific.  I
> > don't
> >  > see anywhere that the common portions of the patch were reviewed or
> >  > approved by anyone with authority to approve the changes to the
> > AWK files.
> >  >
> >  > This patch should not have been committed without approval by a
> > reviewer
> >  > with authority for that portion of the compiler and should have been
> >  > tested on targets other than RISC-V if common parts of the
> > compiler were
> >  > changed.
> > I acked the generic bits.  So the lack of testing on another target is
> > on me.
> >
> >
> > Hi, Jeff
> >
> > Sorry. I didn't see a comment from a global reviewer in the V3 thread.
> NP.
>
> >
> > I am using Gawk on AIX.  After the change, I see a parse error from
> > gawk.  I'm rebuilding with a checkout just before the change to confirm
> > that it was the source of the error, and it seems to be past that
> > failure location.  I didn't keep the exact error.  Once I get past this
> > build cycle, I'll reproduce it.
> I think there's already a patch circulating which fixes this.  It broke
> at least one other platform.  Hopefully it'll all be sorted out today.
>
>
> jeff

[PATCH v1 1/4] options: Define TARGET__P and TARGET__OPTS_P macro for Mask and InverseMask

[Kito Cheng]

We TARGET__P marcro to test a Mask and InverseMask with user
specified target_variable, however we may want to test with specific
gcc_options variable rather than target_variable.

Like RISC-V has defined lots of Mask with TargetVariable, which is not
easy to use, because that means we need to known which Mask are associate with
which TargetVariable, so take a gcc_options variable is a better interface
for such use case.

gcc/ChangeLog:

* doc/options.texi (Mask): Document TARGET__P and
TARGET__OPTS_P.
(InverseMask): Ditto.
* opth-gen.awk (Mask): Generate TARGET__P and
TARGET__OPTS_P macro.
(InverseMask): Ditto.
---
 gcc/doc/options.texi | 23 ---
 gcc/opth-gen.awk | 13 -
 2 files changed, 28 insertions(+), 8 deletions(-)

diff --git a/gcc/doc/options.texi b/gcc/doc/options.texi
index 1f7c15b8eb4..715f0a1479c 100644
--- a/gcc/doc/options.texi
+++ b/gcc/doc/options.texi
@@ -404,18 +404,27 @@ You may also specify @code{Var} to select a variable 
other than
 The options-processing script will automatically allocate a unique bit
 for the option.  If the option is attached to @samp{target_flags} or @code{Var}
 which is defined by @code{TargetVariable},  the script will set the macro
-@code{MASK_@var{name}} to the appropriate bitmask.  It will also declare a 
-@code{TARGET_@var{name}} macro that has the value 1 when the option is active
-and 0 otherwise.  If you use @code{Var} to attach the option to a different 
variable
-which is not defined by @code{TargetVariable}, the bitmask macro with be
-called @code{OPTION_MASK_@var{name}}.
+@code{MASK_@var{name}} to the appropriate bitmask.  It will also declare a
+@code{TARGET_@var{name}}, @code{TARGET_@var{name}_P} and
+@code{TARGET_@var{name}_OPTS_P}: @code{TARGET_@var{name}} macros that has the
+value 1 when the option is active and 0 otherwise, @code{TARGET_@var{name}_P} 
is
+similar to @code{TARGET_@var{name}} but take an argument as @samp{target_flags}
+or @code{TargetVariable}, and @code{TARGET_@var{name}_OPTS_P} also similar to
+@code{TARGET_@var{name}} but take an argument as @code{gcc_options}.
+If you use @code{Var} to attach the option to a different variable which is not
+defined by @code{TargetVariable}, the bitmask macro with be called
+@code{OPTION_MASK_@var{name}}.
 
 @item InverseMask(@var{othername})
 @itemx InverseMask(@var{othername}, @var{thisname})
 The option is the inverse of another option that has the
 @code{Mask(@var{othername})} property.  If @var{thisname} is given,
-the options-processing script will declare a @code{TARGET_@var{thisname}}
-macro that is 1 when the option is active and 0 otherwise.
+the options-processing script will declare @code{TARGET_@var{thisname}},
+@code{TARGET_@var{name}_P} and @code{TARGET_@var{name}_OPTS_P} macros:
+@code{TARGET_@var{thisname}} is 1 when the option is active and 0 otherwise,
+@code{TARGET_@var{name}_P} is similar to @code{TARGET_@var{name}} but take an
+argument as @samp{target_flags}, and and @code{TARGET_@var{name}_OPTS_P} also
+similar to @code{TARGET_@var{name}} but take an argument as @code{gcc_options}.
 
 @item Enum(@var{name})
 The option's argument is a string from the set of strings associated
diff --git a/gcc/opth-gen.awk b/gcc/opth-gen.awk
index 70ca3d37719..4d498abd130 100644
--- a/gcc/opth-gen.awk
+++ b/gcc/opth-gen.awk
@@ -439,6 +439,10 @@ for (i = 0; i < n_target_vars; i++)
{
print "#define TARGET_" other_masks[i][j] \
  " ((" target_vars[i] " & MASK_" other_masks[i][j] ") != 
0)"
+   print "#define TARGET_" other_masks[i][j] "_P(" target_vars[i] 
")" \
+ " (((" target_vars[i] ") & MASK_" other_masks[i][j] ") != 
0)"
+   print "#define TARGET_" other_masks[i][j] "_OPTS_P(opts)" \
+ " (((opts->x_" target_vars[i] ") & MASK_" 
other_masks[i][j] ") != 0)"
}
 }
 print ""
@@ -469,15 +473,22 @@ for (i = 0; i < n_opts; i++) {
  " ((" vname " & " mask original_name ") != 0)"
print "#define TARGET_" name "_P(" vname ")" \
  " (((" vname ") & " mask original_name ") != 0)"
+   print "#define TARGET_" name "_OPTS_P(opts)" \
+ " (((opts->x_" vname ") & " mask original_name ") != 0)"
print "#define TARGET_EXPLICIT_" name "_P(opts)" \
  " ((opts->x_" vname "_explicit & " mask original_name ") 
!= 0)"
print "#define SET_TARGET_" name "(opts) opts->x_" vname " |= " 
mask original_name
}
 }
 for (i = 0; i < n_extra_masks; i++) {
-   if (extra_mask_macros[extra_masks[i]] == 0)
+   if (extra_mask_macros[extra_masks[i]] == 0) {
print "#define TARGET_" extra_masks[i] \
  " ((target_flags & MASK_" extra_masks[i] ") != 0)"
+   print "#define TARGET_" extra_masks[i] "_P(target_flags)" \
+ 

[no subject]

[Kito Cheng]

From: Kito Cheng 

Reply-To:

Subject: [PATCH v1 0/4] RISC-V target attribute

In-Reply-To:

This patch set implement target attribute for RISC-V target, which is similar 
to other target like x86 or ARM, let user able to set some local setting per 
function without changing global settings.

We support arch, tune and cpu first, and we will support other target attribute 
later, this version DOES NOT include multi-version function support yet, that 
is future work, probably work for GCC 15.

The full proposal is put in RISC-V C-API document[1], which has discussed with 
RISC-V LLVM community, so we have consistent syntax and semantics. 

[1] https://github.com/riscv-non-isa/riscv-c-api-doc/pull/35

[PATCH v1 2/4] RISC-V: Refactor riscv_option_override and riscv_convert_vector_bits. [NFC]

[Kito Cheng]

Allow those funciton apply from a local gcc_options rather than the
global options.

Preparatory for target attribute, sperate this change for eaiser reivew
since it's a NFC.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_convert_vector_bits): Get setting
from argument rather than get setting from global setting.
(riscv_override_options_internal): New, splited from
riscv_override_options, also take a gcc_options argument.
(riscv_option_override): Splited most part to
riscv_override_options_internal.
---
 gcc/config/riscv/riscv.cc | 93 ++-
 1 file changed, 52 insertions(+), 41 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index d5446b63dbf..d089ec1b241 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7982,10 +7982,11 @@ riscv_init_machine_status (void)
 /* Return the VLEN value associated with -march.
TODO: So far we only support length-agnostic value. */
 static poly_uint16
-riscv_convert_vector_bits (void)
+riscv_convert_vector_bits (struct gcc_options *opts)
 {
   int chunk_num;
-  if (TARGET_MIN_VLEN > 32)
+  int min_vlen = TARGET_MIN_VLEN_OPTS (opts);
+  if (min_vlen > 32)
 {
   /* When targetting minimum VLEN > 32, we should use 64-bit chunk size.
 Otherwise we can not include SEW = 64bits.
@@ -8003,7 +8004,7 @@ riscv_convert_vector_bits (void)
   - TARGET_MIN_VLEN = 2048bit: [256,256]
   - TARGET_MIN_VLEN = 4096bit: [512,512]
   FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096bit.  */
-  chunk_num = TARGET_MIN_VLEN / 64;
+  chunk_num = min_vlen / 64;
 }
   else
 {
@@ -8022,10 +8023,10 @@ riscv_convert_vector_bits (void)
  to set RVV mode size. The RVV machine modes size are run-time constant if
  TARGET_VECTOR is enabled. The RVV machine modes size remains default
  compile-time constant if TARGET_VECTOR is disabled.  */
-  if (TARGET_VECTOR)
+  if (TARGET_VECTOR_OPTS_P (opts))
 {
-  if (riscv_autovec_preference == RVV_FIXED_VLMAX)
-   return (int) TARGET_MIN_VLEN / (riscv_bytes_per_vector_chunk * 8);
+  if (opts->x_riscv_autovec_preference == RVV_FIXED_VLMAX)
+   return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8);
   else
return poly_uint16 (chunk_num, chunk_num);
 }
@@ -8033,40 +8034,33 @@ riscv_convert_vector_bits (void)
 return 1;
 }
 
-/* Implement TARGET_OPTION_OVERRIDE.  */
-
-static void
-riscv_option_override (void)
+/* 'Unpack' up the internal tuning structs and update the options
+in OPTS.  The caller must have set up selected_tune and selected_arch
+as all the other target-specific codegen decisions are
+derived from them.  */
+void
+riscv_override_options_internal (struct gcc_options *opts)
 {
   const struct riscv_tune_info *cpu;
 
-#ifdef SUBTARGET_OVERRIDE_OPTIONS
-  SUBTARGET_OVERRIDE_OPTIONS;
-#endif
-
-  flag_pcc_struct_return = 0;
-
-  if (flag_pic)
-g_switch_value = 0;
-
   /* The presence of the M extension implies that division instructions
  are present, so include them unless explicitly disabled.  */
-  if (TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0)
-target_flags |= MASK_DIV;
-  else if (!TARGET_MUL && TARGET_DIV)
+  if (TARGET_MUL_OPTS_P (opts) && (target_flags_explicit & MASK_DIV) == 0)
+opts->x_target_flags |= MASK_DIV;
+  else if (!TARGET_MUL_OPTS_P (opts) && TARGET_DIV_OPTS_P (opts))
 error ("%<-mdiv%> requires %<-march%> to subsume the % extension");
 
   /* Likewise floating-point division and square root.  */
   if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (target_flags_explicit & 
MASK_FDIV) == 0)
-target_flags |= MASK_FDIV;
+opts->x_target_flags |= MASK_FDIV;
 
   /* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune
  if both -mtune and -mcpu are not given.  */
-  cpu = riscv_parse_tune (riscv_tune_string ? riscv_tune_string :
- (riscv_cpu_string ? riscv_cpu_string :
+  cpu = riscv_parse_tune (opts->x_riscv_tune_string ? 
opts->x_riscv_tune_string :
+ (opts->x_riscv_cpu_string ? opts->x_riscv_cpu_string :
   RISCV_TUNE_STRING_DEFAULT));
   riscv_microarchitecture = cpu->microarchitecture;
-  tune_param = optimize_size ? &optimize_size_tune_info : cpu->tune_param;
+  tune_param = opts->x_optimize_size ? &optimize_size_tune_info : 
cpu->tune_param;
 
   /* Use -mtune's setting for slow_unaligned_access, even when optimizing
  for size.  For architectures that trap and emulate unaligned accesses,
@@ -8082,15 +8076,38 @@ riscv_option_override (void)
 
   if ((target_flags_explicit & MASK_STRICT_ALIGN) == 0
   && cpu->tune_param->slow_unaligned_access)
-target_flags |= MASK_STRICT_ALIGN;
+opts->x_target_flags |= MASK_STRICT_ALIGN;
 
   /* If the user hasn't specified a branch cost, use the processor's
  default.  */
-  if (riscv_branch_c

[PATCH v1 4/4] RISC-V: Implement target attribute

[Kito Cheng]

The target attribute which proposed in [1], target attribute allow user
to specify a local setting per-function basis.

The syntax of target attribute is `__attribute__((target("")))`.

and the syntax of `` describes below:
```
ATTR-STRING := ATTR-STRING ';' ATTR
 | ATTR

ATTR:= ARCH-ATTR
 | CPU-ATTR
 | TUNE-ATTR

ARCH-ATTR   := 'arch=' EXTENSIONS-OR-FULLARCH

EXTENSIONS-OR-FULLARCH := 
| 

EXTENSIONS :=  ',' 
| 

FULLARCHSTR:= 

EXTENSION  :=   

OP := '+'

VERSION:= [0-9]+ 'p' [0-9]+
| [1-9][0-9]*
|

EXTENSION-NAME := Naming rule is defined in RISC-V ISA manual

CPU-ATTR:= 'cpu=' 
TUNE-ATTR   := 'tune=' 
```

[1] https://github.com/riscv-non-isa/riscv-c-api-doc/pull/35

gcc/ChangeLog:

* config.gcc (riscv): Add riscv-target-attr.o.
* config/riscv/riscv-opts.h (TARGET_MIN_VLEN_OPTS): New.
* config/riscv/riscv-protos.h (riscv_declare_function_size) New.
(riscv_option_valid_attribute_p): New.
(riscv_override_options_internal): New.
(struct riscv_tune_info): New.
(riscv_parse_tune): New.
* config/riscv/riscv-target-attr.cc
(class riscv_target_attr_parser): New.
(struct riscv_attribute_info): New.
(riscv_attributes): New.
(riscv_target_attr_parser::parse_arch):
(riscv_target_attr_parser::handle_arch):
(riscv_target_attr_parser::handle_cpu):
(riscv_target_attr_parser::handle_tune):
(riscv_target_attr_parser::update_settings):
(riscv_process_one_target_attr):
(num_occurences_in_str):
(riscv_process_target_attr):
(riscv_option_valid_attribute_p):
* config/riscv/riscv.cc: Include target-globals.h and
riscv-subset.h.
(struct riscv_tune_info): Move to riscv-protos.h.
(get_tune_str):
(riscv_parse_tune):
(riscv_declare_function_size):
(riscv_option_override): Build target_option_default_node and
target_option_current_node.
(riscv_save_restore_target_globals):
(riscv_option_restore):
(riscv_previous_fndecl):
(riscv_set_current_function): Apply the target attribute.
(TARGET_OPTION_RESTORE): Define.
(TARGET_OPTION_VALID_ATTRIBUTE_P): Ditto.
* config/riscv/riscv.h (SWITCHABLE_TARGET): Define to 1.
(ASM_DECLARE_FUNCTION_SIZE) Define.
* config/riscv/riscv.opt (mtune=): Add Save attribute.
(mcpu=): Ditto.
(mcmodel=): Ditto.
* config/riscv/t-riscv: Add build rule for riscv-target-attr.o
* doc/extend.texi: Add doc for target attribute.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/target-attr-01.c: New.
* gcc.target/riscv/target-attr-02.c: Ditto.
* gcc.target/riscv/target-attr-03.c: Ditto.
* gcc.target/riscv/target-attr-04.c: Ditto.
* gcc.target/riscv/target-attr-05.c: Ditto.
* gcc.target/riscv/target-attr-06.c: Ditto.
* gcc.target/riscv/target-attr-07.c: Ditto.
* gcc.target/riscv/target-attr-bad-01.c: Ditto.
* gcc.target/riscv/target-attr-bad-02.c: Ditto.
* gcc.target/riscv/target-attr-bad-03.c: Ditto.
* gcc.target/riscv/target-attr-bad-04.c: Ditto.
* gcc.target/riscv/target-attr-bad-05.c: Ditto.
* gcc.target/riscv/target-attr-bad-06.c: Ditto.
* gcc.target/riscv/target-attr-bad-07.c: Ditto.
* gcc.target/riscv/target-attr-warning-01.c: Ditto.
* gcc.target/riscv/target-attr-warning-02.c: Ditto.
* gcc.target/riscv/target-attr-warning-03.c: Ditto.
---
 gcc/config.gcc|   2 +-
 gcc/config/riscv/riscv-opts.h |   6 +
 gcc/config/riscv/riscv-protos.h   |  21 +
 gcc/config/riscv/riscv-target-attr.cc | 396 ++
 gcc/config/riscv/riscv.cc | 192 +++--
 gcc/config/riscv/riscv.h  |   6 +
 gcc/config/riscv/riscv.opt|   6 +-
 gcc/config/riscv/t-riscv  |   5 +
 gcc/doc/extend.texi   |  58 +++
 .../gcc.target/riscv/target-attr-01.c |  31 ++
 .../gcc.target/riscv/target-attr-02.c |  31 ++
 .../gcc.target/riscv/target-attr-03.c |  26 ++
 .../gcc.target/riscv/target-attr-04.c |  28 ++
 .../gcc.target/riscv/target-attr-05.c |  27 ++
 .../gcc.target/riscv/target-attr-06.c |  27 ++
 .../gcc.target/riscv/target-attr-07.c |  25 ++
 .../gcc.target/riscv/target-attr-bad-01.c |  13 +
 .../gcc.target/riscv/target-attr-bad-02.c |  13 +
 .../gcc.target/riscv/target-attr-bad-03.c |  13 +
 .../gcc.target/riscv/target-attr-bad-04.c |  13 +
 .../gcc.target/riscv/target-attr-bad-05.c |  13 +
 .../gcc.target/riscv/target-attr-b

[PATCH v1 3/4] RISC-V: Extend riscv_subset_list, preparatory for target attribute support

[Kito Cheng]

riscv_subset_list only accept a full arch string before, but we need to
parse single extension when supporting target attribute, also we may set
a riscv_subset_list directly rather than re-parsing the ISA string
again.

gcc/ChangeLog:

* config/riscv/riscv-subset.h (riscv_subset_list::parse_single_std_ext):
New.
(riscv_subset_list::parse_single_multiletter_ext): Ditto.
(riscv_subset_list::clone): Ditto.
(riscv_subset_list::parse_single_ext): Ditto.
(riscv_subset_list::set_loc): Ditto.
(riscv_set_arch_by_subset_list): Ditto.
* common/config/riscv/riscv-common.cc
(riscv_subset_list::parse_single_std_ext): New.
(riscv_subset_list::parse_single_multiletter_ext): Ditto.
(riscv_subset_list::clone): Ditto.
(riscv_subset_list::parse_single_ext): Ditto.
(riscv_subset_list::set_loc): Ditto.
(riscv_set_arch_by_subset_list): Ditto.
---
 gcc/common/config/riscv/riscv-common.cc | 210 
 gcc/config/riscv/riscv-subset.h |  11 ++
 2 files changed, 221 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 9a0a68fe5db..76a1378874d 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1036,6 +1036,41 @@ riscv_subset_list::parse_std_ext (const char *p)
   return p;
 }
 
+/* Parsing function for one standard extensions.
+
+   Return Value:
+ Points to the end of extensions.
+
+   Arguments:
+ `p`: Current parsing position.  */
+
+const char *
+riscv_subset_list::parse_single_std_ext (const char *p)
+{
+  if (*p == 'x' || *p == 's' || *p == 'z')
+{
+  error_at (m_loc,
+   "%<-march=%s%>: Not single-letter extension. "
+   "%<%c%>",
+   m_arch, *p);
+  return nullptr;
+}
+
+  unsigned major_version = 0;
+  unsigned minor_version = 0;
+  bool explicit_version_p = false;
+  char subset[2] = {0, 0};
+
+  subset[0] = *p;
+
+  p++;
+
+  p = parsing_subset_version (subset, p, &major_version, &minor_version,
+ /* std_ext_p= */ true, &explicit_version_p);
+
+  add (subset, major_version, minor_version, explicit_version_p, false);
+  return p;
+}
 
 /* Check any implied extensions for EXT.  */
 void
@@ -1138,6 +1173,109 @@ riscv_subset_list::handle_combine_ext ()
 }
 }
 
+/* Parsing function for multi-letter extensions.
+
+   Return Value:
+ Points to the end of extensions.
+
+   Arguments:
+ `p`: Current parsing position.
+ `ext_type`: What kind of extensions, 's', 'z' or 'x'.
+ `ext_type_str`: Full name for kind of extension.  */
+
+
+const char *
+riscv_subset_list::parse_single_multiletter_ext (const char *p,
+const char *ext_type,
+const char *ext_type_str)
+{
+  unsigned major_version = 0;
+  unsigned minor_version = 0;
+  size_t ext_type_len = strlen (ext_type);
+
+{
+  if (strncmp (p, ext_type, ext_type_len) != 0)
+   return NULL;
+
+  char *subset = xstrdup (p);
+  char *q = subset;
+  const char *end_of_version;
+  bool explicit_version_p = false;
+  char *ext;
+  char backup;
+  size_t len;
+  size_t end_of_version_pos, i;
+  bool found_any_number = false;
+  bool found_minor_version = false;
+
+  backup = *q;
+  *q = '\0';
+  len = q - subset;
+  *q = backup;
+
+  end_of_version_pos = len;
+  /* Find the begin of version string.  */
+  for (i = len -1; i > 0; --i)
+   {
+ if (ISDIGIT (subset[i]))
+   {
+ found_any_number = true;
+ continue;
+   }
+ /* Might be version seperator, but need to check one more char,
+we only allow p, so we could stop parsing if found
+any more `p`.  */
+ if (subset[i] == 'p' &&
+ !found_minor_version &&
+ found_any_number && ISDIGIT (subset[i-1]))
+   {
+ found_minor_version = true;
+ continue;
+   }
+
+ end_of_version_pos = i + 1;
+ break;
+   }
+
+  backup = subset[end_of_version_pos];
+  subset[end_of_version_pos] = '\0';
+  ext = xstrdup (subset);
+  subset[end_of_version_pos] = backup;
+
+  end_of_version
+   = parsing_subset_version (ext, subset + end_of_version_pos, 
&major_version, &minor_version,
+ /* std_ext_p= */ false, &explicit_version_p);
+  free (ext);
+
+  if (end_of_version == NULL)
+   return NULL;
+
+  subset[end_of_version_pos] = '\0';
+
+  if (strlen (subset) == 1)
+   {
+ error_at (m_loc, "%<-march=%s%>: name of %s must be more than 1 
letter",
+   m_arch, ext_type_str);
+ free (subset);
+ return NULL;
+   }
+
+  add (subset, major_version, minor_ver

Re:

[Kito Cheng]

Ooop, I screwed up when writing my cover letter of the target
attribute patch set...

On Tue, Oct 3, 2023 at 5:10 PM Kito Cheng  wrote:
>
> From: Kito Cheng 
>
> Reply-To:
>
> Subject: [PATCH v1 0/4] RISC-V target attribute
>
> In-Reply-To:
>
> This patch set implement target attribute for RISC-V target, which is similar 
> to other target like x86 or ARM, let user able to set some local setting per 
> function without changing global settings.
>
> We support arch, tune and cpu first, and we will support other target 
> attribute later, this version DOES NOT include multi-version function support 
> yet, that is future work, probably work for GCC 15.
>
> The full proposal is put in RISC-V C-API document[1], which has discussed 
> with RISC-V LLVM community, so we have consistent syntax and semantics.
>
> [1] https://github.com/riscv-non-isa/riscv-c-api-doc/pull/35
>
>

Re: [PATCH] RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512.

[Kito Cheng]

钟居哲 於 2023年10月4日 週三，20:20寫道：
>
> I think the "max poly value" is the LMUL 1 mode coeffs[1]
>
> See int vlenb = BYTES_PER_RISCV_VECTOR.coeffs[1];
>
> So I think bump max_power to exact_log2 (64); is not enough.
> since we adjust the LMUL 1 mode size according to TARGET_MIN_VLEN.
>
> I suspect the testcase you append in this patch will fail with 
> -march=rv64gcv_zvl4096b.


There is no type smaller than  [64, 64] in zvl4096b, RVVMF64BI is [64,
64], it’s smallest type, and RVVFM1BI is [512, 512] (size of single
vector reg.) which at most 64x for zvl4096b, so my understanding is
log2(64) is enough :)

and of cause, verified the testcase is work with -march=rv64gcv_zvl4096b

Re: [PATCH] options: Prevent multidimensional arrays

[Kito Cheng]

committed to trunk, got approval from Jeff in another mail thread:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/631873.html :)

On Mon, Oct 2, 2023 at 4:03 PM Kito Cheng  wrote:
>
> Multidimensional arrary is gawk extension, and we accidentally
> introduced that in recent commit[1].
>
> [1] 
> https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=e4a4b8e983bac865eb435b11798e38d633b98942
>
> gcc/ChangeLog:
>
> * opt-read.awk: Drop multidimensional arrays.
> * opth-gen.awk: Ditto.
> ---
>  gcc/opt-read.awk | 4 ++--
>  gcc/opth-gen.awk | 8 
>  2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/gcc/opt-read.awk b/gcc/opt-read.awk
> index fcf92853957..f74d8478f72 100644
> --- a/gcc/opt-read.awk
> +++ b/gcc/opt-read.awk
> @@ -123,7 +123,7 @@ BEGIN {
> }
> else {
> target_var = opt_args("Var", $0)
> -if (target_var)
> +   if (target_var)
> {
> target_var = opt_args("Var", $1)
> var_index = find_index(target_var, 
> target_vars, n_target_vars)
> @@ -131,7 +131,7 @@ BEGIN {
> {
> target_vars[n_target_vars++] 
> = target_var
> }
> -   
> other_masks[var_index][n_other_mask[var_index]++] = name
> +   other_masks[var_index "," 
> n_other_mask[var_index]++] = name
> }
> else
> {
> diff --git a/gcc/opth-gen.awk b/gcc/opth-gen.awk
> index 70ca3d37719..c4398be2f3a 100644
> --- a/gcc/opth-gen.awk
> +++ b/gcc/opth-gen.awk
> @@ -412,9 +412,9 @@ for (i = 0; i < n_target_vars; i++)
> continue
> for (j = 0; j < n_other_mask[i]; j++)
> {
> -   print "#define MASK_" other_masks[i][j] " (1U << " 
> other_masknum[i][""]++ ")"
> +   print "#define MASK_" other_masks[i "," j] " (1U << " 
> other_masknum[i]++ ")"
> }
> -   if (other_masknum[i][""] > 32)
> +   if (other_masknum[i] > 32)
> print "#error too many target masks for" extra_target_vars[i]
>  }
>
> @@ -437,8 +437,8 @@ for (i = 0; i < n_target_vars; i++)
> continue
> for (j = 0; j < n_other_mask[i]; j++)
> {
> -   print "#define TARGET_" other_masks[i][j] \
> - " ((" target_vars[i] " & MASK_" other_masks[i][j] ") != 
> 0)"
> +   print "#define TARGET_" other_masks[i "," j] \
> + " ((" target_vars[i] " & MASK_" other_masks[i "," j] ") 
> != 0)"
> }
>  }
>  print ""
> --
> 2.40.1
>

Re: [PATCH] RISC-V: THead: Fix missing CFI directives for th.sdd in prologue.

[Kito Cheng]

LGTM, will commit if nobody commit that tomorrow :p

Christoph Müllner 於 2023年10月4日 週三，23:04寫道：

> On Wed, Oct 4, 2023 at 9:49 AM Xianmiao Qu 
> wrote:
> >
> > From: quxm 
> >
> > When generating CFI directives for the store-pair instruction,
> > if we add two parallel REG_FRAME_RELATED_EXPR expr_lists like
> >   (expr_list:REG_FRAME_RELATED_EXPR (set (mem/c:DI (plus:DI (reg/f:DI 2
> sp)
> > (const_int 8 [0x8])) [1  S8 A64])
> > (reg:DI 1 ra))
> >   (expr_list:REG_FRAME_RELATED_EXPR (set (mem/c:DI (reg/f:DI 2 sp) [1
> S8 A64])
> > (reg:DI 8 s0))
> > only the first expr_list will be recognized by dwarf2out_frame_debug
> > funciton. So, here we generate a SEQUENCE expression of
> REG_FRAME_RELATED_EXPR,
> > which includes two sub-expressions of RTX_FRAME_RELATED_P. Then the
> > dwarf2out_frame_debug_expr function will iterate through all the
> sub-expressions
> > and generate the corresponding CFI directives.
> >
> > gcc/
> > * config/riscv/thead.cc (th_mempair_save_regs): Fix missing CFI
> > directives for store-pair instruction.
> >
> > gcc/testsuite/
> > * gcc.target/riscv/xtheadmempair-4.c: New test.
>
> LGTM, I've also tested it.
>
> Reviewed-by: Christoph Müllner 
> Tested-by: Christoph Müllner 
>
> Thanks!
>
> > ---
> >  gcc/config/riscv/thead.cc | 11 +++
> >  .../gcc.target/riscv/xtheadmempair-4.c| 29 +++
> >  2 files changed, 35 insertions(+), 5 deletions(-)
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-4.c
> >
> > diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc
> > index 507c912bc39..be0cd7c1276 100644
> > --- a/gcc/config/riscv/thead.cc
> > +++ b/gcc/config/riscv/thead.cc
> > @@ -366,14 +366,15 @@ th_mempair_save_regs (rtx operands[4])
> >  {
> >rtx set1 = gen_rtx_SET (operands[0], operands[1]);
> >rtx set2 = gen_rtx_SET (operands[2], operands[3]);
> > +  rtx dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (2));
> >rtx insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set1,
> set2)));
> >RTX_FRAME_RELATED_P (insn) = 1;
> >
> > -  REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
> > - copy_rtx (set1), REG_NOTES (insn));
> > -
> > -  REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
> > - copy_rtx (set2), REG_NOTES (insn));
> > +  XVECEXP (dwarf, 0, 0) = copy_rtx (set1);
> > +  XVECEXP (dwarf, 0, 1) = copy_rtx (set2);
> > +  RTX_FRAME_RELATED_P (XVECEXP (dwarf, 0, 0)) = 1;
> > +  RTX_FRAME_RELATED_P (XVECEXP (dwarf, 0, 1)) = 1;
> > +  add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf);
> >  }
> >
> >  /* Similar like riscv_restore_reg, but restores two registers from
> memory
> > diff --git a/gcc/testsuite/gcc.target/riscv/xtheadmempair-4.c
> b/gcc/testsuite/gcc.target/riscv/xtheadmempair-4.c
> > new file mode 100644
> > index 000..9aef4e15f8d
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/riscv/xtheadmempair-4.c
> > @@ -0,0 +1,29 @@
> > +/* { dg-do compile } */
> > +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-g" "-Oz" "-Os" "-flto" } }
> */
> > +/* { dg-options "-march=rv64gc_xtheadmempair -mtune=thead-c906
> -funwind-tables" { target { rv64 } } } */
> > +/* { dg-options "-march=rv32gc_xtheadmempair -mtune=thead-c906
> -funwind-tables" { target { rv32 } } } */
> > +
> > +extern void bar (void);
> > +
> > +void foo (void)
> > +{
> > +  asm volatile (";my clobber list"
> > +   : : : "s0");
> > +  bar ();
> > +  asm volatile (";my clobber list"
> > +   : : : "s0");
> > +}
> > +
> > +/* { dg-final { scan-assembler-times "th.sdd\t" 1 { target { rv64 } } }
> } */
> > +/* { dg-final { scan-assembler ".cfi_offset 8, -16" { target { rv64 } }
> } } */
> > +/* { dg-final { scan-assembler ".cfi_offset 1, -8" { target { rv64 } }
> } } */
> > +
> > +/* { dg-final { scan-assembler-times "th.swd\t" 1 { target { rv32 } } }
> } */
> > +/* { dg-final { scan-assembler ".cfi_offset 8, -8" { target { rv32 } }
> } } */
> > +/* { dg-final { scan-assembler ".cfi_offset 1, -4" { target { rv32 } }
> } } */
> > +
> > +/* { dg-final { scan-assembler ".cfi_restore 1" } } */
> > +/* { dg-final { scan-assembler ".cfi_restore 8" } } */
> > +
> > +/* { dg-final { scan-assembler-times "th.ldd\t" 1 { target { rv64 } } }
> } */
> > +/* { dg-final { scan-assembler-times "th.lwd\t" 1 { target { rv32 } } }
> } */
> > --
> > 2.17.1
> >
>

Re: [PATCH] RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512.

[Kito Cheng]

Hi Robin:

Your suggested code seems work fine, let me run more test and send v2, I
guess I just don’t know how to explain why it work in comment :p

Robin Dapp 於 2023年10月5日 週四，03:57寫道：

> >> I think the "max poly value" is the LMUL 1 mode coeffs[1]
> >>
> >> See int vlenb = BYTES_PER_RISCV_VECTOR.coeffs[1];
> >>
> >> So I think bump max_power to exact_log2 (64); is not enough.
> >> since we adjust the LMUL 1 mode size according to TARGET_MIN_VLEN.
> >>
> >> I suspect the testcase you append in this patch will fail with
> -march=rv64gcv_zvl4096b.
> >
> >
> > There is no type smaller than  [64, 64] in zvl4096b, RVVMF64BI is [64,
> > 64], it’s smallest type, and RVVFM1BI is [512, 512] (size of single
> > vector reg.) which at most 64x for zvl4096b, so my understanding is
> > log2(64) is enough :)
> >
> > and of cause, verified the testcase is work with -march=rv64gcv_zvl4096b
>
> I was wondering if the whole hunk couldn't be condensed into something
> like (untested):
>
>   div_factor = wi::ctz (factor) - wi::ctz (vlenb);
>   if (div_factor >= 0)
> div_factor = 1;
>   else
> div_factor = 1 << -div_factor;
>
> This would avoid the loop as well.  An assert for the div_factor (not
> exceeding a value) could still be added.
>
> Regards
>  Robin
>

Re: [PATCH v2] RISC-V: Use stdint-gcc.h in rvv testsuite

[Kito Cheng]

LGTM

Patrick O'Neill  於 2023年10月6日 週五 07:46 寫道：

> stdint.h can be replaced with stdint-gcc.h to resolve some missing
> system headers in non-multilib installations.
>
> Tested using glibc rv32gcv and rv64gcv on r14-4381-g7eb5ce7f58e.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-1.h:
> Replace stdint.h with stdint-gcc.h.
> * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-2.h:
> Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-1.h:
> Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-2.h:
> Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-1.h:
> Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-2.h:
> Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-1.h:
> Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-2.h:
> Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c: Ditto.
> * gcc.target/riscv/rvv/autovec/partial/slp-8.c: Ditto.
> * gcc.target/riscv/rvv/autovec/partial/slp-9.c: Ditto.
> * gcc.target/riscv/rvv/autovec/pr111232.c: Ditto.
> * gcc.target/riscv/rvv/autovec/unop/cvt-0.c: Ditto.
> * gcc.target/riscv/rvv/autovec/unop/cvt-1.c: Ditto.
> * gcc.target/riscv/rvv/autovec/vls-vlmax/perm.h: Ditto.
> * gcc.target/riscv/rvv/base/abi-call-args-4-run.c: Ditto.
> * gcc.target/riscv/rvv/base/pr110119-2.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/pr111255.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c: Ditto.
>
> Signed-off-by: Patrick O'Neill 
> ---
> Changes from v1:
> - Avoid changing riscv_vector.h
>
> Failures looked like this:
> In file included from
> /riscv-gnu-toolchain/build/sysroot/usr/include/features.h:515,
>   from
> /riscv-gnu-toolchain/build/sysroot/usr/include/bits/libc-header-start.h:33,
>   from
> /riscv-gnu-toolchain/build/sysroot/usr/include/stdint.h:26,
>   from
> /riscv-gnu-toolchain/build/lib/gcc/riscv32-unknown-linux-gnu/14.0.0/include/stdint.h:9,
>   from
> /riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/include/stdint.h:9,
>   from
> /riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/include/riscv_vector.h:28,
>   from
> /riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c:4:
> /riscv-gnu-toolchain/build/sysroot/usr/include/gnu/stubs.h:8:11: fatal
> error: gnu/stubs-ilp32.h: No such file or directory
>
> Resolves these failures on rv32gcv (non-multilib):
> FAIL: gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c
> (test for excess errors)
> FAIL: gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c
> (test for excess errors)
> FAIL: gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c
> (test for excess errors)
> FAIL: gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c
> (test for excess errors)
> FAIL: gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c
> (test for excess errors)
> FAIL: gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c
> (test for excess errors)
> FAIL: gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c
> (test for excess errors)
> FAIL: gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c
> (test for excess errors)
> FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c (test for excess
> errors)
> FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c (test for excess
> errors)
> FAIL: gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c (test for excess
> errors)
> FAIL: gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c (test for excess
> errors)
> FAIL: gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c (test for excess
> errors)
> FAIL: gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c (test for excess
> errors)
> FAIL: gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c (test for excess
> errors)
> FAIL: gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c (test for excess
> errors)
> FAIL: gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c (test for excess
> errors)
> FAIL: gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c (test for excess
> errors)
> FAI

Re: [PATCH v1] RISC-V: Update comments for FP rounding related autovec

[Kito Cheng]

LGTM

 於 2023年10月6日 週五 10:39 寫道：

> From: Pan Li 
>
> Some comment is out of date, this patch would like to fix it.
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md: Update comments.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/config/riscv/autovec.md | 6 +-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index 056f2c352f6..53e9d34eea1 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -2229,12 +2229,16 @@ (define_expand "avg3_ceil"
>  })
>
>  ;;
> -
> -;;  [FP] Math.h.
> +;;  [FP] Rounding.
>  ;;
> -
>  ;; Includes:
>  ;; - ceil/ceilf
>  ;; - floor/floorf
>  ;; - nearbyint/nearbyintf
> +;; - rint/rintf
> +;; - round/roundf
> +;; - trunc/truncf
> +;; - roundeven/roundevenf
>  ;;
> -
>  (define_expand "ceil2"
>[(match_operand:V_VLSF 0 "register_operand")
> --
> 2.34.1
>
>

Re: [PATCH v1 1/4] options: Define TARGET__P and TARGET__OPTS_P macro for Mask and InverseMask

[Kito Cheng]

> Doesn't this need to be updated to avoid multi-dimensional arrays in awk
> and rebased?

Oh, yeah, I should update that, it's post before that issue reported,
let me send v2 sn :P

Re: [PATCH] RISC-V: Make xtheadcondmov-indirect tests robust against instruction reordering

[Kito Cheng]

I guess you may also want to clean up those bodies for "check-function-bodies"?

On Mon, Oct 9, 2023 at 3:47 PM Christoph Muellner
 wrote:
>
> From: Christoph Müllner 
>
> Fixes: c1bc7513b1d7 ("RISC-V: const: hide mvconst splitter from IRA")
>
> A recent change broke the xtheadcondmov-indirect tests, because the order of
> emitted instructions changed. Since the test is too strict when testing for
> a fixed instruction order, let's change the tests to simply count instruction,
> like it is done for similar tests.
>
> Reported-by: Patrick O'Neill 
> Signed-off-by: Christoph Müllner 
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/xtheadcondmov-indirect.c: Make robust against
> instruction reordering.
>
> Signed-off-by: Christoph Müllner 
> ---
>  .../gcc.target/riscv/xtheadcondmov-indirect.c | 11 ---
>  1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect.c 
> b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect.c
> index c3253ba5239..eba1b86137b 100644
> --- a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect.c
> +++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect.c
> @@ -1,8 +1,7 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv32gc_xtheadcondmov -fno-sched-pressure" { target { 
> rv32 } } } */
> -/* { dg-options "-march=rv64gc_xtheadcondmov -fno-sched-pressure" { target { 
> rv64 } } } */
> +/* { dg-options "-march=rv32gc_xtheadcondmov" { target { rv32 } } } */
> +/* { dg-options "-march=rv64gc_xtheadcondmov" { target { rv64 } } } */
>  /* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */
> -/* { dg-final { check-function-bodies "**" "" } } */
>
>  /*
>  ** ConEmv_imm_imm_reg:
> @@ -116,3 +115,9 @@ int ConNmv_reg_reg_reg(int x, int y, int z, int n)
>  return z;
>return n;
>  }
> +
> +/* { dg-final { scan-assembler-times "addi\t" 5 } } */
> +/* { dg-final { scan-assembler-times "li\t" 4 } } */
> +/* { dg-final { scan-assembler-times "sub\t" 4 } } */
> +/* { dg-final { scan-assembler-times "th.mveqz\t" 4 } } */
> +/* { dg-final { scan-assembler-times "th.mvnez\t" 4 } } */
> --
> 2.41.0
>

Re: [PATCH] RISC-V: Add available vector size for RVV

[Kito Cheng]

LGTM

On Mon, Oct 9, 2023 at 4:23 PM Juzhe-Zhong  wrote:
>
> For RVV, we have VLS modes enable according to TARGET_MIN_VLEN
> from M1 to M8.
>
> For example, when TARGET_MIN_VLEN = 128 bits, we enable
> 128/256/512/1024 bits VLS modes.
>
> This patch fixes following FAIL:
> FAIL: gcc.dg/vect/bb-slp-subgroups-2.c -flto -ffat-lto-objects  
> scan-tree-dump-times slp2 "optimized: basic block" 2
> FAIL: gcc.dg/vect/bb-slp-subgroups-2.c scan-tree-dump-times slp2 "optimized: 
> basic block" 2
>
> gcc/testsuite/ChangeLog:
>
> * lib/target-supports.exp: Add 256/512/1024
>
> ---
>  gcc/testsuite/lib/target-supports.exp | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/testsuite/lib/target-supports.exp 
> b/gcc/testsuite/lib/target-supports.exp
> index af52c38433d..dc366d35a0a 100644
> --- a/gcc/testsuite/lib/target-supports.exp
> +++ b/gcc/testsuite/lib/target-supports.exp
> @@ -8881,7 +8881,7 @@ proc available_vector_sizes { } {
> lappend result 4096 2048 1024 512 256 128 64 32 16 8 4 2
>  } elseif { [istarget riscv*-*-*] } {
> if { [check_effective_target_riscv_v] } {
> -   lappend result 0 32 64 128
> +   lappend result 0 32 64 128 256 512 1024
> }
> lappend result 128
>  } else {
> --
> 2.36.3
>

[PATCH v2 0/4] RISC-V target attribute

[Kito Cheng]

This patch set implement target attribute for RISC-V target, which is similar 
to other target like x86 or ARM, let user able to set some local setting per 
function without changing global settings.

We support arch, tune and cpu first, and we will support other target attribute 
later, this version DOES NOT include multi-version function support yet, that 
is future work, probably work for GCC 15.

The full proposal is put in RISC-V C-API document[1], which has discussed with 
RISC-V LLVM community, so we have consistent syntax and semantics. 

[1] https://github.com/riscv-non-isa/riscv-c-api-doc/pull/35

v2 changelog:
- Resolve awk multi-dimensional issue.
- Tweak code format
- Tweak testcases

[PATCH v2 1/4] options: Define TARGET__P and TARGET__OPTS_P macro for Mask and InverseMask

[Kito Cheng]

We TARGET__P marcro to test a Mask and InverseMask with user
specified target_variable, however we may want to test with specific
gcc_options variable rather than target_variable.

Like RISC-V has defined lots of Mask with TargetVariable, which is not
easy to use, because that means we need to known which Mask are associate with
which TargetVariable, so take a gcc_options variable is a better interface
for such use case.

gcc/ChangeLog:

* doc/options.texi (Mask): Document TARGET__P and
TARGET__OPTS_P.
(InverseMask): Ditto.
* opth-gen.awk (Mask): Generate TARGET__P and
TARGET__OPTS_P macro.
(InverseMask): Ditto.
---
 gcc/doc/options.texi | 23 ---
 gcc/opth-gen.awk | 13 -
 2 files changed, 28 insertions(+), 8 deletions(-)

diff --git a/gcc/doc/options.texi b/gcc/doc/options.texi
index 1f7c15b8eb4..715f0a1479c 100644
--- a/gcc/doc/options.texi
+++ b/gcc/doc/options.texi
@@ -404,18 +404,27 @@ You may also specify @code{Var} to select a variable 
other than
 The options-processing script will automatically allocate a unique bit
 for the option.  If the option is attached to @samp{target_flags} or @code{Var}
 which is defined by @code{TargetVariable},  the script will set the macro
-@code{MASK_@var{name}} to the appropriate bitmask.  It will also declare a 
-@code{TARGET_@var{name}} macro that has the value 1 when the option is active
-and 0 otherwise.  If you use @code{Var} to attach the option to a different 
variable
-which is not defined by @code{TargetVariable}, the bitmask macro with be
-called @code{OPTION_MASK_@var{name}}.
+@code{MASK_@var{name}} to the appropriate bitmask.  It will also declare a
+@code{TARGET_@var{name}}, @code{TARGET_@var{name}_P} and
+@code{TARGET_@var{name}_OPTS_P}: @code{TARGET_@var{name}} macros that has the
+value 1 when the option is active and 0 otherwise, @code{TARGET_@var{name}_P} 
is
+similar to @code{TARGET_@var{name}} but take an argument as @samp{target_flags}
+or @code{TargetVariable}, and @code{TARGET_@var{name}_OPTS_P} also similar to
+@code{TARGET_@var{name}} but take an argument as @code{gcc_options}.
+If you use @code{Var} to attach the option to a different variable which is not
+defined by @code{TargetVariable}, the bitmask macro with be called
+@code{OPTION_MASK_@var{name}}.
 
 @item InverseMask(@var{othername})
 @itemx InverseMask(@var{othername}, @var{thisname})
 The option is the inverse of another option that has the
 @code{Mask(@var{othername})} property.  If @var{thisname} is given,
-the options-processing script will declare a @code{TARGET_@var{thisname}}
-macro that is 1 when the option is active and 0 otherwise.
+the options-processing script will declare @code{TARGET_@var{thisname}},
+@code{TARGET_@var{name}_P} and @code{TARGET_@var{name}_OPTS_P} macros:
+@code{TARGET_@var{thisname}} is 1 when the option is active and 0 otherwise,
+@code{TARGET_@var{name}_P} is similar to @code{TARGET_@var{name}} but take an
+argument as @samp{target_flags}, and and @code{TARGET_@var{name}_OPTS_P} also
+similar to @code{TARGET_@var{name}} but take an argument as @code{gcc_options}.
 
 @item Enum(@var{name})
 The option's argument is a string from the set of strings associated
diff --git a/gcc/opth-gen.awk b/gcc/opth-gen.awk
index c4398be2f3a..26551575d55 100644
--- a/gcc/opth-gen.awk
+++ b/gcc/opth-gen.awk
@@ -439,6 +439,10 @@ for (i = 0; i < n_target_vars; i++)
{
print "#define TARGET_" other_masks[i "," j] \
  " ((" target_vars[i] " & MASK_" other_masks[i "," j] ") 
!= 0)"
+   print "#define TARGET_" other_masks[i "," j] "_P(" 
target_vars[i] ")" \
+ " (((" target_vars[i] ") & MASK_" other_masks[i "," j] ") 
!= 0)"
+   print "#define TARGET_" other_masks[i "," j] "_OPTS_P(opts)" \
+ " (((opts->x_" target_vars[i] ") & MASK_" other_masks[i 
"," j] ") != 0)"
}
 }
 print ""
@@ -469,15 +473,22 @@ for (i = 0; i < n_opts; i++) {
  " ((" vname " & " mask original_name ") != 0)"
print "#define TARGET_" name "_P(" vname ")" \
  " (((" vname ") & " mask original_name ") != 0)"
+   print "#define TARGET_" name "_OPTS_P(opts)" \
+ " (((opts->x_" vname ") & " mask original_name ") != 0)"
print "#define TARGET_EXPLICIT_" name "_P(opts)" \
  " ((opts->x_" vname "_explicit & " mask original_name ") 
!= 0)"
print "#define SET_TARGET_" name "(opts) opts->x_" vname " |= " 
mask original_name
}
 }
 for (i = 0; i < n_extra_masks; i++) {
-   if (extra_mask_macros[extra_masks[i]] == 0)
+   if (extra_mask_macros[extra_masks[i]] == 0) {
print "#define TARGET_" extra_masks[i] \
  " ((target_flags & MASK_" extra_masks[i] ") != 0)"
+   print "#define TARGET_" extra_masks[i] "_P(target_flags)" \
+   

[PATCH v2 2/4] RISC-V: Refactor riscv_option_override and riscv_convert_vector_bits. [NFC]

[Kito Cheng]

Allow those funciton apply from a local gcc_options rather than the
global options.

Preparatory for target attribute, sperate this change for eaiser reivew
since it's a NFC.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_convert_vector_bits): Get setting
from argument rather than get setting from global setting.
(riscv_override_options_internal): New, splited from
riscv_override_options, also take a gcc_options argument.
(riscv_option_override): Splited most part to
riscv_override_options_internal.
---
 gcc/config/riscv/riscv.cc | 93 ++-
 1 file changed, 52 insertions(+), 41 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index b7acf836d02..c7d0d300345 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8066,10 +8066,11 @@ riscv_init_machine_status (void)
 /* Return the VLEN value associated with -march.
TODO: So far we only support length-agnostic value. */
 static poly_uint16
-riscv_convert_vector_bits (void)
+riscv_convert_vector_bits (struct gcc_options *opts)
 {
   int chunk_num;
-  if (TARGET_MIN_VLEN > 32)
+  int min_vlen = TARGET_MIN_VLEN_OPTS (opts);
+  if (min_vlen > 32)
 {
   /* When targetting minimum VLEN > 32, we should use 64-bit chunk size.
 Otherwise we can not include SEW = 64bits.
@@ -8087,7 +8088,7 @@ riscv_convert_vector_bits (void)
   - TARGET_MIN_VLEN = 2048bit: [256,256]
   - TARGET_MIN_VLEN = 4096bit: [512,512]
   FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096bit.  */
-  chunk_num = TARGET_MIN_VLEN / 64;
+  chunk_num = min_vlen / 64;
 }
   else
 {
@@ -8106,10 +8107,10 @@ riscv_convert_vector_bits (void)
  to set RVV mode size. The RVV machine modes size are run-time constant if
  TARGET_VECTOR is enabled. The RVV machine modes size remains default
  compile-time constant if TARGET_VECTOR is disabled.  */
-  if (TARGET_VECTOR)
+  if (TARGET_VECTOR_OPTS_P (opts))
 {
-  if (riscv_autovec_preference == RVV_FIXED_VLMAX)
-   return (int) TARGET_MIN_VLEN / (riscv_bytes_per_vector_chunk * 8);
+  if (opts->x_riscv_autovec_preference == RVV_FIXED_VLMAX)
+   return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8);
   else
return poly_uint16 (chunk_num, chunk_num);
 }
@@ -8117,40 +8118,33 @@ riscv_convert_vector_bits (void)
 return 1;
 }
 
-/* Implement TARGET_OPTION_OVERRIDE.  */
-
-static void
-riscv_option_override (void)
+/* 'Unpack' up the internal tuning structs and update the options
+in OPTS.  The caller must have set up selected_tune and selected_arch
+as all the other target-specific codegen decisions are
+derived from them.  */
+void
+riscv_override_options_internal (struct gcc_options *opts)
 {
   const struct riscv_tune_info *cpu;
 
-#ifdef SUBTARGET_OVERRIDE_OPTIONS
-  SUBTARGET_OVERRIDE_OPTIONS;
-#endif
-
-  flag_pcc_struct_return = 0;
-
-  if (flag_pic)
-g_switch_value = 0;
-
   /* The presence of the M extension implies that division instructions
  are present, so include them unless explicitly disabled.  */
-  if (TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0)
-target_flags |= MASK_DIV;
-  else if (!TARGET_MUL && TARGET_DIV)
+  if (TARGET_MUL_OPTS_P (opts) && (target_flags_explicit & MASK_DIV) == 0)
+opts->x_target_flags |= MASK_DIV;
+  else if (!TARGET_MUL_OPTS_P (opts) && TARGET_DIV_OPTS_P (opts))
 error ("%<-mdiv%> requires %<-march%> to subsume the % extension");
 
   /* Likewise floating-point division and square root.  */
   if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (target_flags_explicit & 
MASK_FDIV) == 0)
-target_flags |= MASK_FDIV;
+opts->x_target_flags |= MASK_FDIV;
 
   /* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune
  if both -mtune and -mcpu are not given.  */
-  cpu = riscv_parse_tune (riscv_tune_string ? riscv_tune_string :
- (riscv_cpu_string ? riscv_cpu_string :
+  cpu = riscv_parse_tune (opts->x_riscv_tune_string ? 
opts->x_riscv_tune_string :
+ (opts->x_riscv_cpu_string ? opts->x_riscv_cpu_string :
   RISCV_TUNE_STRING_DEFAULT));
   riscv_microarchitecture = cpu->microarchitecture;
-  tune_param = optimize_size ? &optimize_size_tune_info : cpu->tune_param;
+  tune_param = opts->x_optimize_size ? &optimize_size_tune_info : 
cpu->tune_param;
 
   /* Use -mtune's setting for slow_unaligned_access, even when optimizing
  for size.  For architectures that trap and emulate unaligned accesses,
@@ -8166,15 +8160,38 @@ riscv_option_override (void)
 
   if ((target_flags_explicit & MASK_STRICT_ALIGN) == 0
   && cpu->tune_param->slow_unaligned_access)
-target_flags |= MASK_STRICT_ALIGN;
+opts->x_target_flags |= MASK_STRICT_ALIGN;
 
   /* If the user hasn't specified a branch cost, use the processor's
  default.  */
-  if (riscv_branch_c

[PATCH v2 4/4] RISC-V: Implement target attribute

[Kito Cheng]

The target attribute which proposed in [1], target attribute allow user
to specify a local setting per-function basis.

The syntax of target attribute is `__attribute__((target("")))`.

and the syntax of `` describes below:
```
ATTR-STRING := ATTR-STRING ';' ATTR
 | ATTR

ATTR:= ARCH-ATTR
 | CPU-ATTR
 | TUNE-ATTR

ARCH-ATTR   := 'arch=' EXTENSIONS-OR-FULLARCH

EXTENSIONS-OR-FULLARCH := 
| 

EXTENSIONS :=  ',' 
| 

FULLARCHSTR:= 

EXTENSION  :=   

OP := '+'

VERSION:= [0-9]+ 'p' [0-9]+
| [1-9][0-9]*
|

EXTENSION-NAME := Naming rule is defined in RISC-V ISA manual

CPU-ATTR:= 'cpu=' 
TUNE-ATTR   := 'tune=' 
```

[1] https://github.com/riscv-non-isa/riscv-c-api-doc/pull/35

gcc/ChangeLog:

* config.gcc (riscv): Add riscv-target-attr.o.
* config/riscv/riscv-opts.h (TARGET_MIN_VLEN_OPTS): New.
* config/riscv/riscv-protos.h (riscv_declare_function_size) New.
(riscv_option_valid_attribute_p): New.
(riscv_override_options_internal): New.
(struct riscv_tune_info): New.
(riscv_parse_tune): New.
* config/riscv/riscv-target-attr.cc
(class riscv_target_attr_parser): New.
(struct riscv_attribute_info): New.
(riscv_attributes): New.
(riscv_target_attr_parser::parse_arch):
(riscv_target_attr_parser::handle_arch):
(riscv_target_attr_parser::handle_cpu):
(riscv_target_attr_parser::handle_tune):
(riscv_target_attr_parser::update_settings):
(riscv_process_one_target_attr):
(num_occurences_in_str):
(riscv_process_target_attr):
(riscv_option_valid_attribute_p):
* config/riscv/riscv.cc: Include target-globals.h and
riscv-subset.h.
(struct riscv_tune_info): Move to riscv-protos.h.
(get_tune_str):
(riscv_parse_tune):
(riscv_declare_function_size):
(riscv_option_override): Build target_option_default_node and
target_option_current_node.
(riscv_save_restore_target_globals):
(riscv_option_restore):
(riscv_previous_fndecl):
(riscv_set_current_function): Apply the target attribute.
(TARGET_OPTION_RESTORE): Define.
(TARGET_OPTION_VALID_ATTRIBUTE_P): Ditto.
* config/riscv/riscv.h (SWITCHABLE_TARGET): Define to 1.
(ASM_DECLARE_FUNCTION_SIZE) Define.
* config/riscv/riscv.opt (mtune=): Add Save attribute.
(mcpu=): Ditto.
(mcmodel=): Ditto.
* config/riscv/t-riscv: Add build rule for riscv-target-attr.o
* doc/extend.texi: Add doc for target attribute.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/target-attr-01.c: New.
* gcc.target/riscv/target-attr-02.c: Ditto.
* gcc.target/riscv/target-attr-03.c: Ditto.
* gcc.target/riscv/target-attr-04.c: Ditto.
* gcc.target/riscv/target-attr-05.c: Ditto.
* gcc.target/riscv/target-attr-06.c: Ditto.
* gcc.target/riscv/target-attr-07.c: Ditto.
* gcc.target/riscv/target-attr-bad-01.c: Ditto.
* gcc.target/riscv/target-attr-bad-02.c: Ditto.
* gcc.target/riscv/target-attr-bad-03.c: Ditto.
* gcc.target/riscv/target-attr-bad-04.c: Ditto.
* gcc.target/riscv/target-attr-bad-05.c: Ditto.
* gcc.target/riscv/target-attr-bad-06.c: Ditto.
* gcc.target/riscv/target-attr-bad-07.c: Ditto.
* gcc.target/riscv/target-attr-warning-01.c: Ditto.
* gcc.target/riscv/target-attr-warning-02.c: Ditto.
* gcc.target/riscv/target-attr-warning-03.c: Ditto.
---
 gcc/config.gcc|   2 +-
 gcc/config/riscv/riscv-opts.h |   6 +
 gcc/config/riscv/riscv-protos.h   |  21 +
 gcc/config/riscv/riscv-target-attr.cc | 395 ++
 gcc/config/riscv/riscv.cc | 192 +++--
 gcc/config/riscv/riscv.h  |   6 +
 gcc/config/riscv/riscv.opt|   6 +-
 gcc/config/riscv/t-riscv  |   5 +
 gcc/doc/extend.texi   |  58 +++
 .../gcc.target/riscv/target-attr-01.c |  31 ++
 .../gcc.target/riscv/target-attr-02.c |  31 ++
 .../gcc.target/riscv/target-attr-03.c |  26 ++
 .../gcc.target/riscv/target-attr-04.c |  28 ++
 .../gcc.target/riscv/target-attr-05.c |  27 ++
 .../gcc.target/riscv/target-attr-06.c |  27 ++
 .../gcc.target/riscv/target-attr-07.c |  25 ++
 .../gcc.target/riscv/target-attr-bad-01.c |  13 +
 .../gcc.target/riscv/target-attr-bad-02.c |  13 +
 .../gcc.target/riscv/target-attr-bad-03.c |  13 +
 .../gcc.target/riscv/target-attr-bad-04.c |  13 +
 .../gcc.target/riscv/target-attr-bad-05.c |  13 +
 .../gcc.target/riscv/target-attr-b

[PATCH v2 3/4] RISC-V: Extend riscv_subset_list, preparatory for target attribute support

[Kito Cheng]

riscv_subset_list only accept a full arch string before, but we need to
parse single extension when supporting target attribute, also we may set
a riscv_subset_list directly rather than re-parsing the ISA string
again.

gcc/ChangeLog:

* config/riscv/riscv-subset.h (riscv_subset_list::parse_single_std_ext):
New.
(riscv_subset_list::parse_single_multiletter_ext): Ditto.
(riscv_subset_list::clone): Ditto.
(riscv_subset_list::parse_single_ext): Ditto.
(riscv_subset_list::set_loc): Ditto.
(riscv_set_arch_by_subset_list): Ditto.
* common/config/riscv/riscv-common.cc
(riscv_subset_list::parse_single_std_ext): New.
(riscv_subset_list::parse_single_multiletter_ext): Ditto.
(riscv_subset_list::clone): Ditto.
(riscv_subset_list::parse_single_ext): Ditto.
(riscv_subset_list::set_loc): Ditto.
(riscv_set_arch_by_subset_list): Ditto.
---
 gcc/common/config/riscv/riscv-common.cc | 203 
 gcc/config/riscv/riscv-subset.h |  11 ++
 2 files changed, 214 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 9a0a68fe5db..25630d5923e 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1036,6 +1036,41 @@ riscv_subset_list::parse_std_ext (const char *p)
   return p;
 }
 
+/* Parsing function for one standard extensions.
+
+   Return Value:
+ Points to the end of extensions.
+
+   Arguments:
+ `p`: Current parsing position.  */
+
+const char *
+riscv_subset_list::parse_single_std_ext (const char *p)
+{
+  if (*p == 'x' || *p == 's' || *p == 'z')
+{
+  error_at (m_loc,
+   "%<-march=%s%>: Not single-letter extension. "
+   "%<%c%>",
+   m_arch, *p);
+  return nullptr;
+}
+
+  unsigned major_version = 0;
+  unsigned minor_version = 0;
+  bool explicit_version_p = false;
+  char subset[2] = {0, 0};
+
+  subset[0] = *p;
+
+  p++;
+
+  p = parsing_subset_version (subset, p, &major_version, &minor_version,
+ /* std_ext_p= */ true, &explicit_version_p);
+
+  add (subset, major_version, minor_version, explicit_version_p, false);
+  return p;
+}
 
 /* Check any implied extensions for EXT.  */
 void
@@ -1138,6 +1173,102 @@ riscv_subset_list::handle_combine_ext ()
 }
 }
 
+/* Parsing function for multi-letter extensions.
+
+   Return Value:
+ Points to the end of extensions.
+
+   Arguments:
+ `p`: Current parsing position.
+ `ext_type`: What kind of extensions, 's', 'z' or 'x'.
+ `ext_type_str`: Full name for kind of extension.  */
+
+
+const char *
+riscv_subset_list::parse_single_multiletter_ext (const char *p,
+const char *ext_type,
+const char *ext_type_str)
+{
+  unsigned major_version = 0;
+  unsigned minor_version = 0;
+  size_t ext_type_len = strlen (ext_type);
+
+  if (strncmp (p, ext_type, ext_type_len) != 0)
+return NULL;
+
+  char *subset = xstrdup (p);
+  const char *end_of_version;
+  bool explicit_version_p = false;
+  char *ext;
+  char backup;
+  size_t len = strlen (p);
+  size_t end_of_version_pos, i;
+  bool found_any_number = false;
+  bool found_minor_version = false;
+
+  end_of_version_pos = len;
+  /* Find the begin of version string.  */
+  for (i = len -1; i > 0; --i)
+{
+  if (ISDIGIT (subset[i]))
+   {
+ found_any_number = true;
+ continue;
+   }
+  /* Might be version seperator, but need to check one more char,
+we only allow p, so we could stop parsing if found
+any more `p`.  */
+  if (subset[i] == 'p' &&
+ !found_minor_version &&
+ found_any_number && ISDIGIT (subset[i-1]))
+   {
+ found_minor_version = true;
+ continue;
+   }
+
+  end_of_version_pos = i + 1;
+  break;
+}
+
+  backup = subset[end_of_version_pos];
+  subset[end_of_version_pos] = '\0';
+  ext = xstrdup (subset);
+  subset[end_of_version_pos] = backup;
+
+  end_of_version
+= parsing_subset_version (ext, subset + end_of_version_pos, &major_version,
+ &minor_version, /* std_ext_p= */ false,
+ &explicit_version_p);
+  free (ext);
+
+  if (end_of_version == NULL)
+return NULL;
+
+  subset[end_of_version_pos] = '\0';
+
+  if (strlen (subset) == 1)
+{
+  error_at (m_loc, "%<-march=%s%>: name of %s must be more than 1 letter",
+   m_arch, ext_type_str);
+  free (subset);
+  return NULL;
+}
+
+  add (subset, major_version, minor_version, explicit_version_p, false);
+  p += end_of_version - subset;
+  free (subset);
+
+  if (*p != '\0' && *p != '_')
+{
+  error_at (m_loc, "%<-march=%s%>: %s must separate with %<_%>",
+   m_arch, ext_type_str);
+  return NULL;
+}
+
+  re

Re: [PATCH v3 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions

[Kito Cheng]

Just repeat what I said on the mailing list again :P it's LGTM, just
need to rebase to deal with riscv.opt related changes :)


On Sat, Sep 30, 2023 at 8:02 PM Mary Bennett  wrote:
>
> Thank you for reviewing this patch.
>
> v1->v2:
>   * Add XCValu RTL.
>   * Change assembly mnemonics from mixed case to lower case.
>
> v2->v3:
>   * Change commit message from past tense to present.
>   * Add documentation for new dg-effective-targets.
>
> This patch series presents the comprehensive implementation of the MAC and ALU
> extension for CORE-V.
>
> Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
> ensure its correctness and compatibility with the existing codebase.
> However, your input, reviews, and suggestions are invaluable in making this
> extension even more robust.
>
> The CORE-V builtins are described in the specification [1] and work can be
> found in the OpenHW group's Github repository [2].
>
> [1] 
> github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
>
> [2] github.com/openhwgroup/corev-gcc
>
> Contributors:
> Mary Bennett 
> Nandni Jamnadas 
> Pietra Ferreira 
> Charlie Keaney
> Jessica Mills
> Craig Blackmore 
> Simon Cook 
> Jeremy Bennett 
> Helene Chelin 
>
>   RISC-V: Add support for XCValu extension in CV32E40P
>   RISC-V: Add support for XCVmac extension in CV32E40P
>
>  gcc/common/config/riscv/riscv-common.cc   |   6 +
>  gcc/config/riscv/constraints.md   |   7 +
>  gcc/config/riscv/corev.def|  43 ++
>  gcc/config/riscv/corev.md | 693 ++
>  gcc/config/riscv/predicates.md|   5 +
>  gcc/config/riscv/riscv-builtins.cc|  13 +
>  gcc/config/riscv/riscv-ftypes.def |  11 +
>  gcc/config/riscv/riscv-opts.h |   7 +
>  gcc/config/riscv/riscv.cc |   7 +
>  gcc/config/riscv/riscv.md |   1 +
>  gcc/config/riscv/riscv.opt|   3 +
>  gcc/doc/extend.texi   | 174 +
>  gcc/doc/sourcebuild.texi  |  12 +
>  .../gcc.target/riscv/cv-alu-compile.c | 252 +++
>  .../riscv/cv-alu-fail-compile-addn.c  |  11 +
>  .../riscv/cv-alu-fail-compile-addrn.c |  11 +
>  .../riscv/cv-alu-fail-compile-addun.c |  11 +
>  .../riscv/cv-alu-fail-compile-addurn.c|  11 +
>  .../riscv/cv-alu-fail-compile-clip.c  |  11 +
>  .../riscv/cv-alu-fail-compile-clipu.c |  11 +
>  .../riscv/cv-alu-fail-compile-subn.c  |  11 +
>  .../riscv/cv-alu-fail-compile-subrn.c |  11 +
>  .../riscv/cv-alu-fail-compile-subun.c |  11 +
>  .../riscv/cv-alu-fail-compile-suburn.c|  11 +
>  .../gcc.target/riscv/cv-alu-fail-compile.c|  32 +
>  .../gcc.target/riscv/cv-mac-compile.c | 198 +
>  .../riscv/cv-mac-fail-compile-mac.c   |  25 +
>  .../riscv/cv-mac-fail-compile-machhsn.c   |  24 +
>  .../riscv/cv-mac-fail-compile-machhsrn.c  |  24 +
>  .../riscv/cv-mac-fail-compile-machhun.c   |  24 +
>  .../riscv/cv-mac-fail-compile-machhurn.c  |  24 +
>  .../riscv/cv-mac-fail-compile-macsn.c |  24 +
>  .../riscv/cv-mac-fail-compile-macsrn.c|  24 +
>  .../riscv/cv-mac-fail-compile-macun.c |  24 +
>  .../riscv/cv-mac-fail-compile-macurn.c|  24 +
>  .../riscv/cv-mac-fail-compile-msu.c   |  25 +
>  .../riscv/cv-mac-fail-compile-mulhhsn.c   |  24 +
>  .../riscv/cv-mac-fail-compile-mulhhsrn.c  |  24 +
>  .../riscv/cv-mac-fail-compile-mulhhun.c   |  24 +
>  .../riscv/cv-mac-fail-compile-mulhhurn.c  |  24 +
>  .../riscv/cv-mac-fail-compile-mulsn.c |  24 +
>  .../riscv/cv-mac-fail-compile-mulsrn.c|  24 +
>  .../riscv/cv-mac-fail-compile-mulun.c |  24 +
>  .../riscv/cv-mac-fail-compile-mulurn.c|  24 +
>  .../riscv/cv-mac-test-autogeneration.c|  18 +
>  gcc/testsuite/lib/target-supports.exp |  26 +
>  46 files changed, 2052 insertions(+)
>  create mode 100644 gcc/config/riscv/corev.def
>  create mode 100644 gcc/config/riscv/corev.md
>  create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-compile.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addn.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addrn.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addun.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addurn.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clip.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clipu.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subn.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subrn.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subun.c
>  create 

Re: [PATCH v2 3/4] RISC-V: Extend riscv_subset_list, preparatory for target attribute support

[Kito Cheng]

Thanks, committed with fixup for those two comments :)


On Tue, Oct 10, 2023 at 7:01 AM Jeff Law  wrote:
>
>
>
> On 10/9/23 22:13, Kito Cheng wrote:
> > riscv_subset_list only accept a full arch string before, but we need to
> > parse single extension when supporting target attribute, also we may set
> > a riscv_subset_list directly rather than re-parsing the ISA string
> > again.
> >
> > gcc/ChangeLog:
> >
> >   * config/riscv/riscv-subset.h 
> > (riscv_subset_list::parse_single_std_ext):
> >   New.
> >   (riscv_subset_list::parse_single_multiletter_ext): Ditto.
> >   (riscv_subset_list::clone): Ditto.
> >   (riscv_subset_list::parse_single_ext): Ditto.
> >   (riscv_subset_list::set_loc): Ditto.
> >   (riscv_set_arch_by_subset_list): Ditto.
> >   * common/config/riscv/riscv-common.cc
> >   (riscv_subset_list::parse_single_std_ext): New.
> >   (riscv_subset_list::parse_single_multiletter_ext): Ditto.
> >   (riscv_subset_list::clone): Ditto.
> >   (riscv_subset_list::parse_single_ext): Ditto.
> >   (riscv_subset_list::set_loc): Ditto.
> >   (riscv_set_arch_by_subset_list): Ditto.
> > ---
> >   gcc/common/config/riscv/riscv-common.cc | 203 
> >   gcc/config/riscv/riscv-subset.h |  11 ++
> >   2 files changed, 214 insertions(+)
> >
> > diff --git a/gcc/common/config/riscv/riscv-common.cc 
> > b/gcc/common/config/riscv/riscv-common.cc
> > index 9a0a68fe5db..25630d5923e 100644
> > --- a/gcc/common/config/riscv/riscv-common.cc
> > +++ b/gcc/common/config/riscv/riscv-common.cc
> > @@ -1138,6 +1173,102 @@ riscv_subset_list::handle_combine_ext ()
> >   }
> >   }
> >
> > +/* Parsing function for multi-letter extensions.
> > +
> > +   Return Value:
> > + Points to the end of extensions.
> > +
> > +   Arguments:
> > + `p`: Current parsing position.
> > + `ext_type`: What kind of extensions, 's', 'z' or 'x'.
> > + `ext_type_str`: Full name for kind of extension.  */
> > +
> > +
> > +const char *
> > +riscv_subset_list::parse_single_multiletter_ext (const char *p,
> > +  const char *ext_type,
> > +  const char *ext_type_str)
> [ ... ]
>
>
>
>
> > +
> > +  if (end_of_version == NULL)
> > +return NULL;
> I think when we hit this path we leak SUBSET.
>
>
>
>
> >
> >   std::string
> > @@ -1498,6 +1673,34 @@ static const riscv_ext_flag_table_t 
> > riscv_ext_flag_table[] =
> > {NULL, NULL, 0}
> >   };
> >
> > +void
> > +riscv_set_arch_by_subset_list (riscv_subset_list *subset_list,
> > +struct gcc_options *opts)
> Needs a function comment.
>
> OK with those two minor issues fixed.
>
> jeff

Re: [PATCH v2 1/4] options: Define TARGET__P and TARGET__OPTS_P macro for Mask and InverseMask

[Kito Cheng]

Thanks, committed, and just did one more check with x86 again, it
works as well, hope no more awk portable issue this time :P

On Tue, Oct 10, 2023 at 6:51 AM Jeff Law  wrote:
>
>
>
> On 10/9/23 22:13, Kito Cheng wrote:
> > We TARGET__P marcro to test a Mask and InverseMask with user
> > specified target_variable, however we may want to test with specific
> > gcc_options variable rather than target_variable.
> >
> > Like RISC-V has defined lots of Mask with TargetVariable, which is not
> > easy to use, because that means we need to known which Mask are associate 
> > with
> > which TargetVariable, so take a gcc_options variable is a better interface
> > for such use case.
> >
> > gcc/ChangeLog:
> >
> >   * doc/options.texi (Mask): Document TARGET__P and
> >   TARGET__OPTS_P.
> >   (InverseMask): Ditto.
> >   * opth-gen.awk (Mask): Generate TARGET__P and
> >   TARGET__OPTS_P macro.
> >   (InverseMask): Ditto.
> OK assuming it passes a build cycle on x86 or some other common target.
>
> jeff

Re: [PATCH v2 2/4] RISC-V: Refactor riscv_option_override and riscv_convert_vector_bits. [NFC]

[Kito Cheng]

Thanks, committed :)

On Tue, Oct 10, 2023 at 6:51 AM Jeff Law  wrote:
>
>
>
> On 10/9/23 22:13, Kito Cheng wrote:
> > Allow those funciton apply from a local gcc_options rather than the
> > global options.
> >
> > Preparatory for target attribute, sperate this change for eaiser reivew
> > since it's a NFC.
> >
> > gcc/ChangeLog:
> >
> >   * config/riscv/riscv.cc (riscv_convert_vector_bits): Get setting
> >   from argument rather than get setting from global setting.
> >   (riscv_override_options_internal): New, splited from
> >   riscv_override_options, also take a gcc_options argument.
> >   (riscv_option_override): Splited most part to
> >   riscv_override_options_internal.
> OK.
> jeff

Re: [PATCH v2 4/4] RISC-V: Implement target attribute

[Kito Cheng]

> Assuming you're agreeable to adjusting the code to avoid alloca, we'll
> do a quick turnaround on the v3 -- I'll just audit the return paths to
> make sure we don't leak and we'll be good to go.

Thanks for point out that, let me figure out which is the best way to
fix that, using xstrdup + free or some other smart pointer from C++ :P

Re: Re: [PATCH v2 1/4] options: Define TARGET__P and TARGET__OPTS_P macro for Mask and InverseMask

[Kito Cheng]

Oh, my bad seem like that was in later patch, let me fix now

钟居哲  於 2023年10月11日 週三 15:49 寫道：

> ../../../../gcc/gcc/config/riscv/riscv.cc:8142:18: error:
> ‘TARGET_MIN_VLEN_OPTS’ was not declared in this scope
>int min_vlen = TARGET_MIN_VLEN_OPTS (opts);
>
>
>
> --
> juzhe.zh...@rivai.ai
>
>
> *From:* Kito Cheng 
> *Date:* 2023-10-12 05:20
> *To:* Jeff Law 
> *CC:* Kito Cheng ; gcc-patches
> ; palmer ; rdapp
> ; juzhe.zhong 
> *Subject:* Re: [PATCH v2 1/4] options: Define TARGET__P and
> TARGET__OPTS_P macro for Mask and InverseMask
> Thanks, committed, and just did one more check with x86 again, it
> works as well, hope no more awk portable issue this time :P
>
> On Tue, Oct 10, 2023 at 6:51 AM Jeff Law  wrote:
> >
> >
> >
> > On 10/9/23 22:13, Kito Cheng wrote:
> > > We TARGET__P marcro to test a Mask and InverseMask with user
> > > specified target_variable, however we may want to test with specific
> > > gcc_options variable rather than target_variable.
> > >
> > > Like RISC-V has defined lots of Mask with TargetVariable, which is not
> > > easy to use, because that means we need to known which Mask are
> associate with
> > > which TargetVariable, so take a gcc_options variable is a better
> interface
> > > for such use case.
> > >
> > > gcc/ChangeLog:
> > >
> > >   * doc/options.texi (Mask): Document TARGET__P and
> > >   TARGET__OPTS_P.
> > >   (InverseMask): Ditto.
> > >   * opth-gen.awk (Mask): Generate TARGET__P and
> > >   TARGET__OPTS_P macro.
> > >   (InverseMask): Ditto.
> > OK assuming it passes a build cycle on x86 or some other common target.
> >
> > jeff
>
>
>

Re: Re: [PATCH] RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512.

[Kito Cheng]

Yeah, I'll take you suggestion and go ahead, Robin's suggestion is
great but it's just a little too magic :P

On Wed, Oct 11, 2023 at 4:00 PM 钟居哲  wrote:
>
> Any update of this patch?
>
> Currently, we are running vect testsuite with -march=rv64gcv_zvl128b
>
> I am planning to run vect testsuite with these following combinations:
>
> -march=rv64gcv_zvl128b --param=riscv-autovec-lmul=m1
> -march=rv64gcv_zvl128b --param=riscv-autovec-lmul=m2
> -march=rv64gcv_zvl128b --param=riscv-autovec-lmul=m4
> -march=rv64gcv_zvl128b --param=riscv-autovec-lmul=m8
> -march=rv64gcv_zvl128b --param=riscv-autovec-lmul=dynamic
>
> -march=rv64gcv_zvl256b --param=riscv-autovec-lmul=m1
> -march=rv64gcv_zvl256b --param=riscv-autovec-lmul=m2
> -march=rv64gcv_zvl256b --param=riscv-autovec-lmul=m4
> -march=rv64gcv_zvl256b --param=riscv-autovec-lmul=m8
> -march=rv64gcv_zvl256b --param=riscv-autovec-lmul=dynamic
>
> -march=rv64gcv_zvl512b --param=riscv-autovec-lmul=m1
> -march=rv64gcv_zvl512b --param=riscv-autovec-lmul=m2
> -march=rv64gcv_zvl512b --param=riscv-autovec-lmul=m4
> -march=rv64gcv_zvl512b --param=riscv-autovec-lmul=m8
> -march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic
>
> -march=rv64gcv_zvl1024b --param=riscv-autovec-lmul=m1
> -march=rv64gcv_zvl1024b --param=riscv-autovec-lmul=m2
> -march=rv64gcv_zvl1024b --param=riscv-autovec-lmul=m4
> -march=rv64gcv_zvl1024b --param=riscv-autovec-lmul=m8
> -march=rv64gcv_zvl1024b --param=riscv-autovec-lmul=dynamic
>
> -march=rv64gcv_zvl2048b --param=riscv-autovec-lmul=m1
> -march=rv64gcv_zvl2048b --param=riscv-autovec-lmul=m2
> -march=rv64gcv_zvl2048b --param=riscv-autovec-lmul=m4
> -march=rv64gcv_zvl2048b --param=riscv-autovec-lmul=m8
> -march=rv64gcv_zvl2048b --param=riscv-autovec-lmul=dynamic
>
> -march=rv64gcv_zvl4096b --param=riscv-autovec-lmul=m1
> -march=rv64gcv_zvl4096b --param=riscv-autovec-lmul=m2
> -march=rv64gcv_zvl4096b --param=riscv-autovec-lmul=m4
> -march=rv64gcv_zvl4096b --param=riscv-autovec-lmul=m8
> -march=rv64gcv_zvl4096b --param=riscv-autovec-lmul=dynamic
>
> I will do that in stage 3. I hope this patch can be landed before I do that.
> 
> juzhe.zh...@rivai.ai
>
>
> From: Kito Cheng
> Date: 2023-10-05 22:00
> To: Robin Dapp
> CC: Jeff Law; gcc-patches; kito.cheng; palmer; 钟居哲
> Subject: Re: [PATCH] RISC-V: Fix the riscv_legitimize_poly_move issue on 
> targets where the minimal VLEN exceeds 512.
> Hi Robin:
>
> Your suggested code seems work fine, let me run more test and send v2, I 
> guess I just don’t know how to explain why it work in comment :p
>
> Robin Dapp 於 2023年10月5日 週四，03:57寫道：
>>
>> >> I think the "max poly value" is the LMUL 1 mode coeffs[1]
>> >>
>> >> See int vlenb = BYTES_PER_RISCV_VECTOR.coeffs[1];
>> >>
>> >> So I think bump max_power to exact_log2 (64); is not enough.
>> >> since we adjust the LMUL 1 mode size according to TARGET_MIN_VLEN.
>> >>
>> >> I suspect the testcase you append in this patch will fail with 
>> >> -march=rv64gcv_zvl4096b.
>> >
>> >
>> > There is no type smaller than  [64, 64] in zvl4096b, RVVMF64BI is [64,
>> > 64], it’s smallest type, and RVVFM1BI is [512, 512] (size of single
>> > vector reg.) which at most 64x for zvl4096b, so my understanding is
>> > log2(64) is enough :)
>> >
>> > and of cause, verified the testcase is work with -march=rv64gcv_zvl4096b
>>
>> I was wondering if the whole hunk couldn't be condensed into something
>> like (untested):
>>
>>   div_factor = wi::ctz (factor) - wi::ctz (vlenb);
>>   if (div_factor >= 0)
>> div_factor = 1;
>>   else
>> div_factor = 1 << -div_factor;
>>
>> This would avoid the loop as well.  An assert for the div_factor (not
>> exceeding a value) could still be added.
>>
>> Regards
>>  Robin

[committed] RISC-V: Add TARGET_MIN_VLEN_OPTS to fix the build

[Kito Cheng]

gcc/ChangeLog:

* config/riscv/riscv-opts.h (TARGET_MIN_VLEN_OPTS): New.
---
 gcc/config/riscv/riscv-opts.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index e7c6b75c5ea..31ee42dea6b 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -112,6 +112,12 @@ enum riscv_entity
? 0 \
: 32 << (__builtin_popcount (riscv_zvl_flags) - 1))
 
+/* Same as TARGET_MIN_VLEN, but take an OPTS as gcc_options.  */
+#define TARGET_MIN_VLEN_OPTS(opts) 
\
+  ((opts->x_riscv_zvl_flags == 0)  
\
+ ? 0   
\
+ : 32 << (__builtin_popcount (opts->x_riscv_zvl_flags) - 1))
+
 /* We only enable VLS modes for VLA vectorization since fixed length VLMAX mode
is the highest priority choice and should not conflict with VLS modes.  */
 #define TARGET_VECTOR_VLS  
\
-- 
2.34.1

Re: Re: [PATCH v2 1/4] options: Define TARGET__P and TARGET__OPTS_P macro for Mask and InverseMask

[Kito Cheng]

Fixed, sorry for disturbing trunk

On Wed, Oct 11, 2023 at 3:50 PM Kito Cheng  wrote:
>
> Oh, my bad seem like that was in later patch, let me fix now
>
> 钟居哲  於 2023年10月11日 週三 15:49 寫道：
>>
>> ../../../../gcc/gcc/config/riscv/riscv.cc:8142:18: error: 
>> ‘TARGET_MIN_VLEN_OPTS’ was not declared in this scope
>>int min_vlen = TARGET_MIN_VLEN_OPTS (opts);
>>
>>
>>
>> ____
>> juzhe.zh...@rivai.ai
>>
>>
>> From: Kito Cheng
>> Date: 2023-10-12 05:20
>> To: Jeff Law
>> CC: Kito Cheng; gcc-patches; palmer; rdapp; juzhe.zhong
>> Subject: Re: [PATCH v2 1/4] options: Define TARGET__P and 
>> TARGET__OPTS_P macro for Mask and InverseMask
>> Thanks, committed, and just did one more check with x86 again, it
>> works as well, hope no more awk portable issue this time :P
>>
>> On Tue, Oct 10, 2023 at 6:51 AM Jeff Law  wrote:
>> >
>> >
>> >
>> > On 10/9/23 22:13, Kito Cheng wrote:
>> > > We TARGET__P marcro to test a Mask and InverseMask with user
>> > > specified target_variable, however we may want to test with specific
>> > > gcc_options variable rather than target_variable.
>> > >
>> > > Like RISC-V has defined lots of Mask with TargetVariable, which is not
>> > > easy to use, because that means we need to known which Mask are 
>> > > associate with
>> > > which TargetVariable, so take a gcc_options variable is a better 
>> > > interface
>> > > for such use case.
>> > >
>> > > gcc/ChangeLog:
>> > >
>> > >   * doc/options.texi (Mask): Document TARGET__P and
>> > >   TARGET__OPTS_P.
>> > >   (InverseMask): Ditto.
>> > >   * opth-gen.awk (Mask): Generate TARGET__P and
>> > >   TARGET__OPTS_P macro.
>> > >   (InverseMask): Ditto.
>> > OK assuming it passes a build cycle on x86 or some other common target.
>> >
>> > jeff
>>

Re: RISC-V: Support CORE-V XCVMAC and XCVALU extensions

[Kito Cheng]

Take a quick look and maybe fix it like that, but I am not sure the
layout is what they want.

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index eb665188caf..1692e43de10 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -21714,7 +21714,7 @@ vector intrinsic specification, which is
available at the following link:
All of these functions are declared in the include file @file{riscv_vector.h}.

@node CORE-V Built-in Functions
-@subsubsection CORE-V Built-in Functions
+@subsection CORE-V Built-in Functions

These built-in functions are available for the CORE-V MAC machine
architecture. For more information on CORE-V built-ins, please see


On Wed, Oct 11, 2023 at 6:59 PM Jeff Law  wrote:
>
>
>
> On 10/11/23 19:05, juzhe.zh...@rivai.ai wrote:
> > Plz revert it. It blocks development of all targets.
> We have specific policies for reversion.  In general we want to give
> folks time to fix the problem rather than reverting, resubmitting, etc.
>
> Mary, the issue is the doc changes are apparently dependent on specific
> versions of texinfo being installed resulting in this error:
>
> > ../../../../gcc/gcc/doc/extend.texi:21708: warning: node next `RISC-V 
> > Vector Intrinsics' in menu `CORE-V Built-in Functions' and in sectioning 
> > `RX Built-in Functions' differ
> > ../../../../gcc/gcc/doc/extend.texi:21716: warning: node `RX Built-in 
> > Functions' is next for `CORE-V Built-in Functions' in menu but not in 
> > sectioning
> > ../../../../gcc/gcc/doc/extend.texi:21716: warning: node `RISC-V Vector 
> > Intrinsics' is prev for `CORE-V Built-in Functions' in menu but not in 
> > sectioning
> > ../../../../gcc/gcc/doc/extend.texi:21716: warning: node up `CORE-V 
> > Built-in Functions' in menu `Target Builtins' and in sectioning `RISC-V 
> > Vector Intrinsics' differ
> > ../../../../gcc/gcc/doc/extend.texi:21708: node `RISC-V Vector Intrinsics' 
> > lacks menu item for `CORE-V Built-in Functions' despite being its Up target
> > ../../../../gcc/gcc/doc/extend.texi:21889: warning: node prev `RX Built-in 
> > Functions' in menu `CORE-V Built-in Functions' and in sectioning `RISC-V 
> > Vector Intrinsics' differ
>
>
> Jeff

Re: [PATCH v1] RISC-V: Support FP llrint auto vectorization

[Kito Cheng]

Did I miss something? the title says support but it seems only testcase??

On Wed, Oct 11, 2023 at 8:38 PM Li, Pan2  wrote:
>
> Committed, thanks Juzhe.
>
>
>
> Pan
>
>
>
> From: juzhe.zh...@rivai.ai 
> Sent: Thursday, October 12, 2023 11:34 AM
> To: Li, Pan2 ; gcc-patches 
> Cc: Li, Pan2 ; Wang, Yanzhang ; 
> kito.cheng 
> Subject: Re: [PATCH v1] RISC-V: Support FP llrint auto vectorization
>
>
>
> LGTM
>
>
>
> 
>
> juzhe.zh...@rivai.ai
>
>
>
> From: pan2.li
>
> Date: 2023-10-12 11:28
>
> To: gcc-patches
>
> CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
>
> Subject: [PATCH v1] RISC-V: Support FP llrint auto vectorization
>
> From: Pan Li 
>
>
>
> This patch would like to support the FP llrint auto vectorization.
>
>
>
> * long long llrint (double)
>
>
>
> This will be the CVT from DF => DI from the standard name's perpsective,
>
> which has been covered in previous PATCH(es). Thus, this patch only add
>
> some test cases.
>
>
>
> gcc/testsuite/ChangeLog:
>
>
>
> * gcc.target/riscv/rvv/autovec/unop/test-math.h: Add type int64_t.
>
> * gcc.target/riscv/rvv/autovec/unop/math-llrint-0.c: New test.
>
> * gcc.target/riscv/rvv/autovec/unop/math-llrint-run-0.c: New test.
>
> * gcc.target/riscv/rvv/autovec/vls/math-llrint-0.c: New test.
>
>
>
> Signed-off-by: Pan Li 
>
> ---
>
> .../riscv/rvv/autovec/unop/math-llrint-0.c| 14 +
>
> .../rvv/autovec/unop/math-llrint-run-0.c  | 63 +++
>
> .../riscv/rvv/autovec/unop/test-math.h|  2 +
>
> .../riscv/rvv/autovec/vls/math-llrint-0.c | 30 +
>
> 4 files changed, 109 insertions(+)
>
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-0.c
>
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-run-0.c
>
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrint-0.c
>
>
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-0.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-0.c
>
> new file mode 100644
>
> index 000..2d90d232ba1
>
> --- /dev/null
>
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-0.c
>
> @@ -0,0 +1,14 @@
>
> +/* { dg-do compile } */
>
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
> -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } 
> */
>
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> +
>
> +#include "test-math.h"
>
> +
>
> +/*
>
> +** test_double_int64_t___builtin_llrint:
>
> +**   ...
>
> +**   vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
>
> +**   vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+
>
> +**   ...
>
> +*/
>
> +TEST_UNARY_CALL_CVT (double, int64_t, __builtin_llrint)
>
> diff --git 
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-run-0.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-run-0.c
>
> new file mode 100644
>
> index 000..6b69f5568e9
>
> --- /dev/null
>
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-run-0.c
>
> @@ -0,0 +1,63 @@
>
> +/* { dg-do run { target { riscv_v && rv64 } } } */
>
> +/* { dg-additional-options "-std=c99 -O3 -ftree-vectorize 
> -fno-vect-cost-model -ffast-math" } */
>
> +
>
> +#include "test-math.h"
>
> +
>
> +#define ARRAY_SIZE 128
>
> +
>
> +double in[ARRAY_SIZE];
>
> +int64_t out[ARRAY_SIZE];
>
> +int64_t ref[ARRAY_SIZE];
>
> +
>
> +TEST_UNARY_CALL_CVT (double, int64_t, __builtin_llrint)
>
> +TEST_ASSERT (int64_t)
>
> +
>
> +TEST_INIT_CVT (double, 1.2, int64_t, __builtin_llrint (1.2), 1)
>
> +TEST_INIT_CVT (double, -1.2, int64_t, __builtin_llrint (-1.2), 2)
>
> +TEST_INIT_CVT (double, 0.5, int64_t, __builtin_llrint (0.5), 3)
>
> +TEST_INIT_CVT (double, -0.5, int64_t, __builtin_llrint (-0.5), 4)
>
> +TEST_INIT_CVT (double, 0.1, int64_t, __builtin_llrint (0.1), 5)
>
> +TEST_INIT_CVT (double, -0.1, int64_t, __builtin_llrint (-0.1), 6)
>
> +TEST_INIT_CVT (double, 3.0, int64_t, __builtin_llrint (3.0), 7)
>
> +TEST_INIT_CVT (double, -3.0, int64_t, __builtin_llrint (-3.0), 8)
>
> +TEST_INIT_CVT (double, 4503599627370495.5, int64_t, __builtin_llrint 
> (4503599627370495.5), 9)
>
> +TEST_INIT_CVT (double, 4503599627370497.0, int64_t, __builtin_llrint 
> (4503599627370497.0), 10)
>
> +TEST_INIT_CVT (double, -4503599627370495.5, int64_t, __builtin_llrint 
> (-4503599627370495.5), 11)
>
> +TEST_INIT_CVT (double, -4503599627370496.0, int64_t, __builtin_llrint 
> (-4503599627370496.0), 12)
>
> +TEST_INIT_CVT (double, 0.0, int64_t, __builtin_llrint (-0.0), 13)
>
> +TEST_INIT_CVT (double, -0.0, int64_t, __builtin_llrint (-0.0), 14)
>
> +TEST_INIT_CVT (double, 9223372036854774784.0, int64_t, __builtin_llrint 
> (9223372036854774784.0), 15)
>
> +TEST_INIT_CVT (double, 9223372036854775808.0, int64_t, __builtin_llrint 
> (9223372036854775808.0), 16)
>
> +TEST_INIT_CVT (double, -9223372036854775808.0, int64_t, __builtin_llrint 
> (-9223372036854775808.0), 17)
>
> +TEST_INIT_CVT (dou

Re: [PATCH v1] RISC-V: Support FP llrint auto vectorization

[Kito Cheng]

I would prefer first approach since it no changes other than adding
testcase, that might confusing other people.


Li, Pan2  於 2023年10月11日 週三 23:12 寫道：

> Sorry for misleading here.
>
> When implement the llrint after lrint, I realize llrint (DF => SF) are
> supported by the lrint already in the previous patche(es).
> Because they same the same standard name as well as the mode iterator.
>
> Thus, I may have 2 options here for the patch naming.
>
> 1. Only mentioned test cases for llrint.
> 2. Named as support similar to lrint.
>
> After some consideration from the situation like search from the git logs,
> I choose option 2 here and add some description in
> as well.
>
> Finally, is there any best practices for this case? Thank again for
> comments.
>
> Pan
>
> -Original Message-
> From: Kito Cheng 
> Sent: Thursday, October 12, 2023 1:05 PM
> To: Li, Pan2 
> Cc: juzhe.zh...@rivai.ai; gcc-patches ; Wang,
> Yanzhang 
> Subject: Re: [PATCH v1] RISC-V: Support FP llrint auto vectorization
>
> Did I miss something? the title says support but it seems only testcase??
>
> On Wed, Oct 11, 2023 at 8:38 PM Li, Pan2  wrote:
> >
> > Committed, thanks Juzhe.
> >
> >
> >
> > Pan
> >
> >
> >
> > From: juzhe.zh...@rivai.ai 
> > Sent: Thursday, October 12, 2023 11:34 AM
> > To: Li, Pan2 ; gcc-patches 
> > Cc: Li, Pan2 ; Wang, Yanzhang <
> yanzhang.w...@intel.com>; kito.cheng 
> > Subject: Re: [PATCH v1] RISC-V: Support FP llrint auto vectorization
> >
> >
> >
> > LGTM
> >
> >
> >
> > 
> >
> > juzhe.zh...@rivai.ai
> >
> >
> >
> > From: pan2.li
> >
> > Date: 2023-10-12 11:28
> >
> > To: gcc-patches
> >
> > CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
> >
> > Subject: [PATCH v1] RISC-V: Support FP llrint auto vectorization
> >
> > From: Pan Li 
> >
> >
> >
> > This patch would like to support the FP llrint auto vectorization.
> >
> >
> >
> > * long long llrint (double)
> >
> >
> >
> > This will be the CVT from DF => DI from the standard name's perpsective,
> >
> > which has been covered in previous PATCH(es). Thus, this patch only add
> >
> > some test cases.
> >
> >
> >
> > gcc/testsuite/ChangeLog:
> >
> >
> >
> > * gcc.target/riscv/rvv/autovec/unop/test-math.h: Add type int64_t.
> >
> > * gcc.target/riscv/rvv/autovec/unop/math-llrint-0.c: New test.
> >
> > * gcc.target/riscv/rvv/autovec/unop/math-llrint-run-0.c: New test.
> >
> > * gcc.target/riscv/rvv/autovec/vls/math-llrint-0.c: New test.
> >
> >
> >
> > Signed-off-by: Pan Li 
> >
> > ---
> >
> > .../riscv/rvv/autovec/unop/math-llrint-0.c| 14 +
> >
> > .../rvv/autovec/unop/math-llrint-run-0.c  | 63 +++
> >
> > .../riscv/rvv/autovec/unop/test-math.h|  2 +
> >
> > .../riscv/rvv/autovec/vls/math-llrint-0.c | 30 +
> >
> > 4 files changed, 109 insertions(+)
> >
> > create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-0.c
> >
> > create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-run-0.c
> >
> > create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrint-0.c
> >
> >
> >
> > diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-0.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-0.c
> >
> > new file mode 100644
> >
> > index 000..2d90d232ba1
> >
> > --- /dev/null
> >
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-0.c
> >
> > @@ -0,0 +1,14 @@
> >
> > +/* { dg-do compile } */
> >
> > +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
> -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2"
> } */
> >
> > +/* { dg-final { check-function-bodies "**" "" } } */
> >
> > +
> >
> > +#include "test-math.h"
> >
> > +
> >
> > +/*
> >
> > +** test_double_int64_t___builtin_llrint:
> >
> > +**   ...
> >
> > +**   vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
> >
> > +**   vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+
> >
> > +**   ...
> >
> > +*/
> >
> > 

Re: [PATCH] RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512.

[Kito Cheng]

Yeah, will send v2 today

Jeff Law  於 2023年10月12日 週四 09:15 寫道：

>
>
> On 10/11/23 17:17, Kito Cheng wrote:
> > Yeah, I'll take you suggestion and go ahead, Robin's suggestion is
> > great but it's just a little too magic :P
> So there'll be a V2 of this patch, right?  Just want to make sure state
> is correct in patchwork.
>
> jeff
>

Re: [PATCH v2] RISC-V: Make xtheadcondmov-indirect tests robust against instruction reordering

[Kito Cheng]

Sorry for the late comment after Jeff say ok, but I guess we may
consider add "-fno-schedule-insns -fno-schedule-insns2" to avoid
disturbing from schedule like some of our test case in
gcc/testsuite/gcc.target/riscv/rvv?

On Thu, Oct 12, 2023 at 9:12 AM Jeff Law  wrote:
>
>
>
> On 10/12/23 07:06, Christoph Muellner wrote:
> > From: Christoph Müllner 
> >
> > Fixes: c1bc7513b1d7 ("RISC-V: const: hide mvconst splitter from IRA")
> >
> > A recent change broke the xtheadcondmov-indirect tests, because the order of
> > emitted instructions changed. Since the test is too strict when testing for
> > a fixed instruction order, let's change the tests to simply count 
> > instruction,
> > like it is done for similar tests.
> >
> > Reported-by: Patrick O'Neill 
> > Signed-off-by: Christoph Müllner 
> >
> > gcc/testsuite/ChangeLog:
> >
> >   * gcc.target/riscv/xtheadcondmov-indirect.c: Make robust against
> >   instruction reordering.
> OK for the trunk.
>
> jeff

Re: [PATCH v2] RISC-V: Make xtheadcondmov-indirect tests robust against instruction reordering

[Kito Cheng]

but anyway, I don't have a strong opinion for either way, just go
ahead no matter which one you choose.

On Thu, Oct 12, 2023 at 11:28 AM Kito Cheng  wrote:
>
> Sorry for the late comment after Jeff say ok, but I guess we may
> consider add "-fno-schedule-insns -fno-schedule-insns2" to avoid
> disturbing from schedule like some of our test case in
> gcc/testsuite/gcc.target/riscv/rvv?
>
> On Thu, Oct 12, 2023 at 9:12 AM Jeff Law  wrote:
> >
> >
> >
> > On 10/12/23 07:06, Christoph Muellner wrote:
> > > From: Christoph Müllner 
> > >
> > > Fixes: c1bc7513b1d7 ("RISC-V: const: hide mvconst splitter from IRA")
> > >
> > > A recent change broke the xtheadcondmov-indirect tests, because the order 
> > > of
> > > emitted instructions changed. Since the test is too strict when testing 
> > > for
> > > a fixed instruction order, let's change the tests to simply count 
> > > instruction,
> > > like it is done for similar tests.
> > >
> > > Reported-by: Patrick O'Neill 
> > > Signed-off-by: Christoph Müllner 
> > >
> > > gcc/testsuite/ChangeLog:
> > >
> > >   * gcc.target/riscv/xtheadcondmov-indirect.c: Make robust against
> > >   instruction reordering.
> > OK for the trunk.
> >
> > jeff

[PATCH v2] RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512.

[Kito Cheng]

riscv_legitimize_poly_move was expected to ensure the poly value is at most 32
times smaller than the minimal VLEN (32 being derived from '4096 / 128').
This assumption held when our mode modeling was not so precisely defined.
However, now that we have modeled the mode size according to the correct minimal
VLEN info, the size difference between different RVV modes can be up to 64
times. For instance, comparing RVVMF64BI and RVVMF1BI, the sizes are [1, 1]
versus [64, 64] respectively.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_legitimize_poly_move): Bump
max_power to 64.

gcc/testsuite/ChangeLog:

* g++.target/riscv/rvv/autovec/bug-01.C: New.
* g++.target/riscv/rvv/rvv.exp: Add autovec folder.
---
 gcc/config/riscv/riscv.cc |  5 ++-
 gcc/config/riscv/riscv.h  |  5 +++
 .../g++.target/riscv/rvv/autovec/bug-01.C | 33 +++
 gcc/testsuite/g++.target/riscv/rvv/rvv.exp|  3 ++
 4 files changed, 43 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 739fc77e785..d43bc765ce7 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2411,9 +2411,8 @@ riscv_legitimize_poly_move (machine_mode mode, rtx dest, 
rtx tmp, rtx src)
 }
   else
 {
-  /* FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096.  */
-  int max_power = exact_log2 (4096 / 128);
-  for (int i = 0; i < max_power; i++)
+  int max_power = exact_log2 (MAX_POLY_VARIANT);
+  for (int i = 0; i <= max_power; i++)
{
  int possible_div_factor = 1 << i;
  if (factor % (vlenb / possible_div_factor) == 0)
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 4b8d57509fb..3d2723f5339 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -1197,4 +1197,9 @@ extern void riscv_remove_unneeded_save_restore_calls 
(void);
 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_VECTOR)
 #define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE, riscv_vector::FRM_NONE}
 
+
+/* The size difference between different RVV modes can be up to 64 times.
+   e.g. RVVMF64BI vs RVVMF1BI on zvl512b, which is [1, 1] vs [64, 64].  */
+#define MAX_POLY_VARIANT 64
+
 #endif /* ! GCC_RISCV_H */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C 
b/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C
new file mode 100644
index 000..fd10009ddbe
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C
@@ -0,0 +1,33 @@
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3" } */
+
+class c {
+public:
+  int e();
+  void j();
+};
+float *d;
+class k {
+  int f;
+
+public:
+  k(int m) : f(m) {}
+  float g;
+  float h;
+  void n(int m) {
+for (int i; i < m; i++) {
+  d[0] = d[1] = d[2] = g;
+  d[3] = h;
+  d += f;
+}
+  }
+};
+c l;
+void o() {
+  int b = l.e();
+  k a(b);
+  for (;;)
+if (b == 4) {
+  l.j();
+  a.n(2);
+}
+}
diff --git a/gcc/testsuite/g++.target/riscv/rvv/rvv.exp 
b/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
index 249530580d7..c30d6e93144 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
@@ -40,5 +40,8 @@ set CFLAGS "-march=$gcc_march -O3"
 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.C]] \
"" $CFLAGS
 
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[C\]]] \
+"" $CFLAGS
+
 # All done.
 dg-finish
-- 
2.34.1

Re: [PATCH v2] RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512.

[Kito Cheng]

Committed with few changelog tweak :P

On Thu, Oct 12, 2023 at 3:37 PM 钟居哲  wrote:
>
> LGTM
>
> 
> juzhe.zh...@rivai.ai
>
>
> From: Kito Cheng
> Date: 2023-10-13 02:40
> To: gcc-patches; kito.cheng; palmer; jeffreyalaw; rdapp; juzhe.zhong
> CC: Kito Cheng
> Subject: [PATCH v2] RISC-V: Fix the riscv_legitimize_poly_move issue on 
> targets where the minimal VLEN exceeds 512.
> riscv_legitimize_poly_move was expected to ensure the poly value is at most 32
> times smaller than the minimal VLEN (32 being derived from '4096 / 128').
> This assumption held when our mode modeling was not so precisely defined.
> However, now that we have modeled the mode size according to the correct 
> minimal
> VLEN info, the size difference between different RVV modes can be up to 64
> times. For instance, comparing RVVMF64BI and RVVMF1BI, the sizes are [1, 1]
> versus [64, 64] respectively.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_legitimize_poly_move): Bump
> max_power to 64.
>
> gcc/testsuite/ChangeLog:
>
> * g++.target/riscv/rvv/autovec/bug-01.C: New.
> * g++.target/riscv/rvv/rvv.exp: Add autovec folder.
> ---
> gcc/config/riscv/riscv.cc |  5 ++-
> gcc/config/riscv/riscv.h  |  5 +++
> .../g++.target/riscv/rvv/autovec/bug-01.C | 33 +++
> gcc/testsuite/g++.target/riscv/rvv/rvv.exp|  3 ++
> 4 files changed, 43 insertions(+), 3 deletions(-)
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 739fc77e785..d43bc765ce7 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -2411,9 +2411,8 @@ riscv_legitimize_poly_move (machine_mode mode, rtx 
> dest, rtx tmp, rtx src)
>  }
>else
>  {
> -  /* FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096.  */
> -  int max_power = exact_log2 (4096 / 128);
> -  for (int i = 0; i < max_power; i++)
> +  int max_power = exact_log2 (MAX_POLY_VARIANT);
> +  for (int i = 0; i <= max_power; i++)
> {
>   int possible_div_factor = 1 << i;
>   if (factor % (vlenb / possible_div_factor) == 0)
> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
> index 4b8d57509fb..3d2723f5339 100644
> --- a/gcc/config/riscv/riscv.h
> +++ b/gcc/config/riscv/riscv.h
> @@ -1197,4 +1197,9 @@ extern void riscv_remove_unneeded_save_restore_calls 
> (void);
> #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_VECTOR)
> #define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE, riscv_vector::FRM_NONE}
> +
> +/* The size difference between different RVV modes can be up to 64 times.
> +   e.g. RVVMF64BI vs RVVMF1BI on zvl512b, which is [1, 1] vs [64, 64].  */
> +#define MAX_POLY_VARIANT 64
> +
> #endif /* ! GCC_RISCV_H */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C 
> b/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C
> new file mode 100644
> index 000..fd10009ddbe
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-01.C
> @@ -0,0 +1,33 @@
> +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3" } */
> +
> +class c {
> +public:
> +  int e();
> +  void j();
> +};
> +float *d;
> +class k {
> +  int f;
> +
> +public:
> +  k(int m) : f(m) {}
> +  float g;
> +  float h;
> +  void n(int m) {
> +for (int i; i < m; i++) {
> +  d[0] = d[1] = d[2] = g;
> +  d[3] = h;
> +  d += f;
> +}
> +  }
> +};
> +c l;
> +void o() {
> +  int b = l.e();
> +  k a(b);
> +  for (;;)
> +if (b == 4) {
> +  l.j();
> +  a.n(2);
> +}
> +}
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/rvv.exp 
> b/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
> index 249530580d7..c30d6e93144 100644
> --- a/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
> +++ b/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
> @@ -40,5 +40,8 @@ set CFLAGS "-march=$gcc_march -O3"
> dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.C]] \
> "" $CFLAGS
> +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[C\]]] \
> +"" $CFLAGS
> +
> # All done.
> dg-finish
> --
> 2.34.1
>
>

Re: [PATCH] RISC-V Regression: Fix FAIL of bb-slp-pr69907.c for RVV

[Kito Cheng]

LGTM

Juzhe-Zhong  於 2023年10月12日 週四 22:45 寫道：

> Like ARM SVE and GCN, add RVV.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.dg/vect/bb-slp-pr69907.c: Add RVV.
>
> ---
>  gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
> b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
> index b348526b62f..f63b42a271a 100644
> --- a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
> +++ b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
> @@ -22,5 +22,5 @@ void foo(unsigned *p1, unsigned short *p2)
>  /* Disable for SVE because for long or variable-length vectors we don't
> get an unrolled epilogue loop.  Also disable for AArch64 Advanced SIMD,
> because there we can vectorize the epilogue using mixed vector sizes.
> -   Likewise for AMD GCN.  */
> -/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of
> a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { !
> amdgcn*-*-* } } } } } */
> +   Likewise for AMD GCN and RVV.  */
> +/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of
> a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { { !
> amdgcn*-*-* } && { ! riscv_v } } } } } } */
> --
> 2.36.3
>
>

Re: Continued (Non)mutlib and stub header issue (was Re: [PATCH v2] RISC-V: Use stdint-gcc.h in rvv testsuite)

[Kito Cheng]

> When looking around, I stumbled upon commit
>  d0bbecb1c41 "RISC-V: Add riscv_vector.h wrapper in testsuite to
> prevent pull in stdint.h from C library"
>work
> Which seems like a step in a right direction, but how does one ensure
> that the wrapper riscv_vector.h (containing stdint-gcc.h) is included by
> test vs. the default riscv_vector.h (which is more user facing and thus
> needs to include the system stdint.h)

IIRC it rely on #include "" vs #include <>, the former will
search the same folder first, then the header search path,
so...made a dummy one, and put into test folder, then it will use our
own version now :P

but I guess maybe the right way (or simpler way) is just adding an
extra header search path to CFLAG and making a dummy stdint.h as well?

>
> P.S. I couldn't find the posting for above commit on gcc-patches ?

Here is the mail:
https://gcc.gnu.org/pipermail/gcc-patches/2022-October/603140.html

>
> Thx,
> -Vineet

Re: [PATCH] RISC-V: Fix interrupt support for -g.

[Kito Cheng]

Hi Jim:

Does it possible just combine those pattern into simple_return
pattern, and then check the function type and output correct return
instruction in riscv_output_return?
On Tue, Jul 3, 2018 at 8:22 AM Jim Wilson  wrote:
>
> This fixes a problem found by someone trying to use the new RISC-V interrupt
> attribute support.  With a slightly non-trivial example, and the -g option, we
> get an abort in dwarf2cfi for an inconsistent CFI state.  This is my fault
> for not making the new interrupt return patterns look enough like regular
> return patterns, which is simple to fix.
>
> Tested with cross riscv32-elf and riscv64-linux builds and tests.  There were
> no regressions.  The new testcase fails without the patch and works with the
> patch.
>
> Committed.
>
> Jim
>
> gcc/
> * config/riscv/riscv.c (riscv_expand_epilogue): Use emit_jump_insn
> instead of emit_insn for interrupt returns.
> * config/riscv/riscv.md (riscv_met): Add (return) to rtl.
> (riscv_sret, riscv_uret): Likewise.
>
> gcc/testsuite/
> * gcc.target/riscv/interrupt-debug.c: New.
> ---
>  gcc/config/riscv/riscv.c |  6 +++---
>  gcc/config/riscv/riscv.md|  9 ++---
>  gcc/testsuite/gcc.target/riscv/interrupt-debug.c | 15 +++
>  3 files changed, 24 insertions(+), 6 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/interrupt-debug.c
>
> diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
> index 2709ebdd797..d87836f53f8 100644
> --- a/gcc/config/riscv/riscv.c
> +++ b/gcc/config/riscv/riscv.c
> @@ -3985,11 +3985,11 @@ riscv_expand_epilogue (int style)
>enum riscv_privilege_levels mode = cfun->machine->interrupt_mode;
>
>if (mode == MACHINE_MODE)
> -   emit_insn (gen_riscv_mret ());
> +   emit_jump_insn (gen_riscv_mret ());
>else if (mode == SUPERVISOR_MODE)
> -   emit_insn (gen_riscv_sret ());
> +   emit_jump_insn (gen_riscv_sret ());
>else
> -   emit_insn (gen_riscv_uret ());
> +   emit_jump_insn (gen_riscv_uret ());
>  }
>else if (style != SIBCALL_RETURN)
>  emit_jump_insn (gen_simple_return_internal (ra));
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 7b411f0538e..613af9d79e4 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -2328,17 +2328,20 @@
>"fsflags\t%0")
>
>  (define_insn "riscv_mret"
> -  [(unspec_volatile [(const_int 0)] UNSPECV_MRET)]
> +  [(return)
> +   (unspec_volatile [(const_int 0)] UNSPECV_MRET)]
>""
>"mret")
>
>  (define_insn "riscv_sret"
> -  [(unspec_volatile [(const_int 0)] UNSPECV_SRET)]
> +  [(return)
> +   (unspec_volatile [(const_int 0)] UNSPECV_SRET)]
>""
>"sret")
>
>  (define_insn "riscv_uret"
> -  [(unspec_volatile [(const_int 0)] UNSPECV_URET)]
> +  [(return)
> +   (unspec_volatile [(const_int 0)] UNSPECV_URET)]
>""
>"uret")
>
> diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-debug.c 
> b/gcc/testsuite/gcc.target/riscv/interrupt-debug.c
> new file mode 100644
> index 000..a1b6dac8fbb
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/interrupt-debug.c
> @@ -0,0 +1,15 @@
> +/* Verify that we can compile with debug info.  */
> +/* { dg-do compile } */
> +/* { dg-options "-Og -g" } */
> +extern int var1;
> +extern int var2;
> +extern void sub2 (void);
> +
> +void __attribute__ ((interrupt))
> +sub (void)
> +{
> +  if (var1)
> +var2 = 0;
> +  else
> +sub2 ();
> +}
> --
> 2.17.1
>

Re: [PATCH] RISC-V: Fix interrupt support for -g.

[Kito Cheng]

Hi Jim:

It's no problem with current approach, I just think it can simplify
the .md file.

Thanks :)
On Tue, Jul 3, 2018 at 11:22 AM Jim Wilson  wrote:
>
> On Mon, Jul 2, 2018 at 8:04 PM, Kito Cheng  wrote:
> > Does it possible just combine those pattern into simple_return
> > pattern, and then check the function type and output correct return
> > instruction in riscv_output_return?
>
> There might be problems with optimizations thinking this is a regular
> return when it isn't.  But it might work if we have enough checks for
> the interrupt attribute in the right places.
>
> Having different patterns for different types of return instructions
> makes the RTL dumps self contained.  You can tell what kind of
> instruction it is without having to look at the source tree to see how
> the function was declared.  There is some minor benefit to that.
>
> Is there a problem with the current approach that needs fixing?
>
> Jim

[PATCH] RISC-V: Report error if function declare with different

[Kito Cheng]

Hi all:

This patch implemented TARGET_MERGE_DECL_ATTRIBUTES hook to check the
interrupter is all compatible, tested with rv32ima and rv64ima elf
toolchain.

gcc/ChangeLog
2018-07-06  Kito Cheng  

* config/riscv/riscv.c (enum riscv_privilege_levels): Add UNKNOWN_MODE.
(riscv_expand_epilogue): Add more assertion to check interrupt mode.
(riscv_set_current_function): Extract getting interrupt type to new
function.
(riscv_get_interrupt_type): New function.
(riscv_merge_decl_attributes): New function, checking interrupt type is
same.
(TARGET_MERGE_DECL_ATTRIBUTES): Define.

gcc/testsuite/ChangeLog
2018-07-06  Kito Cheng  

* gcc.target/riscv/interrupt-conflict-mode.c: New.
From ae275a1edd9b5c5f0126417542607aa667234823 Mon Sep 17 00:00:00 2001
From: Kito Cheng 
Date: Tue, 3 Jul 2018 13:29:02 +0800
Subject: [PATCH] RISC-V: Report error if function declare with different
 interrupt mode.

---
 gcc/config/riscv/riscv.c  | 82 +++
 .../riscv/interrupt-conflict-mode.c   | 10 +++
 2 files changed, 74 insertions(+), 18 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/interrupt-conflict-mode.c

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index d87836f53f8..c10c58e3cd5 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -123,7 +123,7 @@ struct GTY(())  riscv_frame_info {
 };
 
 enum riscv_privilege_levels {
-  USER_MODE, SUPERVISOR_MODE, MACHINE_MODE
+  UNKNOWN_MODE, USER_MODE, SUPERVISOR_MODE, MACHINE_MODE
 };
 
 struct GTY(())  machine_function {
@@ -3984,6 +3984,8 @@ riscv_expand_epilogue (int style)
 {
   enum riscv_privilege_levels mode = cfun->machine->interrupt_mode;
 
+  gcc_assert (mode != UNKNOWN_MODE);
+
   if (mode == MACHINE_MODE)
 	emit_jump_insn (gen_riscv_mret ());
   else if (mode == SUPERVISOR_MODE)
@@ -4530,6 +4532,37 @@ riscv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
   return true;
 }
 
+/* Get the intterupt type, return UNKNOWN_MODE if it's not
+   interrupt function. */
+static enum riscv_privilege_levels
+riscv_get_interrupt_type (tree decl)
+{
+  gcc_assert (decl != NULL_TREE);
+
+  if ((TREE_CODE(decl) != FUNCTION_DECL)
+  || (!riscv_interrupt_type_p (TREE_TYPE (decl
+return UNKNOWN_MODE;
+
+  tree attr_args
+= TREE_VALUE (lookup_attribute ("interrupt",
+TYPE_ATTRIBUTES (TREE_TYPE (decl;
+
+  if (attr_args && TREE_CODE (TREE_VALUE (attr_args)) != VOID_TYPE)
+{
+  const char *string = TREE_STRING_POINTER (TREE_VALUE (attr_args));
+
+  if (!strcmp (string, "user"))
+	return USER_MODE;
+  else if (!strcmp (string, "supervisor"))
+	return SUPERVISOR_MODE;
+  else /* Must be "machine".  */
+	return MACHINE_MODE;
+}
+  else
+/* Interrupt attributes are machine mode by default.  */
+return MACHINE_MODE;
+}
+
 /* Implement `TARGET_SET_CURRENT_FUNCTION'.  */
 /* Sanity cheching for above function attributes.  */
 static void
@@ -4554,9 +4587,6 @@ riscv_set_current_function (tree decl)
 {
   tree ret = TREE_TYPE (TREE_TYPE (decl));
   tree args = TYPE_ARG_TYPES (TREE_TYPE (decl));
-  tree attr_args
-	= TREE_VALUE (lookup_attribute ("interrupt",
-	TYPE_ATTRIBUTES (TREE_TYPE (decl;
 
   if (TREE_CODE (ret) != VOID_TYPE)
 	error ("%qs function cannot return a value", "interrupt");
@@ -4564,26 +4594,39 @@ riscv_set_current_function (tree decl)
   if (args && TREE_CODE (TREE_VALUE (args)) != VOID_TYPE)
 	error ("%qs function cannot have arguments", "interrupt");
 
-  if (attr_args && TREE_CODE (TREE_VALUE (attr_args)) != VOID_TYPE)
-	{
-	  const char *string = TREE_STRING_POINTER (TREE_VALUE (attr_args));
-
-	  if (!strcmp (string, "user"))
-	cfun->machine->interrupt_mode = USER_MODE;
-	  else if (!strcmp (string, "supervisor"))
-	cfun->machine->interrupt_mode = SUPERVISOR_MODE;
-	  else /* Must be "machine".  */
-	cfun->machine->interrupt_mode = MACHINE_MODE;
-	}
-  else
-	/* Interrupt attributes are machine mode by default.  */
-	cfun->machine->interrupt_mode = MACHINE_MODE;
+  cfun->machine->interrupt_mode = riscv_get_interrupt_type (decl);
+
+  gcc_assert (cfun->machine->interrupt_mode != UNKNOWN_MODE);
 }
 
   /* Don't print the above diagnostics more than once.  */
   cfun->machine->attributes_checked_p = 1;
 }
 
+/* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
+static tree
+riscv_merge_decl_attributes (tree olddecl, tree newdecl)
+{
+  tree combined_attrs;
+
+  enum riscv_privilege_levels old_interrupt_type
+= riscv_get_interrupt_type (olddecl);
+  enum riscv_privilege_levels new_interrupt_type
+= riscv_get_interrupt_type (newdecl);
+
+  /* Check old and new has same inte

Re: [PATCH] RISC-V: Report error if function declare with different

[Kito Cheng]

ping.
On Fri, Jul 6, 2018 at 4:38 PM Kito Cheng  wrote:
>
> Hi all:
>
> This patch implemented TARGET_MERGE_DECL_ATTRIBUTES hook to check the
> interrupter is all compatible, tested with rv32ima and rv64ima elf
> toolchain.
>
> gcc/ChangeLog
> 2018-07-06  Kito Cheng  
>
> * config/riscv/riscv.c (enum riscv_privilege_levels): Add 
> UNKNOWN_MODE.
> (riscv_expand_epilogue): Add more assertion to check interrupt mode.
> (riscv_set_current_function): Extract getting interrupt type to new
> function.
> (riscv_get_interrupt_type): New function.
> (riscv_merge_decl_attributes): New function, checking interrupt type 
> is
> same.
> (TARGET_MERGE_DECL_ATTRIBUTES): Define.
>
> gcc/testsuite/ChangeLog
> 2018-07-06  Kito Cheng  
>
> * gcc.target/riscv/interrupt-conflict-mode.c: New.

[PATCH 0/0] RISC-V: Support IEEE half precision operation

[Kito Cheng]

This patch set implement _Float16 both for softfloat and hardfloat (zfh/zfhmin),
_Float16 has introduced into RISC-V psABI[1] since Jul 2021 and zfh/zfhmin
extension has ratified since 2022[2].

[1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/172
[2] 
https://github.com/riscv/riscv-isa-manual/commit/b35a54079e0da11740ce5b1e6db999d1d5172768

[PATCH 1/2] RISC-V: Support _Float16 type.

[Kito Cheng]

RISC-V decide use _Float16 as primary IEEE half precision type, and this
already become part of psABI, this patch has added folloing support for
_Float16:

- Soft-float support for _Float16.
- Make sure _Float16 available on C++ mode.
- Name mangling for _Float16 on C++ mode.

gcc/ChangeLog

* config/riscv/riscv-builtins.cc: include stringpool.h
(riscv_float16_type_node): New.
(riscv_init_builtin_types): Ditto.
(riscv_init_builtins): Call riscv_init_builtin_types.
* config/riscv/riscv-modes.def (HF): New.
* gcc/config/riscv/riscv.cc (riscv_output_move): Handle HFmode.
(riscv_mangle_type): New.
(riscv_scalar_mode_supported_p): Ditto.
(riscv_libgcc_floating_mode_supported_p): Ditto.
(riscv_excess_precision): Ditto.
(riscv_floatn_mode): Ditto.
(riscv_init_libfuncs): Ditto.
(TARGET_MANGLE_TYPE): Ditto.
(TARGET_SCALAR_MODE_SUPPORTED_P): Ditto.
(TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P): Ditto.
(TARGET_INIT_LIBFUNCS): Ditto.
(TARGET_C_EXCESS_PRECISION): Ditto.
(TARGET_FLOATN_MODE): Ditto.
* gcc/config/riscv/riscv.md (mode): Add HF.
(softload): Add HF.
(softstore): Ditto.
(fmt): Ditto.
(UNITMODE): Ditto.
(movhf): New.
(*movhf_softfloat): New.

libgcc/ChangeLog:

* config/riscv/sfp-machine.h (_FP_NANFRAC_H): New.
(_FP_NANFRAC_H): Ditto.
(_FP_NANSIGN_H): Ditto.
* config/riscv/t-softfp32 (softfp_extensions): Add HF related
routines.
(softfp_truncations): Ditto.
(softfp_extras): Ditto.
* config/riscv/t-softfp64 (softfp_extras): Add HF related routines.

gcc/testsuite/ChangeLog:

* gcc/testsuite/g++.target/riscv/_Float16.C: New.
* gcc/testsuite/gcc.target/riscv/_Float16-soft-1.c: Ditto.
* gcc/testsuite/gcc.target/riscv/_Float16-soft-2.c: Ditto.
* gcc/testsuite/gcc.target/riscv/_Float16-soft-3.c: Ditto.
* gcc/testsuite/gcc.target/riscv/_Float16-soft-4.c: Ditto.
* gcc/testsuite/gcc.target/riscv/_Float16.c: Ditto.
---
 gcc/config/riscv/riscv-builtins.cc|  24 +++
 gcc/config/riscv/riscv-modes.def  |   1 +
 gcc/config/riscv/riscv.cc | 171 --
 gcc/config/riscv/riscv.md |  30 ++-
 gcc/testsuite/g++.target/riscv/_Float16.C |  18 ++
 .../gcc.target/riscv/_Float16-soft-1.c|   9 +
 .../gcc.target/riscv/_Float16-soft-2.c|  13 ++
 .../gcc.target/riscv/_Float16-soft-3.c|  12 ++
 .../gcc.target/riscv/_Float16-soft-4.c|  12 ++
 gcc/testsuite/gcc.target/riscv/_Float16.c |  19 ++
 libgcc/config/riscv/sfp-machine.h |   3 +
 libgcc/config/riscv/t-softfp32|   5 +
 libgcc/config/riscv/t-softfp64|   1 +
 13 files changed, 300 insertions(+), 18 deletions(-)
 create mode 100644 gcc/testsuite/g++.target/riscv/_Float16.C
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-soft-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-soft-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-soft-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-soft-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16.c

diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index 1218fdfc67d..3009311604d 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -34,6 +34,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "recog.h"
 #include "diagnostic-core.h"
 #include "stor-layout.h"
+#include "stringpool.h"
 #include "expr.h"
 #include "langhooks.h"
 
@@ -160,6 +161,8 @@ static GTY(()) int riscv_builtin_decl_index[NUM_INSN_CODES];
 #define GET_BUILTIN_DECL(CODE) \
   riscv_builtin_decls[riscv_builtin_decl_index[(CODE)]]
 
+tree riscv_float16_type_node = NULL_TREE;
+
 /* Return the function type associated with function prototype TYPE.  */
 
 static tree
@@ -185,11 +188,32 @@ riscv_build_function_type (enum riscv_function_type type)
   return types[(int) type];
 }
 
+static void
+riscv_init_builtin_types (void)
+{
+  /* Provide the _Float16 type and float16_type_node if needed.  */
+  if (!float16_type_node)
+{
+  riscv_float16_type_node = make_node (REAL_TYPE);
+  TYPE_PRECISION (riscv_float16_type_node) = 16;
+  SET_TYPE_MODE (riscv_float16_type_node, HFmode);
+  layout_type (riscv_float16_type_node);
+}
+  else
+riscv_float16_type_node = float16_type_node;
+
+  if (!maybe_get_identifier ("_Float16"))
+lang_hooks.types.register_builtin_type (riscv_float16_type_node,
+   "_Float16");
+}
+
 /* Implement TARGET_INIT_BUILTINS.  */
 
 void
 riscv_init_builtins (void)
 {
+  riscv_init_builtin_types ();
+
   for (size_t i = 0; i < ARRAY_SIZE (riscv_builtins); i++)
 {
   const struct riscv_bu

[PATCH 2/2] RISC-V: Support zfh and zfhmin extension

[Kito Cheng]

Zfh and Zfhmin are extensions for IEEE half precision, both are ratified
in Jan. 2022[1]:

- Zfh has full set of operation like F or D for single or double precision.
- Zfhmin has only provide minimal support for half precision operation,
  like conversion, load, store and move instructions.

[1] 
https://github.com/riscv/riscv-isa-manual/commit/b35a54079e0da11740ce5b1e6db999d1d5172768

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (riscv_implied_info): Add
zfh and zfhmin.
(riscv_ext_version_table): Ditto.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv-opts.h (MASK_ZFHMIN): New.
(MASK_ZFH): Ditto.
(TARGET_ZFHMIN): Ditto.
(TARGET_ZFH): Ditto.
* config/riscv/riscv.cc (riscv_output_move): Handle HFmode move
for zfh and zfhmin.
(riscv_emit_float_compare): Handle HFmode.
* config/riscv/riscv.md (ANYF): Add HF.
(SOFTF): Add HF.
(load): Ditto.
(store): Ditto.
(truncsfhf2): New.
(truncdfhf2): Ditto.
(extendhfsf2): Ditto.
(extendhfdf2): Ditto.
(*movhf_hardfloat): Ditto.
(*movhf_softfloat): Make sure not ZFHMIN.
* config/riscv/riscv.opt (riscv_zf_subext): New.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/_Float16-zfh-1.c: New.
* gcc.target/riscv/_Float16-zfh-2.c: Ditto.
* gcc.target/riscv/_Float16-zfh-3.c: Ditto.
* gcc.target/riscv/_Float16-zfhmin-1.c: Ditto.
* gcc.target/riscv/_Float16-zfhmin-2.c: Ditto.
* gcc.target/riscv/_Float16-zfhmin-3.c: Ditto.
* gcc.target/riscv/arch-16.c: Ditto.
* gcc.target/riscv/arch-17.c: Ditto.
* gcc.target/riscv/predef-21.c: Ditto.
* gcc.target/riscv/predef-22.c: Ditto.
---
 gcc/common/config/riscv/riscv-common.cc   |  8 +++
 gcc/config/riscv/riscv-opts.h |  6 ++
 gcc/config/riscv/riscv.cc | 34 ++-
 gcc/config/riscv/riscv.md | 59 +--
 gcc/config/riscv/riscv.opt|  3 +
 .../gcc.target/riscv/_Float16-zfh-1.c |  8 +++
 .../gcc.target/riscv/_Float16-zfh-2.c |  8 +++
 .../gcc.target/riscv/_Float16-zfh-3.c |  8 +++
 .../gcc.target/riscv/_Float16-zfhmin-1.c  |  9 +++
 .../gcc.target/riscv/_Float16-zfhmin-2.c  |  9 +++
 .../gcc.target/riscv/_Float16-zfhmin-3.c  |  9 +++
 gcc/testsuite/gcc.target/riscv/arch-16.c  |  5 ++
 gcc/testsuite/gcc.target/riscv/arch-17.c  |  5 ++
 gcc/testsuite/gcc.target/riscv/predef-21.c| 59 +++
 gcc/testsuite/gcc.target/riscv/predef-22.c| 59 +++
 15 files changed, 280 insertions(+), 9 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zfh-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zfh-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zfh-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-17.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-21.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-22.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 0e5be2ce105..4ee1b3198c5 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -96,6 +96,9 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"zvl32768b", "zvl16384b"},
   {"zvl65536b", "zvl32768b"},
 
+  {"zfh", "zfhmin"},
+  {"zfhmin", "f"},
+
   {NULL, NULL}
 };
 
@@ -193,6 +196,9 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zfh",   ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zfhmin",ISA_SPEC_CLASS_NONE, 1, 0},
+
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
@@ -1148,6 +1154,8 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B},
   {"zvl65536b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL65536B},
 
+  {"zfhmin",&gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
+  {"zfh",   &gcc_options::x_riscv_zf_subext, MASK_ZFH},
 
   {NULL, NULL, 0}
 };
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 1e153b3a6e7..85e869e62e3 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -153,6 +153,12 @@ enum stack_protector_guard {
 #define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0)
 #define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0)
 
+#define MASK_ZFHMIN   (1 << 0)
+#define MASK_ZFH  (1 << 1)
+
+#define TARGET_ZFHMIN 

Re: [PATCH 1/2] RISC-V: Support _Float16 type.

[Kito Cheng]

Hi Joseph:

On Wed, Jul 27, 2022 at 5:42 AM Joseph Myers  wrote:
>
> On Thu, 7 Jul 2022, Kito Cheng wrote:
>
> > +/* Implement TARGET_MANGLE_TYPE.  */
> > +
> > +static const char *
> > +riscv_mangle_type (const_tree type)
> > +{
> > +  /* Half-precision float.  */
> > +  if (TREE_CODE (type) == REAL_TYPE && TYPE_PRECISION (type) == 16)
> > +return "Dh";
>
> Are you sure you wish to use "Dh" instead of "DF16_" used on x86?  The C++
> ABI lists both
>
>  ::= Dh # IEEE 754r half-precision floating point (16 bits)
>  ::= DF  _ # ISO/IEC TS 18661 binary floating point 
> type _FloatN (N bits)
>
> without distinguishing which should be used when - maybe the choice made
> for _Float16 on RISC-V needs documenting in the RISC-V psABI?

Oh, thanks for catching this, we intend to use DF16_, the patch comes
from downstream which used __fp16 before, but we decided to use
_Float16 as RISC-V official half-precision floating point later.


> --
> Joseph S. Myers
> jos...@codesourcery.com

[PATCH] soft-fp: Update soft-fp from glibc

[Kito Cheng]

This patch is updating all soft-fp from glibc, most changes are
copyright years update, removing "Contributed by" lines and update URL for
license, and changes other than those update are adding conversion
function between IEEE half and 32-bit/64-bit integer, those functions are
required by RISC-V _Float16 support.

libgcc/ChangeLog:

* soft-fp/fixhfdi.c: New.
* soft-fp/fixhfsi.c: Likewise.
* soft-fp/fixunshfdi.c: Likewise.
* soft-fp/fixunshfsi.c: Likewise.
* soft-fp/floatdihf.c: Likewise.
* soft-fp/floatsihf.c: Likewise.
* soft-fp/floatundihf.c: Likewise.
* soft-fp/floatunsihf.c: Likewise.
* soft-fp/adddf3.c: Updating copyright years, removing "Contributed by"
lines and update URL for license.
* soft-fp/addsf3.c: Likewise.
* soft-fp/addtf3.c: Likewise.
* soft-fp/divdf3.c: Likewise.
* soft-fp/divsf3.c: Likewise.
* soft-fp/divtf3.c: Likewise.
* soft-fp/double.h: Likewise.
* soft-fp/eqdf2.c: Likewise.
* soft-fp/eqhf2.c: Likewise.
* soft-fp/eqsf2.c: Likewise.
* soft-fp/eqtf2.c: Likewise.
* soft-fp/extenddftf2.c: Likewise.
* soft-fp/extended.h: Likewise.
* soft-fp/extendhfdf2.c: Likewise.
* soft-fp/extendhfsf2.c: Likewise.
* soft-fp/extendhftf2.c: Likewise.
* soft-fp/extendhfxf2.c: Likewise.
* soft-fp/extendsfdf2.c: Likewise.
* soft-fp/extendsftf2.c: Likewise.
* soft-fp/extendxftf2.c: Likewise.
* soft-fp/fixdfdi.c: Likewise.
* soft-fp/fixdfsi.c: Likewise.
* soft-fp/fixdfti.c: Likewise.
* soft-fp/fixhfti.c: Likewise.
* soft-fp/fixsfdi.c: Likewise.
* soft-fp/fixsfsi.c: Likewise.
* soft-fp/fixsfti.c: Likewise.
* soft-fp/fixtfdi.c: Likewise.
* soft-fp/fixtfsi.c: Likewise.
* soft-fp/fixtfti.c: Likewise.
* soft-fp/fixunsdfdi.c: Likewise.
* soft-fp/fixunsdfsi.c: Likewise.
* soft-fp/fixunsdfti.c: Likewise.
* soft-fp/fixunshfti.c: Likewise.
* soft-fp/fixunssfdi.c: Likewise.
* soft-fp/fixunssfsi.c: Likewise.
* soft-fp/fixunssfti.c: Likewise.
* soft-fp/fixunstfdi.c: Likewise.
* soft-fp/fixunstfsi.c: Likewise.
* soft-fp/fixunstfti.c: Likewise.
* soft-fp/floatdidf.c: Likewise.
* soft-fp/floatdisf.c: Likewise.
* soft-fp/floatditf.c: Likewise.
* soft-fp/floatsidf.c: Likewise.
* soft-fp/floatsisf.c: Likewise.
* soft-fp/floatsitf.c: Likewise.
* soft-fp/floattidf.c: Likewise.
* soft-fp/floattihf.c: Likewise.
* soft-fp/floattisf.c: Likewise.
* soft-fp/floattitf.c: Likewise.
* soft-fp/floatundidf.c: Likewise.
* soft-fp/floatundisf.c: Likewise.
* soft-fp/floatunditf.c: Likewise.
* soft-fp/floatunsidf.c: Likewise.
* soft-fp/floatunsisf.c: Likewise.
* soft-fp/floatunsitf.c: Likewise.
* soft-fp/floatuntidf.c: Likewise.
* soft-fp/floatuntihf.c: Likewise.
* soft-fp/floatuntisf.c: Likewise.
* soft-fp/floatuntitf.c: Likewise.
* soft-fp/gedf2.c: Likewise.
* soft-fp/gesf2.c: Likewise.
* soft-fp/getf2.c: Likewise.
* soft-fp/half.h: Likewise.
* soft-fp/ledf2.c: Likewise.
* soft-fp/lesf2.c: Likewise.
* soft-fp/letf2.c: Likewise.
* soft-fp/muldf3.c: Likewise.
* soft-fp/mulsf3.c: Likewise.
* soft-fp/multf3.c: Likewise.
* soft-fp/negdf2.c: Likewise.
* soft-fp/negsf2.c: Likewise.
* soft-fp/negtf2.c: Likewise.
* soft-fp/op-1.h: Likewise.
* soft-fp/op-2.h: Likewise.
* soft-fp/op-4.h: Likewise.
* soft-fp/op-8.h: Likewise.
* soft-fp/op-common.h: Likewise.
* soft-fp/quad.h: Likewise.
* soft-fp/single.h: Likewise.
* soft-fp/soft-fp.h: Likewise.
* soft-fp/subdf3.c: Likewise.
* soft-fp/subsf3.c: Likewise.
* soft-fp/subtf3.c: Likewise.
* soft-fp/truncdfhf2.c: Likewise.
* soft-fp/truncdfsf2.c: Likewise.
* soft-fp/truncsfhf2.c: Likewise.
* soft-fp/trunctfdf2.c: Likewise.
* soft-fp/trunctfhf2.c: Likewise.
* soft-fp/trunctfsf2.c: Likewise.
* soft-fp/trunctfxf2.c: Likewise.
* soft-fp/truncxfhf2.c: Likewise.
* soft-fp/unorddf2.c: Likewise.
* soft-fp/unordsf2.c: Likewise.
---
 libgcc/soft-fp/adddf3.c  |  6 ++---
 libgcc/soft-fp/addsf3.c  |  6 ++---
 libgcc/soft-fp/addtf3.c  |  6 ++---
 libgcc/soft-fp/divdf3.c  |  6 ++---
 libgcc/soft-fp/divsf3.c  |  6 ++---
 libgcc/soft-fp/divtf3.c  |  6 ++---
 libgcc/soft-fp/double.h  |  8 ++-
 libgcc/soft-fp/eqdf2.c   |  6 ++---
 libgcc/soft-fp/eqhf2.c   |  2 +-
 libgcc/soft-fp/eqsf2.c   |  6 ++---
 libgcc/soft-fp/eqtf2.c   |  6 ++---
 libgcc/soft-fp/extenddftf2.c |  6 ++

[PATCH 0/2] RISC-V: Support _Float16 type and implement zfh and zfhmin extension

[Kito Cheng]

This patch set implements Zfh and Zfhmin, adds soft-float for _Float16, and 
enables _Float16 type in C++ mode.

Zfh and Zfhmin are extensions for IEEE half precision, both are ratified in 
Jan. 2022[1]

v2 Changes:
Fix mangling for C++ mode to fit the RISC-V psABI spec.


[1] 
https://github.com/riscv/riscv-isa-manual/commit/b35a54079e0da11740ce5b1e6db999d1d5172768

[PATCH v2 1/2] RISC-V: Support _Float16 type.

[Kito Cheng]

RISC-V decide use _Float16 as primary IEEE half precision type, and this
already become part of psABI, this patch has added folloing support for
_Float16:

- Soft-float support for _Float16.
- Make sure _Float16 available on C++ mode.
- Name mangling for _Float16 on C++ mode.

gcc/ChangeLog

* config/riscv/riscv-builtins.cc: include stringpool.h
(riscv_float16_type_node): New.
(riscv_init_builtin_types): Ditto.
(riscv_init_builtins): Call riscv_init_builtin_types.
* config/riscv/riscv-modes.def (HF): New.
* gcc/config/riscv/riscv.cc (riscv_output_move): Handle HFmode.
(riscv_mangle_type): New.
(riscv_scalar_mode_supported_p): Ditto.
(riscv_libgcc_floating_mode_supported_p): Ditto.
(riscv_excess_precision): Ditto.
(riscv_floatn_mode): Ditto.
(riscv_init_libfuncs): Ditto.
(TARGET_MANGLE_TYPE): Ditto.
(TARGET_SCALAR_MODE_SUPPORTED_P): Ditto.
(TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P): Ditto.
(TARGET_INIT_LIBFUNCS): Ditto.
(TARGET_C_EXCESS_PRECISION): Ditto.
(TARGET_FLOATN_MODE): Ditto.
* gcc/config/riscv/riscv.md (mode): Add HF.
(softload): Add HF.
(softstore): Ditto.
(fmt): Ditto.
(UNITMODE): Ditto.
(movhf): New.
(*movhf_softfloat): New.

libgcc/ChangeLog:

* config/riscv/sfp-machine.h (_FP_NANFRAC_H): New.
(_FP_NANFRAC_H): Ditto.
(_FP_NANSIGN_H): Ditto.
* config/riscv/t-softfp32 (softfp_extensions): Add HF related
routines.
(softfp_truncations): Ditto.
(softfp_extras): Ditto.
* config/riscv/t-softfp64 (softfp_extras): Add HF related routines.

gcc/testsuite/ChangeLog:

* gcc/testsuite/g++.target/riscv/_Float16.C: New.
* gcc/testsuite/gcc.target/riscv/_Float16-soft-1.c: Ditto.
* gcc/testsuite/gcc.target/riscv/_Float16-soft-2.c: Ditto.
* gcc/testsuite/gcc.target/riscv/_Float16-soft-3.c: Ditto.
* gcc/testsuite/gcc.target/riscv/_Float16-soft-4.c: Ditto.
* gcc/testsuite/gcc.target/riscv/_Float16.c: Ditto.
---
 gcc/config/riscv/riscv-builtins.cc|  24 +++
 gcc/config/riscv/riscv-modes.def  |   1 +
 gcc/config/riscv/riscv.cc | 171 --
 gcc/config/riscv/riscv.md |  30 ++-
 gcc/testsuite/g++.target/riscv/_Float16.C |  18 ++
 .../gcc.target/riscv/_Float16-soft-1.c|   9 +
 .../gcc.target/riscv/_Float16-soft-2.c|  13 ++
 .../gcc.target/riscv/_Float16-soft-3.c|  12 ++
 .../gcc.target/riscv/_Float16-soft-4.c|  12 ++
 gcc/testsuite/gcc.target/riscv/_Float16.c |  19 ++
 libgcc/config/riscv/sfp-machine.h |   3 +
 libgcc/config/riscv/t-softfp32|   5 +
 libgcc/config/riscv/t-softfp64|   1 +
 13 files changed, 300 insertions(+), 18 deletions(-)
 create mode 100644 gcc/testsuite/g++.target/riscv/_Float16.C
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-soft-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-soft-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-soft-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-soft-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16.c

diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index 1218fdfc67d..3009311604d 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -34,6 +34,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "recog.h"
 #include "diagnostic-core.h"
 #include "stor-layout.h"
+#include "stringpool.h"
 #include "expr.h"
 #include "langhooks.h"
 
@@ -160,6 +161,8 @@ static GTY(()) int riscv_builtin_decl_index[NUM_INSN_CODES];
 #define GET_BUILTIN_DECL(CODE) \
   riscv_builtin_decls[riscv_builtin_decl_index[(CODE)]]
 
+tree riscv_float16_type_node = NULL_TREE;
+
 /* Return the function type associated with function prototype TYPE.  */
 
 static tree
@@ -185,11 +188,32 @@ riscv_build_function_type (enum riscv_function_type type)
   return types[(int) type];
 }
 
+static void
+riscv_init_builtin_types (void)
+{
+  /* Provide the _Float16 type and float16_type_node if needed.  */
+  if (!float16_type_node)
+{
+  riscv_float16_type_node = make_node (REAL_TYPE);
+  TYPE_PRECISION (riscv_float16_type_node) = 16;
+  SET_TYPE_MODE (riscv_float16_type_node, HFmode);
+  layout_type (riscv_float16_type_node);
+}
+  else
+riscv_float16_type_node = float16_type_node;
+
+  if (!maybe_get_identifier ("_Float16"))
+lang_hooks.types.register_builtin_type (riscv_float16_type_node,
+   "_Float16");
+}
+
 /* Implement TARGET_INIT_BUILTINS.  */
 
 void
 riscv_init_builtins (void)
 {
+  riscv_init_builtin_types ();
+
   for (size_t i = 0; i < ARRAY_SIZE (riscv_builtins); i++)
 {
   const struct riscv_bu

[PATCH v2 2/2] RISC-V: Support zfh and zfhmin extension

[Kito Cheng]

Zfh and Zfhmin are extensions for IEEE half precision, both are ratified
in Jan. 2022[1]:

- Zfh has full set of operation like F or D for single or double precision.
- Zfhmin has only provide minimal support for half precision operation,
  like conversion, load, store and move instructions.

[1] 
https://github.com/riscv/riscv-isa-manual/commit/b35a54079e0da11740ce5b1e6db999d1d5172768

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (riscv_implied_info): Add
zfh and zfhmin.
(riscv_ext_version_table): Ditto.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv-opts.h (MASK_ZFHMIN): New.
(MASK_ZFH): Ditto.
(TARGET_ZFHMIN): Ditto.
(TARGET_ZFH): Ditto.
* config/riscv/riscv.cc (riscv_output_move): Handle HFmode move
for zfh and zfhmin.
(riscv_emit_float_compare): Handle HFmode.
* config/riscv/riscv.md (ANYF): Add HF.
(SOFTF): Add HF.
(load): Ditto.
(store): Ditto.
(truncsfhf2): New.
(truncdfhf2): Ditto.
(extendhfsf2): Ditto.
(extendhfdf2): Ditto.
(*movhf_hardfloat): Ditto.
(*movhf_softfloat): Make sure not ZFHMIN.
* config/riscv/riscv.opt (riscv_zf_subext): New.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/_Float16-zfh-1.c: New.
* gcc.target/riscv/_Float16-zfh-2.c: Ditto.
* gcc.target/riscv/_Float16-zfh-3.c: Ditto.
* gcc.target/riscv/_Float16-zfhmin-1.c: Ditto.
* gcc.target/riscv/_Float16-zfhmin-2.c: Ditto.
* gcc.target/riscv/_Float16-zfhmin-3.c: Ditto.
* gcc.target/riscv/arch-16.c: Ditto.
* gcc.target/riscv/arch-17.c: Ditto.
* gcc.target/riscv/predef-21.c: Ditto.
* gcc.target/riscv/predef-22.c: Ditto.
---
 gcc/common/config/riscv/riscv-common.cc   |  8 +++
 gcc/config/riscv/riscv-opts.h |  6 ++
 gcc/config/riscv/riscv.cc | 33 ++-
 gcc/config/riscv/riscv.md | 59 +--
 gcc/config/riscv/riscv.opt|  3 +
 .../gcc.target/riscv/_Float16-zfh-1.c |  8 +++
 .../gcc.target/riscv/_Float16-zfh-2.c |  8 +++
 .../gcc.target/riscv/_Float16-zfh-3.c |  8 +++
 .../gcc.target/riscv/_Float16-zfhmin-1.c  |  9 +++
 .../gcc.target/riscv/_Float16-zfhmin-2.c  |  9 +++
 .../gcc.target/riscv/_Float16-zfhmin-3.c  |  9 +++
 gcc/testsuite/gcc.target/riscv/arch-16.c  |  5 ++
 gcc/testsuite/gcc.target/riscv/arch-17.c  |  5 ++
 gcc/testsuite/gcc.target/riscv/predef-21.c| 59 +++
 gcc/testsuite/gcc.target/riscv/predef-22.c| 59 +++
 15 files changed, 279 insertions(+), 9 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zfh-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zfh-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zfh-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-17.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-21.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-22.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 0e5be2ce105..4ee1b3198c5 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -96,6 +96,9 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"zvl32768b", "zvl16384b"},
   {"zvl65536b", "zvl32768b"},
 
+  {"zfh", "zfhmin"},
+  {"zfhmin", "f"},
+
   {NULL, NULL}
 };
 
@@ -193,6 +196,9 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zfh",   ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zfhmin",ISA_SPEC_CLASS_NONE, 1, 0},
+
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
@@ -1148,6 +1154,8 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B},
   {"zvl65536b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL65536B},
 
+  {"zfhmin",&gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
+  {"zfh",   &gcc_options::x_riscv_zf_subext, MASK_ZFH},
 
   {NULL, NULL, 0}
 };
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 1e153b3a6e7..85e869e62e3 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -153,6 +153,12 @@ enum stack_protector_guard {
 #define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0)
 #define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0)
 
+#define MASK_ZFHMIN   (1 << 0)
+#define MASK_ZFH  (1 << 1)
+
+#define TARGET_ZFHMIN 

Re: [PATCH] RISC-V: Rename some variables of vector_block_info[NFC]

[Kito Cheng]

> 1. Remove "m_" prefix as they are not private members.

Actually it's not only for private members[1], but I think it's not
mandatory, anyway it's not objection, and I am OK with that, just
share the doc

[1] "When structs and/or classes have member functions, prefer to name
data members with a leading m_ and static data members with a leading
s_."
https://gcc.gnu.org/codingconventions.html

Re: [PATCH] RISC-V: Fix ICE for the fusion case from vsetvl to scalar move[PR111927]

[Kito Cheng]

Few minor comments:

On Mon, Oct 23, 2023 at 5:04 PM Juzhe-Zhong  wrote:
>
> ICE:
>
> during RTL pass: vsetvl
> : In function 'riscv_lms_f32':
> :240:1: internal compiler error: in merge, at 
> config/riscv/riscv-vsetvl.cc:1997
>   240 | }
>
> In general compatible_p (avl_equal_p) has:
>
> if (next.has_vl () && next.vl_used_by_non_rvv_insn_p ())
>   return false;
>
> Don't fuse AVL of vsetvl if the VL operand is used by non-RVV instructrions.

instructrions -> instructions

>
> It is reasonable to add it into 'can_use_next_avl_p' since we don't want to
> fuse AVL of vsetvl into a scalar move instruction which doesn't demand AVL.
> And after the fusion, we will alway use compatible_p to check whether the 
> demand
> is correct or not.
>
> PR target/111927
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc: Fix ICE.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/vsetvl/pr111927.c: New test.
>
> ---
>  gcc/config/riscv/riscv-vsetvl.cc  |  23 ++
>  .../gcc.target/riscv/rvv/vsetvl/pr111927.c| 243 ++
>  2 files changed, 266 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc 
> b/gcc/config/riscv/riscv-vsetvl.cc
> index 47b459fddd4..42295732ed7 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -1541,6 +1541,29 @@ private:
>inline bool can_use_next_avl_p (const vsetvl_info &prev,
>   const vsetvl_info &next)
>{
> +/* Forbid the AVL/VL propagation if VL of NEXT is used
> +   by non-RVV instructions.  This is because:
> +
> +bb 2:
> +  scalar move (no AVL)

Could you add few comment to mention this is prev

> +bb 3:
> +  vsetvl a5(VL), a4(AVL) ...

and this is next

> +  branch a5,zero
> +
> +   Since user vsetvl instruction is no side effect instruction
> +   which should be placed in the correct and optimal location
> +   of the program by the previous PASS, it is unreasonble that

unreasonble -> unreasonable

> +   VSETVL PASS tries to move it to another places if it used by
> +   non-RVV instructions.
> +
> +   Note: We only forbid the cases that VL is used by the following
> +   non-RVV instructions which will cause issues.  We don't forbid
> +   other cases since it won't cause correctness issues and we still
> +   more more demand info are fused backward.  The later LCM algorithm

more more -> more

> +   should know the optimal location of the vsetvl.  */
> +if (next.has_vl () && next.vl_used_by_non_rvv_insn_p ())
> +  return false;
> +
>  if (!next.has_nonvlmax_reg_avl () && !next.has_vl ())
>return true;
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c
> new file mode 100644
> index 000..62f395fee33
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c
> @@ -0,0 +1,243 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +#include "riscv_vector.h"
> +#include 

Including stdio.h will cause multi-lib testing issues, and I don't saw
any function or declaration defined in stdio.h are used in the file,
so I assume this is safe to remove

and could you clean up the testcase? at least drop those unused #else parts?

Re: [PATCH V2] RISC-V: Fix ICE for the fusion case from vsetvl to scalar move[PR111927]

[Kito Cheng]

LGTM

Juzhe-Zhong  於 2023年10月23日 週一 17:41 寫道：

> ICE:
>
> during RTL pass: vsetvl
> : In function 'riscv_lms_f32':
> :240:1: internal compiler error: in merge, at
> config/riscv/riscv-vsetvl.cc:1997
>   240 | }
>
> In general compatible_p (avl_equal_p) has:
>
> if (next.has_vl () && next.vl_used_by_non_rvv_insn_p ())
>   return false;
>
> Don't fuse AVL of vsetvl if the VL operand is used by non-RVV instructions.
>
> It is reasonable to add it into 'can_use_next_avl_p' since we don't want to
> fuse AVL of vsetvl into a scalar move instruction which doesn't demand AVL.
> And after the fusion, we will alway use compatible_p to check whether the
> demand
> is correct or not.
>
> PR target/111927
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc: Fix bug.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/vsetvl/pr111927.c: New test.
>
> ---
>  gcc/config/riscv/riscv-vsetvl.cc  |  23 +++
>  .../gcc.target/riscv/rvv/vsetvl/pr111927.c| 170 ++
>  2 files changed, 193 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc
> b/gcc/config/riscv/riscv-vsetvl.cc
> index 47b459fddd4..f3922a051c5 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -1541,6 +1541,29 @@ private:
>inline bool can_use_next_avl_p (const vsetvl_info &prev,
>   const vsetvl_info &next)
>{
> +/* Forbid the AVL/VL propagation if VL of NEXT is used
> +   by non-RVV instructions.  This is because:
> +
> +bb 2:
> +  PREV: scalar move (no AVL)
> +bb 3:
> +  NEXT: vsetvl a5(VL), a4(AVL) ...
> +  branch a5,zero
> +
> +   Since user vsetvl instruction is no side effect instruction
> +   which should be placed in the correct and optimal location
> +   of the program by the previous PASS, it is unreasonable that
> +   VSETVL PASS tries to move it to another places if it used by
> +   non-RVV instructions.
> +
> +   Note: We only forbid the cases that VL is used by the following
> +   non-RVV instructions which will cause issues.  We don't forbid
> +   other cases since it won't cause correctness issues and we still
> +   more demand info are fused backward.  The later LCM algorithm
> +   should know the optimal location of the vsetvl.  */
> +if (next.has_vl () && next.vl_used_by_non_rvv_insn_p ())
> +  return false;
> +
>  if (!next.has_nonvlmax_reg_avl () && !next.has_vl ())
>return true;
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c
> new file mode 100644
> index 000..ab599add57f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c
> @@ -0,0 +1,170 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +#define RISCV_MATH_LOOPUNROLL
> +#define RISCV_MATH_VECTOR
> +typedef  float float32_t;
> +
> +  typedef struct
> +  {
> +  uint16_t numTaps;/**< number of coefficients in the filter.
> */
> +  float32_t *pState;   /**< points to the state variable array.
> The array is of length numTaps+blockSize-1. */
> +  float32_t *pCoeffs;  /**< points to the coefficient array. The
> array is of length numTaps. */
> +  float32_t mu;/**< step size that controls filter
> coefficient updates. */
> +  } riscv_lms_instance_f32;
> +
> +
> +void riscv_lms_f32(
> +  const riscv_lms_instance_f32 * S,
> +  const float32_t * pSrc,
> +float32_t * pRef,
> +float32_t * pOut,
> +float32_t * pErr,
> +uint32_t blockSize)
> +{
> +float32_t *pState = S->pState; /* State pointer */
> +float32_t *pCoeffs = S->pCoeffs;   /* Coefficient
> pointer */
> +float32_t *pStateCurnt;/* Points to the
> current sample of the state */
> +float32_t *px, *pb;/* Temporary
> pointers for state and coefficient buffers */
> +float32_t mu = S->mu;  /* Adaptive factor
> */
> +float32_t acc, e;  /* Accumulator,
> error */
> +float32_t w;   /* Weight factor */
> +uint32_t numTaps = S->numTaps; /* Number of
> filter coefficients in the filter */
> +uint32_t tapCnt, blkCnt;   /* Loop counters */
> +
> +  /* Initializations of error,  difference, Coefficient update */
> +  e = 0.0f;
> +  w = 0.0f;
> +
> +  /* S->pState points to state array which contains previous frame
> (numTaps - 1) samples */
> +  /* pStateCurnt points to the location where the new input data should
> be written */
> +  pStateCurnt = &(S->pState[(numTaps - 1U)]);
> +
> +  /* init

Re: Re: [PATCH v2] RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935]

[Kito Cheng]

Ok for gcc 13 but just wait one more week to make sure everything is fine
as gcc convention :)

Li Xu 於 2023年10月24日 週二，15:49寫道：

> Committed to trunk. Thanks juzhe.
>
>
> --
>
>
>
> Li Xu
>
>
>
> >Ok for trunk (You can commit it to the trunk now).
>
>
>
> >
>
>
>
> >For GCC-13,  I'd like to wait for kito's comment.
>
>
>
> >
>
>
>
> >Thanks.
>
>
>
> >
>
>
>
> >
>
>
>
> >juzhe.zh...@rivai.ai
>
>
>
> >
>
>
>
> >From: Li Xu
>
>
>
> >Date: 2023-10-24 15:29
>
>
>
> >To: gcc-patches
>
>
>
> >CC: kito.cheng; palmer; juzhe.zhong
>
>
>
> >Subject: [PATCH v2] RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935]
>
>
>
> >
>
>
>
> >Calling vget/vset intrinsic without receiving a return value will cause
>
>
>
> >a crash. Because in this case e.target is null.
>
>
>
> >This patch should be backported to releases/gcc-13.
>
>
>
> >
>
>
>
> >PR/target 111935
>
>
>
> >
>
>
>
> >gcc/ChangeLog:
>
>
>
> >
>
>
>
> >* config/riscv/riscv-vector-builtins-bases.cc: fix bug.
>
>
>
> >
>
>
>
> >gcc/testsuite/ChangeLog:
>
>
>
> >
>
>
>
> >* gcc.target/riscv/rvv/base/pr111935.c: New test.
>
>
>
> >---
>
>
>
> > .../riscv/riscv-vector-builtins-bases.cc  |  4 +++
>
>
>
> > .../gcc.target/riscv/rvv/base/pr111935.c  | 26 +++
>
>
>
> > 2 files changed, 30 insertions(+)
>
>
>
> > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c
>
>
>
> >
>
>
>
> >diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> b/gcc/config/riscv/riscv-vector-builtins-bases.cc
>
>
>
> >index ab12e130907..0b1409a52e0 100644
>
>
>
> >--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
>
>
>
> >+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
>
>
>
> >@@ -1740,6 +1740,8 @@ public:
>
>
>
> >
>
>
>
> >   rtx expand (function_expander &e) const override
>
>
>
> >   {
>
>
>
> >+if (!e.target)
>
>
>
> >+  return NULL_RTX;
>
>
>
> > rtx dest = expand_normal (CALL_EXPR_ARG (e.exp, 0));
>
>
>
> > gcc_assert (riscv_v_ext_vector_mode_p (GET_MODE (dest)));
>
>
>
> > rtx index = expand_normal (CALL_EXPR_ARG (e.exp, 1));
>
>
>
> >@@ -1777,6 +1779,8 @@ public:
>
>
>
> >
>
>
>
> >   rtx expand (function_expander &e) const override
>
>
>
> >   {
>
>
>
> >+if (!e.target)
>
>
>
> >+  return NULL_RTX;
>
>
>
> > rtx src = expand_normal (CALL_EXPR_ARG (e.exp, 0));
>
>
>
> > gcc_assert (riscv_v_ext_vector_mode_p (GET_MODE (src)));
>
>
>
> > rtx index = expand_normal (CALL_EXPR_ARG (e.exp, 1));
>
>
>
> >diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c
>
>
>
> >new file mode 100644
>
>
>
> >index 000..0b936d849a1
>
>
>
> >--- /dev/null
>
>
>
> >+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111935.c
>
>
>
> >@@ -0,0 +1,26 @@
>
>
>
> >+/* { dg-do compile } */
>
>
>
> >+/* { dg-options "-march=rv64gcv -mabi=lp64d -O0 -Wno-psabi" } */
>
>
>
> >+
>
>
>
> >+#include "riscv_vector.h"
>
>
>
> >+
>
>
>
> >+inline vuint32m4_t __attribute__((__always_inline__))
> transpose_indexes() {
>
>
>
> >+  static const uint32_t idx_[16] = {0, 4, 8, 12,
>
>
>
> >+  1, 5, 9, 13,
>
>
>
> >+  2, 6, 10, 14,
>
>
>
> >+  3, 7, 11, 15};
>
>
>
> >+  return __riscv_vle32_v_u32m4(idx_, 16);
>
>
>
> >+}
>
>
>
> >+
>
>
>
> >+void pffft_real_preprocess_4x4(const float *in) {
>
>
>
> >+  vfloat32m1_t r0=__riscv_vle32_v_f32m1(in,4);
>
>
>
> >+  vfloat32m4_t tmp = __riscv_vundefined_f32m4();
>
>
>
> >+  tmp = __riscv_vset_v_f32m1_f32m4(tmp, 0, r0);
>
>
>
> >+  tmp = __riscv_vset_v_f32m1_f32m4(tmp, 1, r0);
>
>
>
> >+  tmp = __riscv_vset_v_f32m1_f32m4(tmp, 2, r0);
>
>
>
> >+  tmp = __riscv_vset_v_f32m1_f32m4(tmp, 3, r0);
>
>
>
> >+  tmp = __riscv_vrgather_vv_f32m4(tmp, transpose_indexes(), 16);
>
>
>
> >+  r0 = __riscv_vget_v_f32m4_f32m1(tmp, 0);
>
>
>
> >+}
>
>
>
> >+
>
>
>
> >+/* { dg-final { scan-assembler-times
> {vl[0-9]+re[0-9]+\.v\s+v[0-9]+,\s*0\([a-z]+[0-9]+\)} 10 } } */
>
>
>
> >+/* { dg-final { scan-assembler-times
> {vs[0-9]+r\.v\s+v[0-9]+,\s*0\([a-z]+[0-9]+\)} 8 } } */
>
>
>
> >--
>
>
>
> >2.17.1
>
>
>
> >
>
>
>
> >
>
>
>
> >xu...@eswincomputing.com
>
>
>

Re: [PATCH] RISC-V: Add AVL propagation PASS for RVV auto-vectorization

[Kito Cheng]

> +using namespace rtl_ssa;
> +using namespace riscv_vector;
> +
> +/* The AVL propagation instructions and corresponding preferred AVL.
> +   It will be updated during the analysis.  */
> +static hash_map *avlprops;

Maybe put into member data of pass_avlprop?

> +
> +const pass_data pass_data_avlprop = {
> +  RTL_PASS, /* type */
> +  "avlprop",/* name */
> +  OPTGROUP_NONE, /* optinfo_flags */
> +  TV_NONE,  /* tv_id */
> +  0,/* properties_required */
> +  0,/* properties_provided */
> +  0,/* properties_destroyed */
> +  0,/* todo_flags_start */
> +  0,/* todo_flags_finish */
> +};
> +
> +class pass_avlprop : public rtl_opt_pass
> +{
> +public:
> +  pass_avlprop (gcc::context *ctxt) : rtl_opt_pass (pass_data_avlprop, ctxt) 
> {}
> +
> +  /* opt_pass methods: */
> +  virtual bool gate (function *) final override
> +  {
> +return TARGET_VECTOR && optimize > 0;
> +  }
> +  virtual unsigned int execute (function *) final override;
> +}; // class pass_avlprop
> +
> +static void
> +avlprop_init (void)

Maybe put into member function of pass_avlprop?

> +{
> +  calculate_dominance_info (CDI_DOMINATORS);
> +  df_analyze ();
> +  crtl->ssa = new function_info (cfun);

And take function * from incomping parameter of execute

> +  avlprops = new hash_map;
> +}
> +
> +static void
> +avlprop_done (void)
> +{
> +  free_dominance_info (CDI_DOMINATORS);
> +  if (crtl->ssa->perform_pending_updates ())
> +cleanup_cfg (0);
> +  delete crtl->ssa;
> +  crtl->ssa = nullptr;
> +  delete avlprops;
> +  avlprops = NULL;
> +}
> +
> +/* Helper function to get AVL operand.  */
> +static rtx
> +get_avl (insn_info *insn, bool avlprop_p)
> +{
> +  if (get_attr_avl_type (insn->rtl ()) == INVALID_ATTRIBUTE
> +  || get_attr_avl_type (insn->rtl ()) == VLS)
> +return NULL_RTX;
> +  if (avlprop_p)
> +{
> +  if (avlprops->get (insn))
> +   return (*avlprops->get (insn));
> +  else if (vlmax_avl_type_p (insn->rtl ()))
> +   return RVV_VLMAX;

I guess I didn't get why we need handle vlmax_avl_type_p here?

> +}
> +  extract_insn_cached (insn->rtl ());
> +  return recog_data.operand[get_attr_vl_op_idx (insn->rtl ())];
> +}
> +
> +/* This is a straight forward pattern ALWAYS in paritial auto-vectorization:
> +
> + VL = SELECT_AVL (AVL, ...)
> + V0 = MASK_LEN_LOAD (..., VL)
> + V1 = MASK_LEN_LOAD (..., VL)
> + V2 = V0 + V1 --- Missed LEN information.
> + MASK_LEN_STORE (..., V2, VL)
> +
> +   We prefer PLUS_EXPR (V0 + V1) instead of COND_LEN_ADD (V0, V1, dummy LEN)
> +   because:
> +
> + - Few code changes in Loop Vectorizer.
> + - Reuse the current clean flow of partial vectorization, That is, apply
> +   predicate LEN or MASK into LOAD/STORE operations and other special
> +   arithmetic operations (e.d. DIV), then do the whole vector register
> +   operation if it DON'T affect the correctness.
> +   Such flow is used by all other targets like x86, sve, s390, ... etc.
> + - PLUS_EXPR has better gimple optimizations than COND_LEN_ADD.
> +
> +   We propagate AVL from NON-VLMAX to VLMAX for gimple IR like PLUS_EXPR 
> which
> +   generates the VLMAX instruction due to missed LEN information. The later
> +   VSETVL PASS will elided the redundant vsetvls.
> +*/
> +
> +static rtx
> +get_autovectorize_preferred_avl (insn_info *insn)
> +{
> +  if (!vlmax_avl_p (get_avl (insn, true)) || !tail_agnostic_p (insn->rtl ()))
> +return NULL_RTX;

I would prefer adding new attribute to let this become simpler.

> +
> +  rtx use_avl = NULL_RTX;
> +  insn_info *avl_use_insn = nullptr;
> +  unsigned int ratio
> += calculate_ratio (get_sew (insn->rtl ()), get_vlmul (insn->rtl ()));
> +  for (def_info *def : insn->defs ())
> +{
> +  auto set = safe_dyn_cast (def);
> +  if (!set || !set->is_reg ())
> +   return NULL_RTX;
> +  for (use_info *use : set->all_uses ())
> +   {
> + if (!use->is_in_nondebug_insn ())
> +   return NULL_RTX;
> + insn_info *use_insn = use->insn ();
> + /* FIXME: Stop AVL propagation if any USE is not a RVV real
> +instruction. It should be totally enough for vectorized codes 
> since
> +they always locate at extended blocks.
> +
> +TODO: We can extend PHI checking for intrinsic codes if it
> +necessary in the future.  */
> + if (use_insn->is_artificial () || !has_vtype_op (use_insn->rtl ()))
> +   return NULL_RTX;
> + if (!has_vl_op (use_insn->rtl ()))
> +   continue;
> +
> + rtx new_use_avl = get_avl (use_insn, true);
> + if (!new_use_avl)
> +   return NULL_RTX;
> + if (!use_avl)
> +   use_avl = new_use_avl;
> + if (!rtx_equal_p (use_avl, new_use_avl)
> + || calculate_ratio (get_sew (use_insn->rtl ()),
> + get_vlmul (use_insn->rtl ()))
> +  

Re: [PATCH] RISC-V: Export some functions from riscv-vsetvl to riscv-v

[Kito Cheng]

LGTM, but plz mention it's NFC in the title, no v2 needed :)

On Wed, Oct 25, 2023 at 5:03 PM Juzhe-Zhong  wrote:
>
> Address kito's comments of AVL propagation patch.
>
> Export the functions that are not only used by VSETVL PASS but also AVL 
> propagation PASS.
>
> No functionality change.
> gcc/ChangeLog:
>
> * config/riscv/riscv-protos.h (has_vl_op): Export from riscv-vsetvl 
> to riscv-v
> (tail_agnostic_p): Ditto.
> (validate_change_or_fail): Ditto.
> (nonvlmax_avl_type_p): Ditto.
> (vlmax_avl_p): Ditto.
> (get_sew): Ditto.
> (enum vlmul_type): Ditto.
> (count_regno_occurrences): Ditto.
> * config/riscv/riscv-v.cc (has_vl_op): Ditto.
> (get_default_ta): Ditto.
> (tail_agnostic_p): Ditto.
> (validate_change_or_fail): Ditto.
> (nonvlmax_avl_type_p): Ditto.
> (vlmax_avl_p): Ditto.
> (get_sew): Ditto.
> (enum vlmul_type): Ditto.
> (get_vlmul): Ditto.
> (count_regno_occurrences): Ditto.
> * config/riscv/riscv-vsetvl.cc (vlmax_avl_p): Ditto.
> (has_vl_op): Ditto.
> (get_sew): Ditto.
> (get_vlmul): Ditto.
> (get_default_ta): Ditto.
> (tail_agnostic_p): Ditto.
> (count_regno_occurrences): Ditto.
> (validate_change_or_fail): Ditto.
>
> ---
>  gcc/config/riscv/riscv-protos.h  |  8 +++
>  gcc/config/riscv/riscv-v.cc  | 83 
>  gcc/config/riscv/riscv-vsetvl.cc | 70 ---
>  3 files changed, 91 insertions(+), 70 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index fffd9cd0b8a..668d75043ca 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -560,6 +560,14 @@ bool cmp_lmul_gt_one (machine_mode);
>  bool gather_scatter_valid_offset_mode_p (machine_mode);
>  bool vls_mode_valid_p (machine_mode);
>  bool vlmax_avl_type_p (rtx_insn *);
> +bool has_vl_op (rtx_insn *);
> +bool tail_agnostic_p (rtx_insn *);
> +void validate_change_or_fail (rtx, rtx *, rtx, bool);
> +bool nonvlmax_avl_type_p (rtx_insn *);
> +bool vlmax_avl_p (rtx);
> +uint8_t get_sew (rtx_insn *);
> +enum vlmul_type get_vlmul (rtx_insn *);
> +int count_regno_occurrences (rtx_insn *, unsigned int);
>  }
>
>  /* We classify builtin types into two classes:
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index d439ec06af0..3fe8125801b 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -4447,4 +4447,87 @@ vlmax_avl_type_p (rtx_insn *rinsn)
>return INTVAL (avl_type) == VLMAX;
>  }
>
> +/* Return true if it is an RVV instruction depends on VL global
> +   status register.  */
> +bool
> +has_vl_op (rtx_insn *rinsn)
> +{
> +  return recog_memoized (rinsn) >= 0 && get_attr_has_vl_op (rinsn);
> +}
> +
> +/* Get default tail policy.  */
> +static bool
> +get_default_ta ()
> +{
> +  /* For the instruction that doesn't require TA, we still need a default 
> value
> + to emit vsetvl. We pick up the default value according to prefer 
> policy. */
> +  return (bool) (get_prefer_tail_policy () & 0x1
> +|| (get_prefer_tail_policy () >> 1 & 0x1));
> +}
> +
> +/* Helper function to get TA operand.  */
> +bool
> +tail_agnostic_p (rtx_insn *rinsn)
> +{
> +  /* If it doesn't have TA, we return agnostic by default.  */
> +  extract_insn_cached (rinsn);
> +  int ta = get_attr_ta (rinsn);
> +  return ta == INVALID_ATTRIBUTE ? get_default_ta () : IS_AGNOSTIC (ta);
> +}
> +
> +/* Change insn and Assert the change always happens.  */
> +void
> +validate_change_or_fail (rtx object, rtx *loc, rtx new_rtx, bool in_group)
> +{
> +  bool change_p = validate_change (object, loc, new_rtx, in_group);
> +  gcc_assert (change_p);
> +}
> +
> +/* Return true if it is NONVLMAX AVL TYPE.  */
> +bool
> +nonvlmax_avl_type_p (rtx_insn *rinsn)
> +{
> +  extract_insn_cached (rinsn);
> +  int index = get_attr_avl_type_idx (rinsn);
> +  if (index == INVALID_ATTRIBUTE)
> +return false;
> +  rtx avl_type = recog_data.operand[index];
> +  return INTVAL (avl_type) == NONVLMAX;
> +}
> +
> +/* Return true if RTX is RVV VLMAX AVL.  */
> +bool
> +vlmax_avl_p (rtx x)
> +{
> +  return x && rtx_equal_p (x, RVV_VLMAX);
> +}
> +
> +/* Helper function to get SEW operand. We always have SEW value for
> +   all RVV instructions that have VTYPE OP.  */
> +uint8_t
> +get_sew (rtx_insn *rinsn)
> +{
> +  return get_attr_sew (rinsn);
> +}
> +
> +/* Helper function to get VLMUL operand. We always have VLMUL value for
> +   all RVV instructions that have VTYPE OP. */
> +enum vlmul_type
> +get_vlmul (rtx_insn *rinsn)
> +{
> +  return (enum vlmul_type) get_attr_vlmul (rinsn);
> +}
> +
> +/* Count the number of REGNO in RINSN.  */
> +int
> +count_regno_occurrences (rtx_insn *rinsn, unsigned int regno)
> +{
> +  int count = 0;
> +  extract_insn (rinsn);
> +  for (int i = 0; i < recog_data.n_opera

Re: [PATCH V2] RISC-V: Add AVL propagation PASS for RVV auto-vectorization

[Kito Cheng]

LGTM, Thanks, it's really awesome - the implementation is simpler than
I expected, it's another great improvement for RISC-V GCC!

Just make sure Patrick gives a green light on the testing before
committing the patch :)




On Wed, Oct 25, 2023 at 8:05 PM Juzhe-Zhong  wrote:
>
> This patch addresses the redundant AVL/VL toggling in RVV partial 
> auto-vectorization
> which is a known issue for a long time and I finally find the time to address 
> it.
>
> Consider a simple vector addition operation:
>
> https://godbolt.org/z/7hfGfEjW3
>
> void
> foo (int *__restrict a,
>  int *__restrict b,
>  int *__restrict n)
> {
>   for (int i = 0; i < n; i++)
>   a[i] = a[i] + b[i];
> }
>
> Optimized IR:
>
> Loop body:
>   _38 = .SELECT_VL (ivtmp_36, POLY_INT_CST [4, 4]);  
> -> vsetvli a5,a2,e8,mf4,ta,ma
>   ...
>   vect__4.8_27 = .MASK_LEN_LOAD (vectp_a.6_29, 32B, { -1, ... }, _38, 0);
> -> vle32.v v2,0(a0)
>   vect__6.11_20 = .MASK_LEN_LOAD (vectp_b.9_25, 32B, { -1, ... }, _38, 0);   
> -> vle32.v v1,0(a1)
>   vect__7.12_19 = vect__6.11_20 + vect__4.8_27;  
> -> vsetvli a6,zero,e32,m1,ta,ma + vadd.vv v1,v1,v2
>   .MASK_LEN_STORE (vectp_a.13_11, 32B, { -1, ... }, _38, 0, vect__7.12_19);  
> -> vsetvli zero,a5,e32,m1,ta,ma + vse32.v v1,0(a4)
>
> We can see 2 redundant vsetvls inside the loop body due to AVL/VL toggling.
> The AVL/VL toggling is because we are missing LEN information in simple 
> PLUS_EXPR GIMPLE assignment:
>
> vect__7.12_19 = vect__6.11_20 + vect__4.8_27;
>
> GCC apply partial predicate load/store and un-predicated full vector 
> operation on partial vectorization.
> Such flow are used by all other targets like ARM SVE (RVV also uses such 
> flow):
>
> ARM SVE:
>
> .L3:
> ld1wz30.s, p7/z, [x0, x3, lsl 2]   -> predicated load
> ld1wz31.s, p7/z, [x1, x3, lsl 2]   -> predicated load
> add z31.s, z31.s, z30.s-> un-predicated add
> st1wz31.s, p7, [x0, x3, lsl 2] -> predicated store
>
> Such vectorization flow causes AVL/VL toggling on RVV so we need AVL 
> propagation PASS for it.
>
> Also, It's very unlikely that we can apply predicated operations on all 
> vectorization for following reasons:
>
> 1. It's very heavy workload to support them on all vectorization and we don't 
> see any benefits if we can handle that on targets backend.
> 2. Changing Loop vectorizer for it will make code base ugly and hard to 
> maintain.
> 3. We will need so many patterns for all operations. Not only COND_LEN_ADD, 
> COND_LEN_SUB, 
>We also need COND_LEN_EXTEND, , COND_LEN_CEIL, ... .. over 100+ 
> patterns, unreasonable number of patterns.
>
> To conclude, we prefer un-predicated operations here, and design a nice and 
> clean AVL propagation PASS for it to elide the redundant vsetvls
> due to AVL/VL toggling.
>
> The second question is that why we separate a PASS called AVL propagation. 
> Why not optimize it in VSETVL PASS (We definitetly can optimize AVL in VSETVL 
> PASS)
>
> Frankly, I was planning to address such issue in VSETVL PASS that's why we 
> recently refactored VSETVL PASS. However, I changed my mind recently after 
> several
> experiments and tries.
>
> The reasons as follows:
>
> 1. For code base management and maintainience. Current VSETVL PASS is 
> complicated enough and aleady has enough aggressive and fancy optimizations 
> which
>turns out it can always generate optimal codegen in most of the cases. 
> It's not a good idea keep adding more features into VSETVL PASS to make VSETVL
>  PASS become heavy and heavy again, then we will need to refactor it 
> again in the future.
>  Actuall, the VSETVL PASS is very stable and optimal after the recent 
> refactoring. Hopefully, we should not change VSETVL PASS any more except the 
> minor
>  fixes.
>
> 2. vsetvl insertion (VSETVL PASS does this thing) and AVL propagation are 2 
> different things,  I don't think we should fuse them into same PASS.
>
> 3. VSETVL PASS is an post-RA PASS, wheras AVL propagtion should be done 
> before RA which can reduce register allocation.
>
> 4. This patch's AVL propagation PASS only does AVL propagation for RVV 
> partial auto-vectorization situations.
>This patch's codes are only hundreds lines which is very managable and can 
> be very easily extended features and enhancements.
>  We can easily extend and enhance more AVL propagation in a clean and 
> separate PASS in the future. (If we do it on VSETVL PASS, we will complicate
>  VSETVL PASS again which is already so complicated.)
>
> Here is an example to demonstrate more:
>
> https://godbolt.org/z/bE86sv3q5
>
> void foo2 (int *__restrict a,
>   int *__restrict b,
>   int *__restrict c,
>   int *__restrict a2,
>   int *__restrict b2,
>   int *__restrict c2,
>   int *__restrict a3,
>   int *__restrict b3,
>   int *__re

Re: Re: [PATCH] RISC-V: Add rawmemchr expander.

[Kito Cheng]

Could you put it into riscv-string.cc rather than riscv-v.cc? I would
like to put those builtin function expander together if possible,
riscv-string.cc might little bit confuse, but it's all included in
string.h

On Fri, Oct 27, 2023 at 3:40 PM juzhe.zh...@rivai.ai
 wrote:
>
> LGTM. Thanks.
>
> 
> juzhe.zh...@rivai.ai
>
>
> From: Robin Dapp
> Date: 2023-10-27 15:38
> To: 钟居哲; gcc-patches; palmer; kito.cheng; Jeff Law
> CC: rdapp.gcc
> Subject: Re: [PATCH] RISC-V: Add rawmemchr expander.
> > Suggested adapt codes as follows:
> >
> > unsigned int element_size = GET_MODE_SIZE (mode).to_constant ();
> > poly_int64 nunits = exact_div (BYTES_PER_RISCV_VECTOR *TARGET_MAX_LMUL, 
> > element_size);
> > if (!get_vector_mode(mode, nunits).exists(&vmode))
> >   gcc_unreachable ();
>
> Actually I was initially considering using lmul = m8 here,
> unconditionally, but the param is probably the more intuitive choice.
>
> Attached v2 with that included.  Also moved the riscv test to
> autovec/builtin/ so we can add the other builtins as well.
>
> > Also, this patch reminds me we are missing some more similiar builtin
> > function which can use RVV:
> >
> > strlen, strcpy, strcmp...etc
>
> Yes we should still have them but I'd rather not work on that right
> now.  How about I open a PR for it so we can still add them in stage 3?
> Their impact is pretty localized and the risk should be low.
> Kito, Palmer, Jeff - would that be acceptable?
>
> Regards
> Robin
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md (rawmemchr): New expander.
> * config/riscv/riscv-protos.h (enum insn_type): Define.
> (expand_rawmemchr): New function.
> * config/riscv/riscv-v.cc (expand_rawmemchr): Add vectorized
> rawmemchr.
> * internal-fn.cc (expand_RAWMEMCHR): Fix typo.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.dg/tree-ssa/ldist-rawmemchr-1.c: Add riscv.
> * gcc.dg/tree-ssa/ldist-rawmemchr-2.c: Ditto.
> * gcc.target/riscv/rvv/rvv.exp: Add builtin directory.
> * gcc.target/riscv/rvv/autovec/builtin/rawmemchr-1.c: New test.
> ---
> gcc/config/riscv/autovec.md   | 13 +++
> gcc/config/riscv/riscv-protos.h   |  1 +
> gcc/config/riscv/riscv-v.cc   | 89 +
> gcc/internal-fn.cc|  2 +-
> .../gcc.dg/tree-ssa/ldist-rawmemchr-1.c   |  8 +-
> .../gcc.dg/tree-ssa/ldist-rawmemchr-2.c   |  8 +-
> .../riscv/rvv/autovec/builtin/rawmemchr-1.c   | 99 +++
> gcc/testsuite/gcc.target/riscv/rvv/rvv.exp|  2 +
> 8 files changed, 213 insertions(+), 9 deletions(-)
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/builtin/rawmemchr-1.c
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index 1ddc1993120..4f13494afdb 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -2397,3 +2397,16 @@ (define_expand "lfloor2"
>  DONE;
>}
> )
> +
> +;; Implement rawmemchr[qi|si|hi].
> +(define_expand "rawmemchr"
> +  [(match_operand  0 "register_operand")
> +   (match_operand  1 "memory_operand")
> +   (match_operand:ANYI 2 "const_int_operand")]
> +  "TARGET_VECTOR"
> +  {
> +riscv_vector::expand_rawmemchr(mode, operands[0], operands[1],
> +operands[2]);
> +DONE;
> +  }
> +)
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index 843a81b0e86..7f148ed95fe 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -526,6 +526,7 @@ void expand_cond_unop (unsigned, rtx *);
> void expand_cond_binop (unsigned, rtx *);
> void expand_cond_ternop (unsigned, rtx *);
> void expand_popcount (rtx *);
> +void expand_rawmemchr (machine_mode, rtx, rtx, rtx);
> /* Rounding mode bitfield for fixed point VXRM.  */
> enum fixed_point_rounding_mode
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 3fe8125801b..0f664553cf4 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -2215,6 +2215,95 @@ expand_block_move (rtx dst_in, rtx src_in, rtx 
> length_in)
>return true;
> }
> +/* Implement rawmemchr using vector instructions.
> +   It can be assumed that the needle is in the haystack, otherwise the
> +   behavior is undefined.  */
> +
> +void
> +expand_rawmemchr (machine_mode mode, rtx dst, rtx src, rtx pat)
> +{
> +  /*
> +rawmemchr:
> +loop:
> +   vsetvli a1, zero, e[8,16,32,64], m1, ta, ma
> +   vle[8,16,32,64]ff.v v8, (a0)  # Load.
> +   csrr a1, vl  # Get number of bytes read.
> +   vmseq.vx v0, v8, pat  # v0 = (v8 == {pat, pat, ...})
> +   vfirst.m a2, v0  # Find first hit.
> +   add a0, a0, a1  # Bump pointer.
> +   bltz a2, loop  # Not found?
> +
> +   sub a0, a0, a1  # Go back by a1.
> +   shll a2, a2, [0,1,2,3]  # Shift to get byte offset.
> +   add a0, a0, a2  # Add the offset.
> +
> +   ret
> +  */
> +  gcc_assert (TARGET_VECTOR);
> +
> +  unsigned

Re: [PATCH 1/4] RISC-V: Recategorize "prefetch" availabilities

[Kito Cheng]

> Unless Kito feels otherwise I would suggest keeping a distinct API
> interface for each case.

Yeah, I think they should have a distinct API.

Re: [RFC] RISC-V: Support -mcmodel=large.

[Kito Cheng]

> Overall it looks pretty good.   Does Andestech have a copyright
> assignment in place?  Or are you contributing under the DCO rule?

Kuan-Lin Chen is Andestech folk, and Andestech have signed copyright
assignment for most GNU toolchain components I believe :)

> https://gcc.gnu.org/dco.html
>
> JeJeff

Re: [PATCH] RISC-V: Early expand DImode vec_duplicate in RV32 system

[Kito Cheng]

Could you add a testcase? other than that LGTM.

On Mon, Nov 6, 2023 at 8:27 PM Juzhe-Zhong  wrote:
>
> An ICE was discovered in recent rounding autovec support:
>
> config/riscv/riscv-v.cc:4314
>65 | }
>   | ^
> 0x1fa5223 riscv_vector::validate_change_or_fail(rtx_def*, rtx_def**,
> rtx_def*, bool)
> 
> /home/pli/repos/gcc/222/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/config/riscv/riscv-v.cc:4314
> 0x1fb1aa2 pre_vsetvl::remove_avl_operand()
> 
> /home/pli/repos/gcc/222/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/config/riscv/riscv-vsetvl.cc:3342
> 0x1fb18c1 pre_vsetvl::cleaup()
> 
> /home/pli/repos/gcc/222/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/config/riscv/riscv-vsetvl.cc:3308
> 0x1fb216d pass_vsetvl::lazy_vsetvl()
> 
> /home/pli/repos/gcc/222/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/config/riscv/riscv-vsetvl.cc:3480
> 0x1fb2214 pass_vsetvl::execute(function*)
> 
> /home/pli/repos/gcc/222/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/config/riscv/riscv-vsetvl.cc:3504
>
> The root cause is that the RA reload into (set (reg) vec_duplicate:DI). 
> However, it is not valid in RV32 system
> since we don't have a single broadcast instruction DI scalar in RV32 system.
> We should expand it early for RV32 system.
>
> gcc/ChangeLog:
>
> * config/riscv/predicates.md: Refine predicate.
> * config/riscv/riscv-protos.h (can_be_broadcasted_p): New function.
> * config/riscv/riscv-v.cc (can_be_broadcasted_p): Ditto.
> * config/riscv/vector.md (vec_duplicate): New pattern.
> (*vec_duplicate): Adapt pattern.
>
> ---
>  gcc/config/riscv/predicates.md  |  9 +
>  gcc/config/riscv/riscv-protos.h |  1 +
>  gcc/config/riscv/riscv-v.cc | 20 
>  gcc/config/riscv/vector.md  | 20 +++-
>  4 files changed, 41 insertions(+), 9 deletions(-)
>
> diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
> index db18054607f..df1c66f3a76 100644
> --- a/gcc/config/riscv/predicates.md
> +++ b/gcc/config/riscv/predicates.md
> @@ -553,14 +553,7 @@
>
>  ;; The scalar operand can be directly broadcast by RVV instructions.
>  (define_predicate "direct_broadcast_operand"
> -  (and (match_test "!(reload_completed && !FLOAT_MODE_P (GET_MODE (op))
> -   && (register_operand (op, GET_MODE (op)) || CONST_INT_P (op)
> -   || rtx_equal_p (op, CONST0_RTX (GET_MODE (op
> -   && maybe_gt (GET_MODE_BITSIZE (GET_MODE (op)), 
> GET_MODE_BITSIZE (Pmode)))")
> -(ior (match_test "rtx_equal_p (op, CONST0_RTX (GET_MODE (op)))")
> - (ior (match_code "const_int,const_poly_int")
> -  (ior (match_operand 0 "register_operand")
> -   (match_test "satisfies_constraint_Wdm (op)"))
> +  (match_test "riscv_vector::can_be_broadcasted_p (op)"))
>
>  ;; A CONST_INT operand that has exactly two bits cleared.
>  (define_predicate "const_nottwobits_operand"
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index 6cbf2130f88..acae00f653f 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -595,6 +595,7 @@ uint8_t get_sew (rtx_insn *);
>  enum vlmul_type get_vlmul (rtx_insn *);
>  int count_regno_occurrences (rtx_insn *, unsigned int);
>  bool imm_avl_p (machine_mode);
> +bool can_be_broadcasted_p (rtx);
>  }
>
>  /* We classify builtin types into two classes:
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 80d2bb9e289..a64946213c3 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -4417,4 +4417,24 @@ count_regno_occurrences (rtx_insn *rinsn, unsigned int 
> regno)
>return count;
>  }
>
> +/* Return true if the OP can be directly broadcasted.  */
> +bool
> +can_be_broadcasted_p (rtx op)
> +{
> +  machine_mode mode = GET_MODE (op);
> +  /* We don't allow RA (register allocation) reload generate
> +(vec_duplicate:DI reg) in RV32 system wheras we allow
> +(vec_duplicate:DI mem) in RV32 system.  */
> +  if (!can_create_pseudo_p () && !FLOAT_MODE_P (mode)
> +  && maybe_gt (GET_MODE_SIZE (mode), GET_MODE_SIZE (Pmode))
> +  && !satisfies_constraint_Wdm (op))
> +return false;
> +
> +  if (satisfies_constraint_K (op) || register_operand (op, mode)
> +  || satisfies_constraint_Wdm (op) || rtx_equal_p (op, CONST0_RTX 
> (mode)))
> +return true;
> +
> +  return can_create_pseudo_p () && nonmemory_operand (op, mode);
> +}
> +
>  } // namespace riscv_vector
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index 8509c4fe5f2..e23f64938b7 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -1370,11 +1370,29 @@
>  ;;  Duplicate Operations
>  ;; -
>
> +(define_expand "vec_duplicate"
> +  [(set (match_operand:V_VLS 0 "register_operand")
> +(vec_duplic

Re: Re: [PATCH] RISC-V: Early expand DImode vec_duplicate in RV32 system

[Kito Cheng]

I would prefer to add a dedicated test case to test that, so that we
could also cover that even if we didn't enable multi-lib testing for
RV32, and I suppose that should only require compile test for part of
that test case ?

On Mon, Nov 6, 2023 at 8:41 PM juzhe.zh...@rivai.ai
 wrote:
>
> Testcase already existed on the trunk, which is added by Li Pan added 
> recently when supporting rounding mode autovec.
>
> https://gcc.gnu.org/pipermail/gcc-patches/2023-November/635280.html
>
> math-llrintf-run-0.c passed on RV64 but cause ICE on RV32.
>
>
>
> ____
> juzhe.zh...@rivai.ai
>
>
> From: Kito Cheng
> Date: 2023-11-06 20:38
> To: Juzhe-Zhong
> CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
> Subject: Re: [PATCH] RISC-V: Early expand DImode vec_duplicate in RV32 system
> Could you add a testcase? other than that LGTM.
>
> On Mon, Nov 6, 2023 at 8:27 PM Juzhe-Zhong  wrote:
> >
> > An ICE was discovered in recent rounding autovec support:
> >
> > config/riscv/riscv-v.cc:4314
> >65 | }
> >   | ^
> > 0x1fa5223 riscv_vector::validate_change_or_fail(rtx_def*, rtx_def**,
> > rtx_def*, bool)
> > 
> > /home/pli/repos/gcc/222/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/config/riscv/riscv-v.cc:4314
> > 0x1fb1aa2 pre_vsetvl::remove_avl_operand()
> > 
> > /home/pli/repos/gcc/222/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/config/riscv/riscv-vsetvl.cc:3342
> > 0x1fb18c1 pre_vsetvl::cleaup()
> > 
> > /home/pli/repos/gcc/222/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/config/riscv/riscv-vsetvl.cc:3308
> > 0x1fb216d pass_vsetvl::lazy_vsetvl()
> > 
> > /home/pli/repos/gcc/222/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/config/riscv/riscv-vsetvl.cc:3480
> > 0x1fb2214 pass_vsetvl::execute(function*)
> > 
> > /home/pli/repos/gcc/222/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/config/riscv/riscv-vsetvl.cc:3504
> >
> > The root cause is that the RA reload into (set (reg) vec_duplicate:DI). 
> > However, it is not valid in RV32 system
> > since we don't have a single broadcast instruction DI scalar in RV32 system.
> > We should expand it early for RV32 system.
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/predicates.md: Refine predicate.
> > * config/riscv/riscv-protos.h (can_be_broadcasted_p): New function.
> > * config/riscv/riscv-v.cc (can_be_broadcasted_p): Ditto.
> > * config/riscv/vector.md (vec_duplicate): New pattern.
> > (*vec_duplicate): Adapt pattern.
> >
> > ---
> >  gcc/config/riscv/predicates.md  |  9 +
> >  gcc/config/riscv/riscv-protos.h |  1 +
> >  gcc/config/riscv/riscv-v.cc | 20 
> >  gcc/config/riscv/vector.md  | 20 +++-
> >  4 files changed, 41 insertions(+), 9 deletions(-)
> >
> > diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
> > index db18054607f..df1c66f3a76 100644
> > --- a/gcc/config/riscv/predicates.md
> > +++ b/gcc/config/riscv/predicates.md
> > @@ -553,14 +553,7 @@
> >
> >  ;; The scalar operand can be directly broadcast by RVV instructions.
> >  (define_predicate "direct_broadcast_operand"
> > -  (and (match_test "!(reload_completed && !FLOAT_MODE_P (GET_MODE (op))
> > -   && (register_operand (op, GET_MODE (op)) || CONST_INT_P (op)
> > -   || rtx_equal_p (op, CONST0_RTX (GET_MODE (op
> > -   && maybe_gt (GET_MODE_BITSIZE (GET_MODE (op)), 
> > GET_MODE_BITSIZE (Pmode)))")
> > -(ior (match_test "rtx_equal_p (op, CONST0_RTX (GET_MODE (op)))")
> > - (ior (match_code "const_int,const_poly_int")
> > -  (ior (match_operand 0 "register_operand")
> > -   (match_test "satisfies_constraint_Wdm (op)"))
> > +  (match_test "riscv_vector::can_be_broadcasted_p (op)"))
> >
> >  ;; A CONST_INT operand that has exactly two bits cleared.
> >  (define_predicate "const_nottwobits_operand"
> > diff --git a/gcc/config/riscv/riscv-protos.h 
> > b/gcc/config/riscv/riscv-protos.h
> > index 6cbf2130f88..acae00f653f 100644
> > --- a/gcc/config/riscv/riscv-protos.h
> > +++ b/gcc/config/riscv/riscv-protos.h
> > @@ -595,6 +595,7 @@ uint8_t get_sew (rtx_insn *);
> >  enum vlmul_type get_vlmul (rtx_insn *);
> >  int count_regno_occurrences (rtx_insn *, unsigned int);
> >  bool imm_avl_p (machine_mode);
> > +bool can_be_b

Re: [PATCH] RISC-V: VECT: Remember to assert any_known_not_updated_vssa

[Kito Cheng]

> Oh, you're right! I should have checked the master branch first... and
> I was even wondering why it wasn't marked as such. Should perhaps
> cherry pick this for gcc-13-with-riscv-opts?

 gcc-13-with-riscv-opts mostly maintained by Ventana folks, so maybe
ask Jeff if you want to cherry pick into that branch?

Re: [PATCH] RISC-V: Fix -march option parsing when `p` extension exists.

[Kito Cheng]

Hi Jim:

I think this patch is small enough to accept without FSF copyright
assignment, and he is also on the way of the process, what do you
think?

On Fri, Jan 22, 2021 at 2:44 PM Xing GUO  wrote:
>
> Hi Kito,
>
> I’ve sent my assignments and my school’s disclaimer to ass...@gnu.org 
> ([gnu.org #1673033] Xing GUO), but I haven’t got response so far. Not sure if 
> this patch can be accepted as  a small bugfix patch. If not, I’m happy to 
> wait until FSF prove it.
>
> Best Regards,
> Xing
>
> On Jan 22, 2021, at 2:26 PM, Kito Cheng  wrote:
>
> Hi Xing:
>
> Thanks for your patch, but I would like to know did you have the
> copyright assignment for FSF? or your employee/company has signed
> that?
>
> On Thu, Jan 21, 2021 at 8:48 PM Xing GUO via Gcc-patches
>  wrote:
>
>
> This patch fixes -march option parsing when `p` extension exists,
> e.g., -march=rv64imafdcp should produce
>
> .attribute arch, "rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_p"
>
> rather than
>
> .attribute arch, "rv64i2p0_m2p0_a2p0_f2p0_d2p0_c_p"
>
> ---
> gcc/ChangeLog:
>
>* common/config/riscv/riscv-common.c
> (riscv_subset_list::parsing_subset_version):
>Fix -march option parsing when `p` extension exists.
>
> gcc/testsuite/ChangeLog:
>
>* gcc.target/riscv/attribute-18.c: New test.
> --
>
> Cheers,
> Xing
>
>

[PATCH] PR target/98743: Fix ICE in convert_move for RISC-V

[Kito Cheng]

 - Check `TO` mode is not BLMmode before call store_expr, calling store_expr
   with BLKmode will cause ICE.

 - Verified with riscv64, x86_64 and aarch64, no introduce new regression.

Note: Those logic was introduced by 3e60ddeb8220ed388819bb3f14e8caa9309fd3c2,
  so I cc Jakub for reivew.

gcc/ChangeLog:

PR target/98743
* expr.c: Check mode before calling store_expr.

gcc/testsuite/ChangeLog:

PR target/98743
* g++.target/riscv/pr98743.C: New.
---
 gcc/expr.c   |  1 +
 gcc/testsuite/g++.target/riscv/pr98743.C | 27 
 2 files changed, 28 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/pr98743.C

diff --git a/gcc/expr.c b/gcc/expr.c
index 04ef5ad114d..3cf492acea3 100644
--- a/gcc/expr.c
+++ b/gcc/expr.c
@@ -5459,6 +5459,7 @@ expand_assignment (tree to, tree from, bool nontemporal)
  /* If to_rtx is a promoted subreg, we need to zero or sign
 extend the value afterwards.  */
  if (TREE_CODE (to) == MEM_REF
+ && mode != BLKmode
  && !REF_REVERSE_STORAGE_ORDER (to)
  && known_eq (bitpos, 0)
  && known_eq (bitsize, GET_MODE_BITSIZE (GET_MODE (to_rtx
diff --git a/gcc/testsuite/g++.target/riscv/pr98743.C 
b/gcc/testsuite/g++.target/riscv/pr98743.C
new file mode 100644
index 000..1b94597ac68
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/pr98743.C
@@ -0,0 +1,27 @@
+// Test for value-initialization via {}
+// { dg-do run { target c++11 } }
+/* { dg-options "-Og -version -fno-early-inlining -finline-small-functions 
-fpack-struct" */
+void * operator new (__SIZE_TYPE__, void *p) { return p; }
+void * operator new[] (__SIZE_TYPE__, void *p) { return p; }
+
+// Empty base so A isn't an aggregate
+struct B {};
+struct A: B {
+  int i;
+};
+
+struct C: A {
+  C(): A{} {}
+};
+
+int main()
+{
+  int space = 42;
+  A* ap = new (&space) A{};
+  int space1[1] = { 42 };
+  A* a1p = new (space1) A[1]{};
+  if (ap->i != 0 ||
+  a1p[0].i != 0)
+return 1;
+  return 0;
+}
-- 
2.30.0

Re: [PATCH] PR target/98743: Fix ICE in convert_move for RISC-V

[Kito Cheng]

> >  - Check `TO` mode is not BLMmode before call store_expr, calling store_expr
> >with BLKmode will cause ICE.
>
> How do you end up with a SUBREG_PROMOTED* of something that has bitsize of 0
> (GET_MODE_BITSIZE of BLKmode is 0, right)?

to_rtx is already having a mode other than BLKmode in this point,
it's SImode for riscv64*-*-*, so bitsize is 32 rather than 0.

I guess my comment isn't clear enough, the root cause why
`store_expr (from, to_rtx, 0, nontemporal, false)` ICE is
because `from` is still BLKmode here.

> That makes no sense.
>
> Jakub
>

[PATCH v2] PR target/98743: Fix ICE in convert_move for RISC-V

[Kito Cheng]

 - Check `from` mode is not BLMmode before call store_expr, calling store_expr
   with BLKmode will cause ICE.

 - Verified with riscv64, x86_64 and aarch64, no introduce new regression.

Note: Those logic was introduced by 3e60ddeb8220ed388819bb3f14e8caa9309fd3c2,
  so I cc Jakub for reivew.

Changes for V2:

 - Checking mode of `from` rather than mode of `to`.
 - Verified on riscv64, x86_64 and aarch64 again.

gcc/ChangeLog:

PR target/98743
* expr.c: Check mode before calling store_expr.

gcc/testsuite/ChangeLog:

PR target/98743
* g++.target/riscv/pr98743.C: New.
---
 gcc/expr.c   |  1 +
 gcc/testsuite/g++.target/riscv/pr98743.C | 27 
 2 files changed, 28 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/pr98743.C

diff --git a/gcc/expr.c b/gcc/expr.c
index 04ef5ad114d..86dc1b6c973 100644
--- a/gcc/expr.c
+++ b/gcc/expr.c
@@ -5459,6 +5459,7 @@ expand_assignment (tree to, tree from, bool nontemporal)
  /* If to_rtx is a promoted subreg, we need to zero or sign
 extend the value afterwards.  */
  if (TREE_CODE (to) == MEM_REF
+ && TYPE_MODE (TREE_TYPE (from)) != BLKmode
  && !REF_REVERSE_STORAGE_ORDER (to)
  && known_eq (bitpos, 0)
  && known_eq (bitsize, GET_MODE_BITSIZE (GET_MODE (to_rtx
diff --git a/gcc/testsuite/g++.target/riscv/pr98743.C 
b/gcc/testsuite/g++.target/riscv/pr98743.C
new file mode 100644
index 000..41f476fbe8e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/pr98743.C
@@ -0,0 +1,27 @@
+// Test for value-initialization via {}
+// { dg-do run { target c++11 } }
+/* { dg-options "-Og -fno-early-inlining -finline-small-functions 
-fpack-struct" */
+void * operator new (__SIZE_TYPE__, void *p) { return p; }
+void * operator new[] (__SIZE_TYPE__, void *p) { return p; }
+
+// Empty base so A isn't an aggregate
+struct B {};
+struct A: B {
+  int i;
+};
+
+struct C: A {
+  C(): A{} {}
+};
+
+int main()
+{
+  int space = 42;
+  A* ap = new (&space) A{};
+  int space1[1] = { 42 };
+  A* a1p = new (space1) A[1]{};
+  if (ap->i != 0 ||
+  a1p[0].i != 0)
+return 1;
+  return 0;
+}
-- 
2.30.0

Re: [PATCH v2] PR target/98743: Fix ICE in convert_move for RISC-V

[Kito Cheng]

Hi Jakub:

Thanks for your review, committed with testcase movement.

On Tue, Feb 2, 2021 at 4:41 PM Jakub Jelinek  wrote:
>
> On Tue, Feb 02, 2021 at 03:21:24PM +0800, Kito Cheng wrote:
> >  - Check `from` mode is not BLMmode before call store_expr, calling 
> > store_expr
> >with BLKmode will cause ICE.
> >
> >  - Verified with riscv64, x86_64 and aarch64, no introduce new regression.
> >
> > Note: Those logic was introduced by 
> > 3e60ddeb8220ed388819bb3f14e8caa9309fd3c2,
> >   so I cc Jakub for reivew.
> >
> > Changes for V2:
> >
> >  - Checking mode of `from` rather than mode of `to`.
> >  - Verified on riscv64, x86_64 and aarch64 again.
> >
> > gcc/ChangeLog:
> >
> >   PR target/98743
> >   * expr.c: Check mode before calling store_expr.
>
> Ok, with a small nit.
> >
> > gcc/testsuite/ChangeLog:
> >
> >   PR target/98743
> >   * g++.target/riscv/pr98743.C: New.
>
> There is nothing riscv specific on the testcase, so it should go into
> g++.dg/opt/ instead.
>
> Jakub
>

[PATCH] PR target/98878 - Incorrect multilib list for riscv*-rtems

[Kito Cheng]

 - Multi-lib only check the default argument is appeared in the multilib
   flag list, but we didn't check the case that the flag is required but
   default argument didn't provide.

 - For example riscv*-rtems has a multilib set:

 rv32imafd/ilp32d;@march=rv32imafd@mabi=ilp32d

   And when we set the default argument of arch to rv32imafdc and ABI to
   ilp32d, gcc will check the ilp32d is matched, but it didn't check
   rv32imafd is not provided by default arguments, so it should not
   reuse default library.

 - The side effcet of this patch is csky-elf target will increase the
   number of multilib from 54 to 59, but it's because genmultilib didn't
   know the default argument for multilib, so I think it could be
   improved in future.

gcc/ChangeLog:

* gcc.c (print_multilib_info): Check all required argument is provided
by default arg.
---
 gcc/gcc.c | 23 +++
 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git a/gcc/gcc.c b/gcc/gcc.c
index aa5774af7e7..645f2a04d5a 100644
--- a/gcc/gcc.c
+++ b/gcc/gcc.c
@@ -9909,12 +9909,14 @@ print_multilib_info (void)
  last_path_len = p - this_path;
}
 
-  /* If this directory requires any default arguments, we can skip
+  /* If this directory requires any default arguments, and any default
+arguments not appear in the ! argument list, then we can skip
 it.  We will already have printed a directory identical to
 this one which does not require that default argument.  */
   if (! skip)
{
  const char *q;
+ bool default_arg_ok = false;
 
  q = p + 1;
  while (*q != ';')
@@ -9946,16 +9948,29 @@ print_multilib_info (void)
 list.  */
  if (not_arg)
{
- skip = 0;
+ default_arg_ok = false;
  break;
}
- else
-   skip = 1;
+
+ default_arg_ok = true;
+   }
+ else if (!not_arg)
+   {
+ /* Stop checking if any required argument is not provided by
+default arguments.  */
+ default_arg_ok = false;
+ break;
}
 
  if (*q == ' ')
++q;
}
+
+ /* Make sure all default argument is OK for this multi-lib set.  */
+ if (default_arg_ok)
+   skip = 1;
+ else
+   skip = 0;
}
 
   if (! skip)
-- 
2.30.0

[PATCH] config.sub, config.guess : Import upstream 2021-01-25.

[Kito Cheng]

Hi

Does it update config.sub and config.guess, I know it's already
stage 4, but the config.* stuff update should be harmless things,
and we need this for RISC-V big-endian support, which is already
supported in binutils 2.36.

This imports from:

sha1 6faca61810d335c7837f320733fe8e15a1431fc2

ChangeLog:

* config.guess: Import latest upstream.
* config.sub: Import latest upstream.
---
 config.guess | 48 +++-
 config.sub   | 23 +++
 2 files changed, 46 insertions(+), 25 deletions(-)

diff --git a/config.guess b/config.guess
index 0fc11edb2d1..1972fda8eb0 100755
--- a/config.guess
+++ b/config.guess
@@ -1,8 +1,8 @@
 #! /bin/sh
 # Attempt to guess a canonical system name.
-#   Copyright 1992-2020 Free Software Foundation, Inc.
+#   Copyright 1992-2021 Free Software Foundation, Inc.
 
-timestamp='2020-11-07'
+timestamp='2021-01-25'
 
 # This file is free software; you can redistribute it and/or modify it
 # under the terms of the GNU General Public License as published by
@@ -27,7 +27,7 @@ timestamp='2020-11-07'
 # Originally written by Per Bothner; maintained since 2000 by Ben Elliston.
 #
 # You can get the latest version of this script from:
-# https://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.guess
+# https://git.savannah.gnu.org/cgit/config.git/plain/config.guess
 #
 # Please send patches to .
 
@@ -50,7 +50,7 @@ version="\
 GNU config.guess ($timestamp)
 
 Originally written by Per Bothner.
-Copyright 1992-2020 Free Software Foundation, Inc.
+Copyright 1992-2021 Free Software Foundation, Inc.
 
 This is free software; see the source for copying conditions.  There is NO
 warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE."
@@ -138,9 +138,7 @@ UNAME_VERSION=$( (uname -v) 2>/dev/null) || 
UNAME_VERSION=unknown
 
 case "$UNAME_SYSTEM" in
 Linux|GNU|GNU/*)
-   # If the system lacks a compiler, then just pick glibc.
-   # We could probably try harder.
-   LIBC=gnu
+   LIBC=unknown
 
set_cc_for_build
cat <<-EOF > "$dummy.c"
@@ -149,16 +147,30 @@ Linux|GNU|GNU/*)
LIBC=uclibc
#elif defined(__dietlibc__)
LIBC=dietlibc
+   #elif defined(__GLIBC__)
+   LIBC=gnu
#else
#include 
+   /* First heuristic to detect musl libc.  */
#ifdef __DEFINED_va_list
LIBC=musl
-   #else
-   LIBC=gnu
#endif
#endif
EOF
eval "$($CC_FOR_BUILD -E "$dummy.c" 2>/dev/null | grep '^LIBC' | sed 
's, ,,g')"
+
+   # Second heuristic to detect musl libc.
+   if [ "$LIBC" = unknown ] &&
+  command -v ldd >/dev/null &&
+  ldd --version 2>&1 | grep -q ^musl; then
+   LIBC=musl
+   fi
+
+   # If the system lacks a compiler, then just pick glibc.
+   # We could probably try harder.
+   if [ "$LIBC" = unknown ]; then
+   LIBC=gnu
+   fi
;;
 esac
 
@@ -176,10 +188,9 @@ case 
"$UNAME_MACHINE:$UNAME_SYSTEM:$UNAME_RELEASE:$UNAME_VERSION" in
#
# Note: NetBSD doesn't particularly care about the vendor
# portion of the name.  We always set it to "unknown".
-   sysctl="sysctl -n hw.machine_arch"
UNAME_MACHINE_ARCH=$( (uname -p 2>/dev/null || \
-   "/sbin/$sysctl" 2>/dev/null || \
-   "/usr/sbin/$sysctl" 2>/dev/null || \
+   /sbin/sysctl -n hw.machine_arch 2>/dev/null || \
+   /usr/sbin/sysctl -n hw.machine_arch 2>/dev/null || \
echo unknown))
case "$UNAME_MACHINE_ARCH" in
aarch64eb) machine=aarch64_be-unknown ;;
@@ -984,6 +995,9 @@ EOF
 k1om:Linux:*:*)
echo "$UNAME_MACHINE"-unknown-linux-"$LIBC"
exit ;;
+loongarch32:Linux:*:* | loongarch64:Linux:*:* | loongarchx32:Linux:*:*)
+   echo "$UNAME_MACHINE"-unknown-linux-"$LIBC"
+   exit ;;
 m32r*:Linux:*:*)
echo "$UNAME_MACHINE"-unknown-linux-"$LIBC"
exit ;;
@@ -1072,7 +1086,7 @@ EOF
 ppcle:Linux:*:*)
echo powerpcle-unknown-linux-"$LIBC"
exit ;;
-riscv32:Linux:*:* | riscv64:Linux:*:*)
+riscv32:Linux:*:* | riscv32be:Linux:*:* | riscv64:Linux:*:* | 
riscv64be:Linux:*:*)
echo "$UNAME_MACHINE"-unknown-linux-"$LIBC"
exit ;;
 s390:Linux:*:* | s390x:Linux:*:*)
@@ -1468,8 +1482,8 @@ EOF
 i*86:rdos:*:*)
echo "$UNAME_MACHINE"-pc-rdos
exit ;;
-i*86:AROS:*:*)
-   echo "$UNAME_MACHINE"-pc-aros
+*:AROS:*:*)
+   echo "$UNAME_MACHINE"-unknown-aros
exit ;;
 x86_64:VMkernel:*:*)
echo "$UNAME_MACHINE"-unknown-esx
@@ -1638,9 +1652,9 @@ This script (version $timestamp), has failed to recognize 
the
 operating system you are using. If your script is old, overwrite *all*
 copies of config.guess and config.sub with the latest versions from:
 
-  https://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.guess
+  https://git.savannah

[PATCH] PR target/99314: Fix integer signedness issue for cpymem pattern expansion.

[Kito Cheng]

From: Sinan Lin 

Third operand of cpymem pattern is unsigned HOST_WIDE_INT, however we
are interpret that as signed HOST_WIDE_INT, that not a problem in
most case, but when the value is large than signed HOST_WIDE_INT, it
might screw up since we have using that value to calculate the buffer
size.

2021-03-05  Sinan Lin  
Kito Cheng  

gcc/ChangeLog:

* config/riscv/riscv.c (riscv_block_move_straight): Change type
to unsigned HOST_WIDE_INT for parameter and local variable with
HOST_WIDE_INT type.
(riscv_adjust_block_mem): Ditto.
(riscv_block_move_loop): Ditto.
(riscv_expand_block_move): Ditto.
---
 gcc/config/riscv/riscv.c | 24 +---
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index fffd0814eee..96fc0c0a4a0 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -3146,9 +3146,9 @@ riscv_legitimize_call_address (rtx addr)
Assume that the areas do not overlap.  */
 
 static void
-riscv_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
+riscv_block_move_straight (rtx dest, rtx src, unsigned HOST_WIDE_INT length)
 {
-  HOST_WIDE_INT offset, delta;
+  unsigned HOST_WIDE_INT offset, delta;
   unsigned HOST_WIDE_INT bits;
   int i;
   enum machine_mode mode;
@@ -3194,8 +3194,8 @@ riscv_block_move_straight (rtx dest, rtx src, 
HOST_WIDE_INT length)
register.  Store them in *LOOP_REG and *LOOP_MEM respectively.  */
 
 static void
-riscv_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
-  rtx *loop_reg, rtx *loop_mem)
+riscv_adjust_block_mem (rtx mem, unsigned HOST_WIDE_INT length,
+   rtx *loop_reg, rtx *loop_mem)
 {
   *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
 
@@ -3210,11 +3210,11 @@ riscv_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
the memory regions do not overlap.  */
 
 static void
-riscv_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
- HOST_WIDE_INT bytes_per_iter)
+riscv_block_move_loop (rtx dest, rtx src, unsigned HOST_WIDE_INT length,
+  unsigned HOST_WIDE_INT bytes_per_iter)
 {
   rtx label, src_reg, dest_reg, final_src, test;
-  HOST_WIDE_INT leftover;
+  unsigned HOST_WIDE_INT leftover;
 
   leftover = length % bytes_per_iter;
   length -= leftover;
@@ -3259,18 +3259,19 @@ riscv_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT 
length,
 bool
 riscv_expand_block_move (rtx dest, rtx src, rtx length)
 {
+  unsigned HOST_WIDE_INT hwi_length = UINTVAL (length);
   if (CONST_INT_P (length))
 {
-  HOST_WIDE_INT factor, align;
+  unsigned HOST_WIDE_INT factor, align;
 
   align = MIN (MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), BITS_PER_WORD);
   factor = BITS_PER_WORD / align;
 
   if (optimize_function_for_size_p (cfun)
- && INTVAL (length) * factor * UNITS_PER_WORD > MOVE_RATIO (false))
+ && hwi_length * factor * UNITS_PER_WORD > MOVE_RATIO (false))
return false;
 
-  if (INTVAL (length) <= RISCV_MAX_MOVE_BYTES_STRAIGHT / factor)
+  if (hwi_length <= (RISCV_MAX_MOVE_BYTES_STRAIGHT / factor))
{
  riscv_block_move_straight (dest, src, INTVAL (length));
  return true;
@@ -3280,7 +3281,8 @@ riscv_expand_block_move (rtx dest, rtx src, rtx length)
  unsigned min_iter_words
= RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD;
  unsigned iter_words = min_iter_words;
- HOST_WIDE_INT bytes = INTVAL (length), words = bytes / UNITS_PER_WORD;
+ unsigned HOST_WIDE_INT bytes = hwi_length;
+ unsigned HOST_WIDE_INT words = bytes / UNITS_PER_WORD;
 
  /* Lengthen the loop body if it shortens the tail.  */
  for (unsigned i = min_iter_words; i < min_iter_words * 2 - 1; i++)
-- 
2.30.0

Re: [PATCH] RISC-V: Allow multi-lib build with different code model

[Kito Cheng]

Committed to trunk.

On Wed, Jul 21, 2021 at 4:45 PM Kito Cheng  wrote:
>
> --with-multilib-generator was only support for different ISA/ABI
> combination, however code model is effect the code gen a lots it
> should able to handled in multilib mechanism.
>
> Adding `--cmodel=` option to `--with-multilib-generator` to generating
> multilib combination with different code model.
>
> E.g.
> --with-multilib-generator="rv64ima-lp64--;--cmodel=medlow,medany"
> will generate 3 multi-lib suppport:
> 1) rv64ima with lp64
> 2) rv64ima with lp64 and medlow code model
> 3) rv64ima with lp64 and medany code model
>
> gcc/
>
> * config/riscv/multilib-generator: Support code model option for
> multi-lib.
> * doc/install.texi: Add document of new option for
> --with-multilib-generator.
> ---
>  gcc/config/riscv/multilib-generator | 86 +++--
>  gcc/doc/install.texi| 17 ++
>  2 files changed, 73 insertions(+), 30 deletions(-)
>
> diff --git a/gcc/config/riscv/multilib-generator 
> b/gcc/config/riscv/multilib-generator
> index fe115b3184f..1164d1c5c8e 100755
> --- a/gcc/config/riscv/multilib-generator
> +++ b/gcc/config/riscv/multilib-generator
> @@ -40,6 +40,7 @@ import collections
>  import itertools
>  from functools import reduce
>  import subprocess
> +import argparse
>
>  #
>  # TODO: Add test for this script.
> @@ -127,44 +128,69 @@ def expand_combination(ext):
>
>return ext
>
> -for cfg in sys.argv[1:]:
> -  try:
> -(arch, abi, extra, ext) = cfg.split('-')
> -  except:
> -print ("Invalid configure string %s, ---\n"
> -   " and  can be empty, "
> -   "e.g. rv32imafd-ilp32--" % cfg)
> -sys.exit(1)
> -
> -  arch = arch_canonicalize (arch)
> -  arches[arch] = 1
> -  abis[abi] = 1
> -  extra = list(filter(None, extra.split(',')))
> -  ext_combs = expand_combination(ext)
> -  alts = sum([[x] + [x + y for y in ext_combs] for x in [arch] + extra], [])
> -  alts = list(map(arch_canonicalize, alts))
> +multilib_cfgs = filter(lambda x:not x.startswith("--"), sys.argv[1:])
> +options = filter(lambda x:x.startswith("--"), sys.argv[1:])
> +
> +parser = argparse.ArgumentParser()
> +parser.add_argument("--cmodel", type=str)
> +parser.add_argument("cfgs", type=str, nargs='*')
> +args = parser.parse_args()
> +
> +if args.cmodel:
> +  cmodels = [None] + args.cmodel.split(",")
> +else:
> +  cmodels = [None]
> +
> +cmodel_options = '/'.join(['mcmodel=%s' % x for x in cmodels[1:]])
> +cmodel_dirnames = ' \\\n'.join(cmodels[1:])
> +
> +for cmodel in cmodels:
> +  for cfg in args.cfgs:
> +try:
> +  (arch, abi, extra, ext) = cfg.split('-')
> +except:
> +  print ("Invalid configure string %s, 
> ---\n"
> + " and  can be empty, "
> + "e.g. rv32imafd-ilp32--" % cfg)
> +  sys.exit(1)
> +
> +# Compact code model only support rv64.
> +if cmodel == "compact" and arch.startswith("rv32"):
> +  continue
>
> -  # Drop duplicated entry.
> -  alts = unique(alts)
> +arch = arch_canonicalize (arch)
> +arches[arch] = 1
> +abis[abi] = 1
> +extra = list(filter(None, extra.split(',')))
> +ext_combs = expand_combination(ext)
> +alts = sum([[x] + [x + y for y in ext_combs] for x in [arch] + extra], 
> [])
> +alts = list(map(arch_canonicalize, alts))
>
> -  for alt in alts:
> -if alt == arch:
> -  continue
> -arches[alt] = 1
> -reuse.append('march.%s/mabi.%s=march.%s/mabi.%s' % (arch, abi, alt, abi))
> -  required.append('march=%s/mabi=%s' % (arch, abi))
> +# Drop duplicated entry.
> +alts = unique(alts)
> +
> +for alt in alts[1:]:
> +  if alt == arch:
> +continue
> +  arches[alt] = 1
> +  reuse.append('march.%s/mabi.%s=march.%s/mabi.%s' % (arch, abi, alt, 
> abi))
> +
> +if cmodel:
> +  required.append('march=%s/mabi=%s/mcmodel=%s' % (arch, abi, cmodel))
> +else:
> +  required.append('march=%s/mabi=%s' % (arch, abi))
>
> -arch_options = '/'.join(['march=%s' % x for x in arches.keys()])
> -arch_dirnames = ' \\\n'.join(arches.keys())
> +  arch_options = '/'.join(['march=%s' % x for x in arches.keys()])
> +  arch_dirnames = ' \\\n'.join(arches.keys())
>
> -abi_options = '/'.join(['mabi=%s' %

[PATCH v2] PR target/96759 - Handle global variable assignment from misaligned structure/PARALLEL return values.

[Kito Cheng]

In g:70cdb21e579191fe9f0f1d45e328908e59c0179e, DECL/global variable has handled
misaligned stores, but it didn't handle PARALLEL values, and I refer the
other part of this function, I found the PARALLEL need handled by
emit_group_* functions, so I add a check, and using emit_group_store if
storing a PARALLEL value, also checked this change didn't break the
testcase(gcc.target/arm/unaligned-argument-3.c) added by the orginal changes.

For riscv64 target, struct S {int a; double b;} will pack into a parallel
value to return and it has TImode when misaligned access is supported,
however TImode required 16-byte align, but it only 8-byte align, so it go to
the misaligned stores handling, then it will try to generate move
instruction from a PARALLEL value.

Tested on following target without introduced new reguression:
  - riscv32/riscv64 elf
  - x86_64-linux
  - arm-eabi

v2 changes:
  - Use maybe_emit_group_store instead of emit_group_store.
  - Remove push_temp_slots/pop_temp_slots, emit_group_store only require
stack temp slot when dst is CONCAT or PARALLEL, however
maybe_emit_group_store will always use REG for dst if needed.

gcc/ChangeLog:

PR target/96759
* expr.c (expand_assignment): Handle misaligned stores with PARALLEL
value.

gcc/testsuite/ChangeLog:

PR target/96759
* g++.target/riscv/pr96759.C: New.
* gcc.target/riscv/pr96759.c: New.
---
 gcc/expr.c   |  2 ++
 gcc/testsuite/g++.target/riscv/pr96759.C |  8 
 gcc/testsuite/gcc.target/riscv/pr96759.c | 13 +
 3 files changed, 23 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/pr96759.C
 create mode 100644 gcc/testsuite/gcc.target/riscv/pr96759.c

diff --git a/gcc/expr.c b/gcc/expr.c
index 1a15f24b3979..6eb13a12c8c5 100644
--- a/gcc/expr.c
+++ b/gcc/expr.c
@@ -5168,6 +5168,8 @@ expand_assignment (tree to, tree from, bool nontemporal)
   rtx reg, mem;
 
   reg = expand_expr (from, NULL_RTX, VOIDmode, EXPAND_NORMAL);
+  /* Handle PARALLEL.  */
+  reg = maybe_emit_group_store (reg, TREE_TYPE (from));
   reg = force_not_mem (reg);
   mem = expand_expr (to, NULL_RTX, VOIDmode, EXPAND_WRITE);
   if (TREE_CODE (to) == MEM_REF && REF_REVERSE_STORAGE_ORDER (to))
diff --git a/gcc/testsuite/g++.target/riscv/pr96759.C 
b/gcc/testsuite/g++.target/riscv/pr96759.C
new file mode 100644
index ..673999a4baf7
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/pr96759.C
@@ -0,0 +1,8 @@
+/* { dg-options "-mno-strict-align -std=gnu++17" } */
+/* { dg-do compile } */
+struct S {
+  int a;
+  double b;
+};
+S GetNumbers();
+auto [globalC, globalD] = GetNumbers();
diff --git a/gcc/testsuite/gcc.target/riscv/pr96759.c 
b/gcc/testsuite/gcc.target/riscv/pr96759.c
new file mode 100644
index ..621c39196fca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr96759.c
@@ -0,0 +1,13 @@
+/* { dg-options "-mno-strict-align" } */
+/* { dg-do compile } */
+
+struct S {
+  int a;
+  double b;
+};
+struct S GetNumbers();
+struct S g;
+
+void foo(){
+  g = GetNumbers();
+}
-- 
2.28.0

[PATCH] RISC-V: Define __riscv_cmodel_medany for PIC mode.

[Kito Cheng]

 - According the conclusion in RISC-V C API document, we decide to deprecat
   the __riscv_cmodel_pic marco

 - __riscv_cmodel_pic is deprecated and will removed in next GCC
   release.

[1] https://github.com/riscv/riscv-c-api-doc/pull/11
---
 gcc/config/riscv/riscv-c.c| 7 ---
 gcc/testsuite/gcc.target/riscv/predef-3.c | 6 +++---
 gcc/testsuite/gcc.target/riscv/predef-6.c | 6 +++---
 3 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/gcc/config/riscv/riscv-c.c b/gcc/config/riscv/riscv-c.c
index 735f2f2f513f..9221fcbaca5d 100644
--- a/gcc/config/riscv/riscv-c.c
+++ b/gcc/config/riscv/riscv-c.c
@@ -90,12 +90,13 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
   builtin_define ("__riscv_cmodel_medlow");
   break;
 
+case CM_PIC:
+  builtin_define ("__riscv_cmodel_pic");
+  /* FALLTHROUGH. */
+
 case CM_MEDANY:
   builtin_define ("__riscv_cmodel_medany");
   break;
 
-case CM_PIC:
-  builtin_define ("__riscv_cmodel_pic");
-  break;
 }
 }
diff --git a/gcc/testsuite/gcc.target/riscv/predef-3.c 
b/gcc/testsuite/gcc.target/riscv/predef-3.c
index 6f4f2e219941..d7c9793b3d7c 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-3.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-3.c
@@ -55,11 +55,11 @@ int main () {
 #if defined(__riscv_cmodel_medlow)
 #error "__riscv_cmodel_medlow"
 #endif
-#if defined(__riscv_cmodel_medany)
-#error "__riscv_cmodel_medlow"
+#if !defined(__riscv_cmodel_medany)
+#error "__riscv_cmodel_medany"
 #endif
 #if !defined(__riscv_cmodel_pic)
-#error "__riscv_cmodel_medlow"
+#error "__riscv_cmodel_pic"
 #endif
 
   return 0;
diff --git a/gcc/testsuite/gcc.target/riscv/predef-6.c 
b/gcc/testsuite/gcc.target/riscv/predef-6.c
index ee4e02bcb63e..7530f9598aeb 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-6.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-6.c
@@ -55,11 +55,11 @@ int main () {
 #if defined(__riscv_cmodel_medlow)
 #error "__riscv_cmodel_medlow"
 #endif
-#if defined(__riscv_cmodel_medany)
-#error "__riscv_cmodel_medlow"
+#if !defined(__riscv_cmodel_medany)
+#error "__riscv_cmodel_medany"
 #endif
 #if !defined(__riscv_cmodel_pic)
-#error "__riscv_cmodel_medlow"
+#error "__riscv_cmodel_medpic"
 #endif
 
   return 0;
-- 
2.28.0

Re: [PATCH v2] PR target/96759 - Handle global variable assignment from misaligned structure/PARALLEL return values.

[Kito Cheng]

ping.


On Fri, Sep 25, 2020 at 2:33 PM Richard Biener  wrote:

> On Fri, 25 Sep 2020, Kito Cheng wrote:
>
> > In g:70cdb21e579191fe9f0f1d45e328908e59c0179e, DECL/global variable has
> handled
> > misaligned stores, but it didn't handle PARALLEL values, and I refer the
> > other part of this function, I found the PARALLEL need handled by
> > emit_group_* functions, so I add a check, and using emit_group_store if
> > storing a PARALLEL value, also checked this change didn't break the
> > testcase(gcc.target/arm/unaligned-argument-3.c) added by the orginal
> changes.
> >
> > For riscv64 target, struct S {int a; double b;} will pack into a parallel
> > value to return and it has TImode when misaligned access is supported,
> > however TImode required 16-byte align, but it only 8-byte align, so it
> go to
> > the misaligned stores handling, then it will try to generate move
> > instruction from a PARALLEL value.
> >
> > Tested on following target without introduced new reguression:
> >   - riscv32/riscv64 elf
> >   - x86_64-linux
> >   - arm-eabi
>
> OK if Eric says so.
>
> Thanks,
> Richard.
>
> > v2 changes:
> >   - Use maybe_emit_group_store instead of emit_group_store.
> >   - Remove push_temp_slots/pop_temp_slots, emit_group_store only require
> > stack temp slot when dst is CONCAT or PARALLEL, however
> > maybe_emit_group_store will always use REG for dst if needed.
> >
> > gcc/ChangeLog:
> >
> >   PR target/96759
> >   * expr.c (expand_assignment): Handle misaligned stores with
> PARALLEL
> >   value.
> >
> > gcc/testsuite/ChangeLog:
> >
> >   PR target/96759
> >   * g++.target/riscv/pr96759.C: New.
> >   * gcc.target/riscv/pr96759.c: New.
> > ---
> >  gcc/expr.c   |  2 ++
> >  gcc/testsuite/g++.target/riscv/pr96759.C |  8 
> >  gcc/testsuite/gcc.target/riscv/pr96759.c | 13 +
> >  3 files changed, 23 insertions(+)
> >  create mode 100644 gcc/testsuite/g++.target/riscv/pr96759.C
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/pr96759.c
> >
> > diff --git a/gcc/expr.c b/gcc/expr.c
> > index 1a15f24b3979..6eb13a12c8c5 100644
> > --- a/gcc/expr.c
> > +++ b/gcc/expr.c
> > @@ -5168,6 +5168,8 @@ expand_assignment (tree to, tree from, bool
> nontemporal)
> >rtx reg, mem;
> >
> >reg = expand_expr (from, NULL_RTX, VOIDmode, EXPAND_NORMAL);
> > +  /* Handle PARALLEL.  */
> > +  reg = maybe_emit_group_store (reg, TREE_TYPE (from));
> >reg = force_not_mem (reg);
> >mem = expand_expr (to, NULL_RTX, VOIDmode, EXPAND_WRITE);
> >if (TREE_CODE (to) == MEM_REF && REF_REVERSE_STORAGE_ORDER (to))
> > diff --git a/gcc/testsuite/g++.target/riscv/pr96759.C
> b/gcc/testsuite/g++.target/riscv/pr96759.C
> > new file mode 100644
> > index ..673999a4baf7
> > --- /dev/null
> > +++ b/gcc/testsuite/g++.target/riscv/pr96759.C
> > @@ -0,0 +1,8 @@
> > +/* { dg-options "-mno-strict-align -std=gnu++17" } */
> > +/* { dg-do compile } */
> > +struct S {
> > +  int a;
> > +  double b;
> > +};
> > +S GetNumbers();
> > +auto [globalC, globalD] = GetNumbers();
> > diff --git a/gcc/testsuite/gcc.target/riscv/pr96759.c
> b/gcc/testsuite/gcc.target/riscv/pr96759.c
> > new file mode 100644
> > index ..621c39196fca
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/riscv/pr96759.c
> > @@ -0,0 +1,13 @@
> > +/* { dg-options "-mno-strict-align" } */
> > +/* { dg-do compile } */
> > +
> > +struct S {
> > +  int a;
> > +  double b;
> > +};
> > +struct S GetNumbers();
> > +struct S g;
> > +
> > +void foo(){
> > +  g = GetNumbers();
> > +}
> >
>
> --
> Richard Biener 
> SUSE Software Solutions Germany GmbH, Maxfeldstrasse 5, 90409 Nuernberg,
> Germany; GF: Felix Imend
>

[PATCH] PR target/96307: Fix KASAN option checking.

[Kito Cheng]

 - Disable kasan if target is unsupported and -fasan-shadow-offset= is not
   given, no matter `--param asan-stack=1` is given or not.

 - Moving KASAN option checking testcase to gcc.dg, those testcase could be
   useful for all other target which not support asan.

 - Verifed on riscv and x86.

gcc/ChangeLog:

PR target/96307
* toplev.c (process_options): Remove param_asan_stack checking for kasan
option checking.

gcc/testsuite/ChangeLog:

PR target/96307
* gcc.dg/pr96307.c: New.
* gcc.target/riscv/pr96260.c: Move this test case from here to ...
* gcc.dg/pr96260.c: ... here.
* gcc.target/riscv/pr91441.c: Move this test case from here to ...
* gcc.dg/pr91441.c: ... here.
* lib/target-supports.exp (check_effective_target_no_fsanitize_address):
New proc.
---
 .../{gcc.target/riscv => gcc.dg}/pr91441.c|  1 +
 .../{gcc.target/riscv => gcc.dg}/pr96260.c|  1 +
 gcc/testsuite/gcc.dg/pr96307.c| 25 +++
 gcc/testsuite/lib/target-supports.exp | 11 
 gcc/toplev.c  |  1 -
 5 files changed, 38 insertions(+), 1 deletion(-)
 rename gcc/testsuite/{gcc.target/riscv => gcc.dg}/pr91441.c (85%)
 rename gcc/testsuite/{gcc.target/riscv => gcc.dg}/pr96260.c (77%)
 create mode 100644 gcc/testsuite/gcc.dg/pr96307.c

diff --git a/gcc/testsuite/gcc.target/riscv/pr91441.c 
b/gcc/testsuite/gcc.dg/pr91441.c
similarity index 85%
rename from gcc/testsuite/gcc.target/riscv/pr91441.c
rename to gcc/testsuite/gcc.dg/pr91441.c
index b55df5e7f00c..4f7a8fbec5e9 100644
--- a/gcc/testsuite/gcc.target/riscv/pr91441.c
+++ b/gcc/testsuite/gcc.dg/pr91441.c
@@ -1,5 +1,6 @@
 /* PR target/91441 */
 /* { dg-do compile  } */
+/* { dg-require-effective-target no_fsanitize_address }*/
 /* { dg-options "--param asan-stack=1 -fsanitize=kernel-address" } */
 
 int *bar(int *);
diff --git a/gcc/testsuite/gcc.target/riscv/pr96260.c 
b/gcc/testsuite/gcc.dg/pr96260.c
similarity index 77%
rename from gcc/testsuite/gcc.target/riscv/pr96260.c
rename to gcc/testsuite/gcc.dg/pr96260.c
index 229997f877b7..734832f021e3 100644
--- a/gcc/testsuite/gcc.target/riscv/pr96260.c
+++ b/gcc/testsuite/gcc.dg/pr96260.c
@@ -1,5 +1,6 @@
 /* PR target/96260 */
 /* { dg-do compile } */
+/* { dg-require-effective-target no_fsanitize_address }*/
 /* { dg-options "--param asan-stack=1 -fsanitize=kernel-address 
-fasan-shadow-offset=0x10" } */
 
 int *bar(int *);
diff --git a/gcc/testsuite/gcc.dg/pr96307.c b/gcc/testsuite/gcc.dg/pr96307.c
new file mode 100644
index ..cd1c17c9661b
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr96307.c
@@ -0,0 +1,25 @@
+/* PR target/96307 */
+/* { dg-do compile } */
+/* { dg-require-effective-target no_fsanitize_address }*/
+/* { dg-additional-options "-fsanitize=kernel-address 
--param=asan-instrumentation-with-call-threshold=8" } */
+
+#include 
+enum a {test1, test2, test3=INT_MAX};
+enum a a;
+enum a *b;
+
+void reset (void);
+
+void
+t()
+{
+  if (a != test2)
+__builtin_abort ();
+  if (*b != test2)
+__builtin_abort ();
+  reset ();
+  if (a != test1)
+__builtin_abort ();
+  if (*b != test1)
+__builtin_abort ();
+}
diff --git a/gcc/testsuite/lib/target-supports.exp 
b/gcc/testsuite/lib/target-supports.exp
index 8314e443c437..e80b71a2110c 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -10552,3 +10552,14 @@ proc check_effective_target_ident_directive {} {
int i;
 }]
 }
+
+# Return 1 if target is not support address sanitize, 1 otherwise.
+
+proc check_effective_target_no_fsanitize_address {} {
+if ![check_no_compiler_messages fsanitize_address executable {
+   int main (void) { return 0; }
+}] {
+   return 1;
+}
+return 0;
+}
diff --git a/gcc/toplev.c b/gcc/toplev.c
index a4cb8bb262ed..540e131d963d 100644
--- a/gcc/toplev.c
+++ b/gcc/toplev.c
@@ -1842,7 +1842,6 @@ process_options (void)
 
   if ((flag_sanitize & SANITIZE_KERNEL_ADDRESS)
   && (targetm.asan_shadow_offset == NULL
- && param_asan_stack
  && !asan_shadow_offset_set_p ()))
 {
   warning_at (UNKNOWN_LOCATION, 0,
-- 
2.28.0

[PATCH] RISC-V: Derive ABI from -march if -mabi is not present.

[Kito Cheng]

Hi Jim, Palmer and Andrew:

I think this patch is kind of major change for GCC RISC-V port, so I cc all
RISC-V gcc maintainer to make sure this change is fine with you guys.

 - Motivation of this patch:
   1. Sync behavior between clang/llvm.
   2. Preparation for -mcpu option support, -mcpu will set -march
  according the core default arch, however it would be awkward
  if we only change arch: user need to know the default arch of
  the core and then set the right ABI, of cause user still can
  specify arch and abi via -march and -mabi.

 - This patch has change the behavior for default value of ABI, the ABI
   will derive from -march if -mabi is not given, which is same behavior
   as clang/llvm.

 - So the new rule for the ABI:
   - Use value from -mabi if the option is present.
   - Derive ABI from -march if -mabi is not present.
   - Using default value from `--with-abi` if -mabi and -march are both not
 present.

 - Derivative rule:
   - Using ilp32e E-extension is present.
   - Using ilp32d or lp64d if D-extension is present.
   - Otherwise using ilp32 or lp64.

gcc/ChangeLog:

* common/config/riscv/riscv-common.c:
* config/riscv/riscv.h:
* doc/invoke.texi

gcc/testsuite/ChangeLog:

* gcc.target/riscv/implied-abi-1.c: New.
* gcc.target/riscv/implied-abi-2.c: Ditto.
* gcc.target/riscv/implied-abi-3.c: Ditto.
* gcc.target/riscv/implied-abi-4.c: Ditto.
* gcc.target/riscv/implied-abi-5.c: Ditto.
* gcc.target/riscv/implied-abi-6.c: Ditto.
* gcc.target/riscv/implied-abi-7.c: Ditto.
* gcc.target/riscv/implied-abi-8.c: Ditto.
---
 gcc/common/config/riscv/riscv-common.c| 142 +-
 gcc/config/riscv/riscv.h  |  13 +-
 gcc/doc/invoke.texi   |   9 +-
 .../gcc.target/riscv/implied-abi-1.c  |  10 ++
 .../gcc.target/riscv/implied-abi-2.c  |  10 ++
 .../gcc.target/riscv/implied-abi-3.c  |  10 ++
 .../gcc.target/riscv/implied-abi-4.c  |  10 ++
 .../gcc.target/riscv/implied-abi-5.c  |  10 ++
 .../gcc.target/riscv/implied-abi-6.c  |  10 ++
 .../gcc.target/riscv/implied-abi-7.c  |  10 ++
 .../gcc.target/riscv/implied-abi-8.c  |  10 ++
 11 files changed, 204 insertions(+), 40 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/implied-abi-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/implied-abi-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/implied-abi-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/implied-abi-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/implied-abi-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/implied-abi-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/implied-abi-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/implied-abi-8.c

diff --git a/gcc/common/config/riscv/riscv-common.c 
b/gcc/common/config/riscv/riscv-common.c
index 82c5154b6118..07afc1a365e3 100644
--- a/gcc/common/config/riscv/riscv-common.c
+++ b/gcc/common/config/riscv/riscv-common.c
@@ -79,7 +79,10 @@ private:
   /* X-len of m_arch. */
   unsigned m_xlen;
 
-  riscv_subset_list (const char *, location_t);
+  /* Silent mode, don't emit error if m_silent_p is true.  */
+  bool m_silent_p;
+
+  riscv_subset_list (const char *, location_t, bool);
 
   const char *parsing_subset_version (const char *, unsigned *, unsigned *,
  unsigned, unsigned, bool, bool *);
@@ -104,7 +107,7 @@ public:
 
   unsigned xlen() const {return m_xlen;};
 
-  static riscv_subset_list *parse (const char *, location_t);
+  static riscv_subset_list *parse (const char *, location_t, bool silent_p);
 
 };
 
@@ -118,8 +121,11 @@ riscv_subset_t::riscv_subset_t ()
 {
 }
 
-riscv_subset_list::riscv_subset_list (const char *arch, location_t loc)
-  : m_arch (arch), m_loc (loc), m_head (NULL), m_tail (NULL), m_xlen (0)
+riscv_subset_list::riscv_subset_list (const char *arch,
+ location_t loc,
+ bool silent_p)
+  : m_arch (arch), m_loc (loc), m_head (NULL), m_tail (NULL),
+m_xlen (0), m_silent_p(silent_p)
 {
 }
 
@@ -283,8 +289,9 @@ riscv_subset_list::parsing_subset_version (const char *p,
}
  else
{
- error_at (m_loc, "%<-march=%s%>: Expect number "
-   "after %<%dp%>.", m_arch, version);
+ if (!m_silent_p)
+   error_at (m_loc, "%<-march=%s%>: Expect number "
+ "after %<%dp%>.", m_arch, version);
  return NULL;
}
}
@@ -363,8 +370,9 @@ riscv_subset_list::parse_std_ext (const char *p)
 
   if (m_xlen > 32)
{
- error_at (m_loc, "%<-march=%s%>: rv%de is not a valid base ISA",
-   m_arch, m_xlen);
+ if (!m_silent_p)
+   error_at (m

[PATCH] RISC-V: Support --target-help for -mcpu/-mtune

[Kito Cheng]

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (riscv_tunes): New.
(riscv_get_valid_option_values): New.
(TARGET_GET_VALID_OPTION_VALUES): New.
* config/riscv/riscv-cores.def (RISCV_TUNE): New, define options
for tune here.
(RISCV_CORE): Fix comment.
* config/riscv/riscv.cc (riscv_tune_info_table): Move definition to
riscv-cores.def.
---
 gcc/common/config/riscv/riscv-common.cc | 46 +
 gcc/config/riscv/riscv-cores.def| 35 ---
 gcc/config/riscv/riscv.cc   |  9 ++---
 3 files changed, 80 insertions(+), 10 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index c39ed2e2696..697bfe435c8 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -224,6 +224,14 @@ static const riscv_cpu_info riscv_cpu_tables[] =
 {NULL, NULL, NULL}
 };
 
+static const char *riscv_tunes[] =
+{
+#define RISCV_TUNE(TUNE_NAME, PIPELINE_MODEL, TUNE_INFO) \
+TUNE_NAME,
+#include "../../../config/riscv/riscv-cores.def"
+NULL
+};
+
 static const char *riscv_supported_std_ext (void);
 
 static riscv_subset_list *current_subset_list = NULL;
@@ -1683,6 +1691,41 @@ riscv_compute_multilib (
 return xstrdup (multilib_infos[best_match_multi_lib].path.c_str ());
 }
 
+vec
+riscv_get_valid_option_values (int option_code,
+  const char *prefix ATTRIBUTE_UNUSED)
+{
+  vec v;
+  v.create (0);
+  opt_code opt = (opt_code) option_code;
+
+  switch (opt)
+{
+case OPT_mtune_:
+  {
+   const char **tune = &riscv_tunes[0];
+   for (;*tune; ++tune)
+ v.safe_push (*tune);
+
+   const riscv_cpu_info *cpu_info = &riscv_cpu_tables[0];
+   for (;cpu_info->name; ++cpu_info)
+ v.safe_push (cpu_info->name);
+  }
+  break;
+case OPT_mcpu_:
+  {
+   const riscv_cpu_info *cpu_info = &riscv_cpu_tables[0];
+   for (;cpu_info->name; ++cpu_info)
+ v.safe_push (cpu_info->name);
+  }
+  break;
+default:
+  break;
+}
+
+  return v;
+}
+
 #undef TARGET_COMPUTE_MULTILIB
 #define TARGET_COMPUTE_MULTILIB riscv_compute_multilib
 #endif
@@ -1701,4 +1744,7 @@ static const struct default_options 
riscv_option_optimization_table[] =
 #undef TARGET_HANDLE_OPTION
 #define TARGET_HANDLE_OPTION riscv_handle_option
 
+#undef  TARGET_GET_VALID_OPTION_VALUES
+#define TARGET_GET_VALID_OPTION_VALUES riscv_get_valid_option_values
+
 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index ecb5e213d98..b84ad999ac1 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -17,19 +17,46 @@
along with GCC; see the file COPYING3.  If not see
.  */
 
+/* This is a list of tune that implement RISC-V.
+
+   Before using #include to read this file, define a macro:
+
+  RISCV_TUNE(TUNE_NAME, PIPELINE_MODEL, TUNE_INFO)
+
+   The TUNE_NAME is the name of the micro-arch, represented as a string.
+   The PIPELINE_MODEL is the pipeline model of the micro-arch, represented as a
+   string, defined in riscv.md.
+   The TUNE_INFO is the detail cost model for this core, represented as an
+   identifier, reference to riscv.cc.  */
+
+#ifndef RISCV_TUNE
+#define RISCV_TUNE(TUNE_NAME, PIPELINE_MODEL, TUNE_INFO)
+#endif
+
+RISCV_TUNE("rocket", generic, rocket_tune_info)
+RISCV_TUNE("sifive-3-series", generic, rocket_tune_info)
+RISCV_TUNE("sifive-5-series", generic, rocket_tune_info)
+RISCV_TUNE("sifive-7-series", generic, sifive_7_tune_info)
+RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
+RISCV_TUNE("size", generic, optimize_size_tune_info)
+
+#undef RISCV_TUNE
+
 /* This is a list of cores that implement RISC-V.
 
Before using #include to read this file, define a macro:
 
-  RISCV_CORE(CORE_NAME, ARCH, MICRO_ARCH, TUNE_INFO)
+  RISCV_CORE(CORE_NAME, ARCH, MICRO_ARCH)
 
The CORE_NAME is the name of the core, represented as a string.
The ARCH is the default arch of the core, represented as a string,
can be NULL if no default arch.
The MICRO_ARCH is the name of the core for which scheduling decisions
-   will be made, represented as an identifier.
-   The TUNE_INFO is the detail cost model for this core, represented as an
-   identifier, reference to riscv-tunes.def.  */
+   will be made, represented as an identifier.  */
+
+#ifndef RISCV_CORE
+#define RISCV_CORE(CORE_NAME, ARCH, MICRO_ARCH)
+#endif
 
 RISCV_CORE("sifive-e20",  "rv32imc","rocket")
 RISCV_CORE("sifive-e21",  "rv32imac",   "rocket")
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 0d618315828..00b7df02e2e 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -395,12 +395,9 @@ static const unsigned gpr_save_reg_order[] = {

[PATCH] PR middle-end/88345: Honor -falign-functions=N even optimized for size.

[Kito Cheng]

From: Monk Chiang 

Currnetly setting of -falign-functions=N will be ignored if the function
is optimized for size or marked as cold function.

However function alignment requirement is needed even optimized for
size in some situations, RISC-V target is an example, RISC-V kernel implement
patchable function that require function must be align to at least 4 bytes for
atomicly patch the function prologue.

Here is 4 way to fix that:
1. Fix -falign-functions=N, let it work as expect on -Os and all cold
functions, which is this patch.
2. Force align to 4 byte if -fpatchable-function-entry is given by adjust
RISC-V's FUNCTION_BOUNDARY.
3. Adjust RISC-V's FUNCTION_BOUNDARY to let it honor to -falign-functions=N.
4. Adding a -malign-functions=N for RISC-V...which x86 already deprecated that.

And this patch is the first approach.

gcc/ChangeLog:

PR middle-end/88345
* varasm.cc (assemble_start_function): Adjust function align
even optimized for size.
* doc/invoke.texi (Os): Remove -falign-functions= from the exclusion
list of -Os.

gcc/testsuite/ChangeLog:

PR middle-end/88345
* gcc.target/i386/pr88345-1.c: New.
* gcc.target/i386/pr88345-2.c: Ditto.
* gcc.target/riscv/pr88345-1.c: Ditto.
* gcc.target/riscv/pr88345-2.c: Ditto.
---
 gcc/doc/invoke.texi| 2 +-
 gcc/testsuite/gcc.target/i386/pr88345-1.c  | 5 +
 gcc/testsuite/gcc.target/i386/pr88345-2.c  | 5 +
 gcc/testsuite/gcc.target/riscv/pr88345-1.c | 5 +
 gcc/testsuite/gcc.target/riscv/pr88345-2.c | 5 +
 gcc/varasm.cc  | 3 +--
 6 files changed, 22 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr88345-1.c
 create mode 100644 gcc/testsuite/gcc.target/i386/pr88345-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/pr88345-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/pr88345-2.c

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index a2b0b9636f0..acf98c68825 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -11381,7 +11381,7 @@ results.  This is the default.
 Optimize for size.  @option{-Os} enables all @option{-O2} optimizations 
 except those that often increase code size:
 
-@gccoptlist{-falign-functions  -falign-jumps @gol
+@gccoptlist{-falign-jumps @gol
 -falign-labels  -falign-loops @gol
 -fprefetch-loop-arrays  -freorder-blocks-algorithm=stc}
 
diff --git a/gcc/testsuite/gcc.target/i386/pr88345-1.c 
b/gcc/testsuite/gcc.target/i386/pr88345-1.c
new file mode 100644
index 000..226bb9ffc82
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr88345-1.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-falign-functions=128" } */
+/* { dg-final { scan-assembler-times "\.p2align\t7" 1 } } */
+
+__attribute__((__cold__)) void a() {}
diff --git a/gcc/testsuite/gcc.target/i386/pr88345-2.c 
b/gcc/testsuite/gcc.target/i386/pr88345-2.c
new file mode 100644
index 000..a7fc3b162dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr88345-2.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-falign-functions=128 -Os" } */
+/* { dg-final { scan-assembler-times "\.p2align\t7" 1 } } */
+
+void a() {}
diff --git a/gcc/testsuite/gcc.target/riscv/pr88345-1.c 
b/gcc/testsuite/gcc.target/riscv/pr88345-1.c
new file mode 100644
index 000..7d5afe683eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr88345-1.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-falign-functions=128" } */
+/* { dg-final { scan-assembler-times "\.align\t7" 1 } } */
+
+__attribute__((__cold__)) void a() {}
diff --git a/gcc/testsuite/gcc.target/riscv/pr88345-2.c 
b/gcc/testsuite/gcc.target/riscv/pr88345-2.c
new file mode 100644
index 000..d4fc89d86d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr88345-2.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-falign-functions=128 -Os" } */
+/* { dg-final { scan-assembler-times "\.align\t7" 1 } } */
+
+void a() {}
diff --git a/gcc/varasm.cc b/gcc/varasm.cc
index 423f3f91af8..4001648b214 100644
--- a/gcc/varasm.cc
+++ b/gcc/varasm.cc
@@ -1923,8 +1923,7 @@ assemble_start_function (tree decl, const char *fnname)
  Note that we still need to align to DECL_ALIGN, as above,
  because ASM_OUTPUT_MAX_SKIP_ALIGN might not do any alignment at all.  */
   if (! DECL_USER_ALIGN (decl)
-  && align_functions.levels[0].log > align
-  && optimize_function_for_speed_p (cfun))
+  && align_functions.levels[0].log > align)
 {
 #ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
   int align_log = align_functions.levels[0].log;
-- 
2.37.2

[committed] RISC-V: Add newline to the end of file [NFC]

[Kito Cheng]

gcc/ChangeLog:

* config/riscv/riscv-c.cc: Add newline to the end of file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/pragma-1.c: Add newline to the end of file.
* gcc.target/riscv/rvv/base/pragma-2.c: Ditto.
* gcc.target/riscv/rvv/base/pragma-3.c: Ditto.
* gcc.target/riscv/rvv/base/user-1.c: Ditto.
* gcc.target/riscv/rvv/base/user-2.c: Ditto.
* gcc.target/riscv/rvv/base/user-3.c: Ditto.
* gcc.target/riscv/rvv/base/user-4.c: Ditto.
* gcc.target/riscv/rvv/base/user-5.c: Ditto.
* gcc.target/riscv/rvv/base/user-6.c: Ditto.
* gcc.target/riscv/rvv/base/vread_csr.c: Ditto.
* gcc.target/riscv/rvv/base/vwrite_csr.c: Ditto.
---
 gcc/config/riscv/riscv-c.cc  | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c   | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/pragma-2.c   | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/pragma-3.c   | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/user-1.c | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/user-2.c | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/user-3.c | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/user-4.c | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/user-5.c | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/user-6.c | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c | 2 +-
 12 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index cac0043d680..78f6eacb068 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -190,4 +190,4 @@ void
 riscv_register_pragmas (void)
 {
   c_register_pragma ("riscv", "intrinsic", riscv_pragma_intrinsic);
-}
\ No newline at end of file
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c
index 79b1159d9e7..3d81b179235 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c
@@ -1,4 +1,4 @@
 /* { dg-do compile } */
 /* { dg-options "-O3 -march=rv32gc -mabi=ilp32d" } */
 
-#pragma riscv intrinsic "vector" /* { dg-error {#pragma riscv intrinsic' 
option 'vector' needs 'V' extension enabled} } */
\ No newline at end of file
+#pragma riscv intrinsic "vector" /* { dg-error {#pragma riscv intrinsic' 
option 'vector' needs 'V' extension enabled} } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-2.c
index fa790b1f4e6..fd2aa3066cd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-2.c
@@ -1,4 +1,4 @@
 /* { dg-do compile } */
 /* { dg-skip-if "test rvv intrinsic" { *-*-* } { "*" } { "-march=rv*v*" } } */
 
-#pragma riscv intrinsic "vector"
\ No newline at end of file
+#pragma riscv intrinsic "vector"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-3.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-3.c
index 86da678adfa..96a0e051a29 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-3.c
@@ -1,4 +1,4 @@
 /* { dg-do compile } */
 /* { dg-skip-if "test rvv intrinsic" { *-*-* } { "*" } { "-march=rv*v*" } } */
 
-#pragma riscv intrinsic "report-error" /* { dg-error {unknown '#pragma riscv 
intrinsic' option 'report-error'} } */
\ No newline at end of file
+#pragma riscv intrinsic "report-error" /* { dg-error {unknown '#pragma riscv 
intrinsic' option 'report-error'} } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/user-1.c
index 299e3934a57..fa1f0f3d4d2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-1.c
@@ -62,4 +62,4 @@ void foo61 () {vfloat32m8_t t;}
 void foo62 () {vfloat64m1_t t;}
 void foo63 () {vfloat64m2_t t;}
 void foo64 () {vfloat64m4_t t;}
-void foo65 () {vfloat64m8_t t;}
\ No newline at end of file
+void foo65 () {vfloat64m8_t t;}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/user-2.c
index 2a88467d218..92f4ee02d20 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-2.c
@@ -62,4 +62,4 @@ void foo61 () {vfloat32m8_t t;} /* { dg-error {unknown type 
name 'vfloat32m8_t'}
 void foo62 () {vfloat64m1_t t;} /* { dg-error {unknown type name 
'vfloat64m1_t'} } */
 void foo63 () {vfloat64m2_t t;} /* { dg-error {unknown type name 
'vfloat64m2_t'} } */
 void foo64 () {vfloat64m4_t t;} /* { dg-error {unknown type name 
'vfloat64m4_t'} } */
-void foo65 () {vfloat64m8_t t;} /* { dg-error {unknown type name 
'vfloat64m8_t'} } */
\ No newline at end of file
+void foo65 () {vfloat64m8_t t;} /* { dg-error {unknown type name 
'vfloat64m8_t'} } */
diff --git a

[committed] RISC-V: Adjust testcase for rvv/base/user-1.c

[Kito Cheng]

The -march option check isn't precise enough, -march=rv*v* also mach any
zve extensions.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/user-1.c: Add dg-options and drop
dg-skip-if.

Reported-by: Christoph Müllner 
Tested-by: Christoph Müllner 
Reviewed-by: Ju-Zhe Zhong 
---
 gcc/testsuite/gcc.target/riscv/rvv/base/user-1.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/user-1.c
index fa1f0f3d4d2..00fb73f220f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-skip-if "test rvv intrinsic" { *-*-* } { "*" } { "-march=rv*v*" } } */
+/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */
 
 #include "riscv_vector.h"
 
-- 
2.37.2

[committed] RISC-V: Add riscv_vector.h wrapper in testsuite to prevent pull in stdint.h from C library

[Kito Cheng]

For RISC-V linux/glibc toolchain will got header file not found when including
stdint.h if multilib is not enabled, it because some header file will
try to include gnu/stubs-.h from the system, however it only
generated when multilib enabled.

In order to prevent that, we introduce a wrapper for riscv_vector.h,
include stdint-gcc.h rather than the default stdint.h.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/riscv_vector.h: New.

Reported-by: Christoph Müllner 
Tested-by: Christoph Müllner 
Reviewed-by: Ju-Zhe Zhong 
---
 .../gcc.target/riscv/rvv/base/riscv_vector.h  | 11 +++
 1 file changed, 11 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/riscv_vector.h

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/riscv_vector.h 
b/gcc/testsuite/gcc.target/riscv/rvv/base/riscv_vector.h
new file mode 100644
index 000..fbb4858fc86
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/riscv_vector.h
@@ -0,0 +1,11 @@
+/* Wrapper of riscv_vector.h, prevent riscv_vector.h including stdint.h from
+   C library, that might cause problem on testing RV32 related testcase when
+   we disable multilib.  */
+#ifndef _RISCV_VECTOR_WRAP_H
+
+#define _GCC_WRAP_STDINT_H
+#include "stdint-gcc.h"
+#include_next 
+#define _RISCV_VECTOR_WRAP_H
+
+#endif
-- 
2.37.2

[committed] RISC-V: Implement misc macro for vector extensions.

[Kito Cheng]

See also:
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/21

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (riscv_ext_flag_table):
Update flag name and mask name.
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Define
misc macro for vector extensions.
* config/riscv/riscv-opts.h (MASK_VECTOR_EEW_32): Rename to ...
(MASK_VECTOR_ELEN_32): ... this.
(MASK_VECTOR_EEW_64): Rename to ...
(MASK_VECTOR_ELEN_64): ... this.
(MASK_VECTOR_EEW_FP_32): Rename to ...
(MASK_VECTOR_ELEN_FP_32): ... this.
(MASK_VECTOR_EEW_FP_64): Rename to ...
(MASK_VECTOR_ELEN_FP_64): ... this.
(TARGET_VECTOR_ELEN_32): New.
(TARGET_VECTOR_ELEN_64): Ditto.
(TARGET_VECTOR_ELEN_FP_32): Ditto.
(TARGET_VECTOR_ELEN_FP_64): Ditto.
(TARGET_MIN_VLEN): Ditto.
* config/riscv/riscv.opt (riscv_vector_eew_flags): Rename to ...
(riscv_vector_elen_flags): ... this.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-13.c: New.
* gcc.target/riscv/arch-14.c: Ditto.
* gcc.target/riscv/arch-15.c: Ditto.
* gcc.target/riscv/predef-18.c: Ditto.
* gcc.target/riscv/predef-19.c: Ditto.
* gcc.target/riscv/predef-20.c: Ditto.
---
 gcc/common/config/riscv/riscv-common.cc| 16 ++--
 gcc/config/riscv/riscv-c.cc| 18 +
 gcc/config/riscv/riscv-opts.h  | 25 +-
 gcc/config/riscv/riscv.opt |  2 +-
 gcc/testsuite/gcc.target/riscv/arch-13.c   |  5 ++
 gcc/testsuite/gcc.target/riscv/arch-14.c   |  5 ++
 gcc/testsuite/gcc.target/riscv/arch-15.c   |  5 ++
 gcc/testsuite/gcc.target/riscv/predef-18.c | 84 +
 gcc/testsuite/gcc.target/riscv/predef-19.c | 88 ++
 gcc/testsuite/gcc.target/riscv/predef-20.c | 84 +
 10 files changed, 319 insertions(+), 13 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-13.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-14.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-15.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-18.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-19.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-20.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 48c4fabdc6b..1501242e296 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1116,16 +1116,16 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zve64f",   &gcc_options::x_target_flags, MASK_VECTOR},
   {"zve64d",   &gcc_options::x_target_flags, MASK_VECTOR},
 
-  /* We don't need to put complete EEW/EEW_FP info here, due to the
+  /* We don't need to put complete ELEN/ELEN_FP info here, due to the
  implication relation of vector extension.
- e.g. v -> zve64d ... zve32x, so v has set MASK_VECTOR_EEW_FP_64,
- MASK_VECTOR_EEW_FP_32, MASK_VECTOR_EEW_64 and MASK_VECTOR_EEW_32
+ e.g. v -> zve64d ... zve32x, so v has set MASK_VECTOR_ELEN_FP_64,
+ MASK_VECTOR_ELEN_FP_32, MASK_VECTOR_ELEN_64 and MASK_VECTOR_ELEN_32
  due to the extension implication.  */
-  {"zve32x",   &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_32},
-  {"zve32f",   &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_FP_32},
-  {"zve64x",   &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_64},
-  {"zve64f",   &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_FP_32},
-  {"zve64d",   &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_FP_64},
+  {"zve32x",   &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_32},
+  {"zve32f",   &gcc_options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_32},
+  {"zve64x",   &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_64},
+  {"zve64f",   &gcc_options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_32},
+  {"zve64d",   &gcc_options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_64},
 
   {"zvl32b",&gcc_options::x_riscv_zvl_flags, MASK_ZVL32B},
   {"zvl64b",&gcc_options::x_riscv_zvl_flags, MASK_ZVL64B},
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index 73c62f41274..eb7ef09297e 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -104,6 +104,24 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
 
 }
 
+  if (TARGET_MIN_VLEN != 0)
+builtin_define_with_int_value ("__riscv_v_min_vlen", TARGET_MIN_VLEN);
+
+  if (TARGET_VECTOR_ELEN_64)
+builtin_define_with_int_value ("__riscv_v_elen", 64);
+  else if (TARGET_VECTOR_ELEN_32)
+builtin_define_with_int_value ("__riscv_v_elen", 32);
+
+  if (TARGET_VECTOR_ELEN_FP_64)
+builtin_define_with_int_value ("__riscv_v_elen_fp", 64);
+  else if (TARGET_VECTOR_ELEN_FP_32)
+builtin_define_with_int_value ("__riscv_v_elen_fp", 32);
+  else if (TARGET_MIN_VLEN != 0)
+builtin_define_wit

Re: [PATCH] RISC-V: Implement ZTSO extension.

[Kito Cheng]

Hi Palmer:

I guess the problem is binutils isn't included and it's too close to the
GCC release, and binutils will report errors if it has any unsupported
extensions.

Most distro will use GCC 12 + binutils 2.38 or GCC 11 + binutils 2.38, so
either combination doesn't work for march string with ztso.

So that's why I am not intending to include that at this moment, but maybe
we could include that first and it'll work once binutils 2.39 released,
then we can have GCC 12 + binutils 2.39 in the next few months.

Anyway, I think I am fine with that, and I'll ping Nelson for the binutils
part.

On Tue, Mar 22, 2022 at 9:13 AM Palmer Dabbelt  wrote:

> On Thu, 17 Mar 2022 23:52:04 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
> > Hi Shi-Hua:
> >
> > Thanks, this patch is LGTM, but I would defer that until stage 1,
> > because the binutils part isn't merget yet.
>
> IMO we should at least have a __riscv_ztso define, and ideally have the
> relevent builtins ported (atomics, fences, etc) as well.  Otherwise this
> is really just setting a bit that makes binaries incompatible without
> providing any real benefit.  That'll also let us work through how these
> mappings should be implemented, so we don't end up with issues like we
> did with WMO.
>
> >
> > On Tue, Mar 15, 2022 at 5:10 PM  wrote:
> >>
> >> From: LiaoShihua 
> >>
> >>   ZTSO is the extension of tatol store order model.
> >>   This extension adds no new instructions to the ISA, and you can
> use it with arch "ztso".
> >>   If you use it, TSO flag will be generate in the ELF header.
> >>
> >> gcc/ChangeLog:
> >>
> >> * common/config/riscv/riscv-common.cc: define new arch.
> >> * config/riscv/riscv-opts.h (MASK_ZTSO): Ditto.
> >> (TARGET_ZTSO):Ditto.
> >> * config/riscv/riscv.opt:Ditto.
> >>
> >> ---
> >>  gcc/common/config/riscv/riscv-common.cc | 4 +++-
> >>  gcc/config/riscv/riscv-opts.h   | 3 +++
> >>  gcc/config/riscv/riscv.opt  | 3 +++
> >>  3 files changed, 9 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/gcc/common/config/riscv/riscv-common.cc
> b/gcc/common/config/riscv/riscv-common.cc
> >> index a904893b9ed..f4730b991d7 100644
> >> --- a/gcc/common/config/riscv/riscv-common.cc
> >> +++ b/gcc/common/config/riscv/riscv-common.cc
> >> @@ -185,6 +185,8 @@ static const struct riscv_ext_version
> riscv_ext_version_table[] =
> >>{"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0},
> >>{"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0},
> >>
> >> +  {"ztso", ISA_SPEC_CLASS_NONE, 0, 1},
> >> +
> >>/* Terminate the list.  */
> >>{NULL, ISA_SPEC_CLASS_NONE, 0, 0}
> >>  };
> >> @@ -1080,7 +1082,7 @@ static const riscv_ext_flag_table_t
> riscv_ext_flag_table[] =
> >>{"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B},
> >>{"zvl65536b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL65536B},
> >>
> >> -
> >> +  {"ztso", &gcc_options::x_riscv_ztso_subext, MASK_ZTSO},
> >>{NULL, NULL, 0}
> >>  };
> >>
> >> diff --git a/gcc/config/riscv/riscv-opts.h
> b/gcc/config/riscv/riscv-opts.h
> >> index 929e4e3a7c5..9cb5f2a550a 100644
> >> --- a/gcc/config/riscv/riscv-opts.h
> >> +++ b/gcc/config/riscv/riscv-opts.h
> >> @@ -136,4 +136,7 @@ enum stack_protector_guard {
> >>  #define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0)
> >>  #define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0)
> >>
> >> +#define MASK_ZTSO(1 <<  0)
> >> +#define TARGET_ZTSO((riscv_ztso_subext & MASK_ZTSO) != 0)
> >> +
> >>  #endif /* ! GCC_RISCV_OPTS_H */
> >> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> >> index 9fffc08220d..6128bfa31dc 100644
> >> --- a/gcc/config/riscv/riscv.opt
> >> +++ b/gcc/config/riscv/riscv.opt
> >> @@ -209,6 +209,9 @@ int riscv_vector_eew_flags
> >>  TargetVariable
> >>  int riscv_zvl_flags
> >>
> >> +TargetVariable
> >> +int riscv_ztso_subext
> >> +
> >>  Enum
> >>  Name(isa_spec_class) Type(enum riscv_isa_spec_class)
> >>  Supported ISA specs (for use with the -misa-spec= option):
> >> --
> >> 2.31.1.windows.1
> >>
>

[committed] RISC-V: Sync arch-canonicalize and riscv-common.cc

[Kito Cheng]

Currently we are sync that manually, but I guess we should re-implement
arch-canonicalize in C++, so that we could reuse the stuffs from
riscv-common.cc.

gcc/ChangeLog:

* config/riscv/arch-canonicalize: Add TODO item.
(IMPLIED_EXT): Sync.
(arch_canonicalize): Checking until no change.
---
 gcc/config/riscv/arch-canonicalize | 58 +++---
 1 file changed, 37 insertions(+), 21 deletions(-)

diff --git a/gcc/config/riscv/arch-canonicalize 
b/gcc/config/riscv/arch-canonicalize
index 49a6204b9cb..73589af608e 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -20,6 +20,9 @@
 # along with GCC; see the file COPYING3.  If not see
 # .
 
+# TODO: Extract riscv_subset_t from riscv-common.cc and make it can be compiled
+#   standalone to replace this script, that also prevents us implementing
+#   that twice and keep sync again and again.
 
 from __future__ import print_function
 import sys
@@ -35,21 +38,30 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x']
 # IMPLIED_EXT(ext) -> implied extension list.
 #
 IMPLIED_EXT = {
-  "d" : ["f"],
-  "zk" : ["zkn"],
-  "zk" : ["zkr"],
-  "zk" : ["zkt"],
-  "zkn" : ["zbkb"],
-  "zkn" : ["zbkc"],
-  "zkn" : ["zbkx"],
-  "zkn" : ["zkne"],
-  "zkn" : ["zknd"],
-  "zkn" : ["zknh"],
-  "zks" : ["zbkb"],
-  "zks" : ["zbkc"],
-  "zks" : ["zbkx"],
-  "zks" : ["zksed"],
-  "zks" : ["zksh"],
+  "d" : ["f", "zicsr"],
+  "f" : ["zicsr"],
+  "zk" : ["zkn", "zkr", "zkt"],
+  "zkn" : ["zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"],
+  "zks" : ["zbkb", "zbkc", "zbkx", "zksed", "zksh"],
+
+  "v" : ["zvl128b", "zve64d"],
+  "zve32x" : ["zvl32b"],
+  "zve64x" : ["zve32x", "zvl64b"],
+  "zve32f" : ["f", "zve32x"],
+  "zve64f" : ["f", "zve32f", "zve64x"],
+  "zve64d" : ["d", "zve64f"],
+
+  "zvl64b" : ["zvl32b"],
+  "zvl128b" : ["zvl64b"],
+  "zvl256b" : ["zvl128b"],
+  "zvl512b" : ["zvl256b"],
+  "zvl1024b" : ["zvl512b"],
+  "zvl2048b" : ["zvl1024b"],
+  "zvl4096b" : ["zvl2048b"],
+  "zvl8192b" : ["zvl4096b"],
+  "zvl16384b" : ["zvl8192b"],
+  "zvl32768b" : ["zvl16384b"],
+  "zvl65536b" : ["zvl32768b"],
 }
 
 def arch_canonicalize(arch):
@@ -77,12 +89,16 @@ def arch_canonicalize(arch):
   #
   # Handle implied extensions.
   #
-  for ext in std_exts + long_exts:
-if ext in IMPLIED_EXT:
-  implied_exts = IMPLIED_EXT[ext]
-  for implied_ext in implied_exts:
-if implied_ext not in std_exts + long_exts:
-  long_exts.append(implied_ext)
+  any_change = True
+  while any_change:
+any_change = False
+for ext in std_exts + long_exts:
+  if ext in IMPLIED_EXT:
+implied_exts = IMPLIED_EXT[ext]
+for implied_ext in implied_exts:
+  if implied_ext not in std_exts + long_exts:
+long_exts.append(implied_ext)
+any_change = True
 
   # Single letter extension might appear in the long_exts list,
   # becasue we just append extensions list to the arch string.
-- 
2.34.0

[committed] RISC-V: Support -misa-spec for arch-canonicalize and multilib-generator. [PR104853]

[Kito Cheng]

We migrate the default ISA spec version from 2.2 to 20191213, but those scripts
aren't updated at the same time, this patch is making both scripts support
different ISA spec versions.

gcc/ChangeLog:

PR target/104853
* config.gcc: Pass -misa-spec to arch-canonicalize and
multilib-generator.
* config/riscv/arch-canonicalize: Adding -misa-spec option.
(SUPPORTED_ISA_SPEC): New.
(arch_canonicalize): New argument `isa_spec`.
Handle multiple ISA spec versions.
* config/riscv/multilib-generator: Adding -misa-spec option.
---
 gcc/config.gcc  |  3 ++-
 gcc/config/riscv/arch-canonicalize  | 32 -
 gcc/config/riscv/multilib-generator | 14 +
 3 files changed, 39 insertions(+), 10 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 5382788e267..48a5bbcf787 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4717,7 +4717,7 @@ case "${target}" in
esac
PYTHON=`which python || which python3 || which python2`
if test "x${PYTHON}" != x; then
-   with_arch=`${PYTHON} 
${srcdir}/config/riscv/arch-canonicalize ${with_arch}`
+   with_arch=`${PYTHON} 
${srcdir}/config/riscv/arch-canonicalize -misa-spec=${with_isa_spec} 
${with_arch}`
fi
tm_defines="${tm_defines} 
TARGET_RISCV_DEFAULT_ARCH=${with_arch}"
 
@@ -4766,6 +4766,7 @@ case "${target}" in
case "${target}" in
riscv*-*-elf*)
if ${srcdir}/config/riscv/multilib-generator \
+   -misa-spec=${with_isa_spec} \
`echo ${with_multilib_generator} | sed 
's/;/ /g'`\
> t-multilib-config;
then
diff --git a/gcc/config/riscv/arch-canonicalize 
b/gcc/config/riscv/arch-canonicalize
index 73589af608e..f36a2ca4593 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -26,11 +26,12 @@
 
 from __future__ import print_function
 import sys
+import argparse
 import collections
 import itertools
 from functools import reduce
 
-
+SUPPORTED_ISA_SPEC = ["2.2", "20190608", "20191213"]
 CANONICAL_ORDER = "imafdgqlcbjktpvn"
 LONG_EXT_PREFIXES = ['z', 's', 'h', 'x']
 
@@ -64,12 +65,16 @@ IMPLIED_EXT = {
   "zvl65536b" : ["zvl32768b"],
 }
 
-def arch_canonicalize(arch):
+def arch_canonicalize(arch, isa_spec):
   # TODO: Support extension version.
+  is_isa_spec_2p2 = isa_spec == '2.2'
   new_arch = ""
+  extra_long_ext = []
   if arch[:5] in ['rv32e', 'rv32i', 'rv32g', 'rv64i', 'rv64g']:
-# TODO: We should expand g to imad_zifencei once we support newer spec.
 new_arch = arch[:5].replace("g", "imafd")
+if arch[:5] in ['rv32g', 'rv64g']:
+  if not is_isa_spec_2p2:
+extra_long_ext = ['zicsr', 'zifencei']
   else:
 raise Exception("Unexpected arch: `%s`" % arch[:5])
 
@@ -86,6 +91,8 @@ def arch_canonicalize(arch):
 long_exts = []
 std_exts = list(arch[5:])
 
+  long_exts += extra_long_ext
+
   #
   # Handle implied extensions.
   #
@@ -96,6 +103,9 @@ def arch_canonicalize(arch):
   if ext in IMPLIED_EXT:
 implied_exts = IMPLIED_EXT[ext]
 for implied_ext in implied_exts:
+  if implied_ext == 'zicsr' and is_isa_spec_2p2:
+  continue
+
   if implied_ext not in std_exts + long_exts:
 long_exts.append(implied_ext)
 any_change = True
@@ -115,6 +125,9 @@ def arch_canonicalize(arch):
 return (exts.startswith("x"), exts.startswith("zxm"),
 LONG_EXT_PREFIXES.index(exts[0]), canonical_sort, exts[1:])
 
+  # Removing duplicates.
+  long_exts = list(set(long_exts))
+
   # Multi-letter extension must be in lexicographic order.
   long_exts = list(sorted(filter(lambda x:len(x) != 1, long_exts),
   key=longext_sort))
@@ -134,11 +147,20 @@ def arch_canonicalize(arch):
   # Concat rest of the multi-char extensions.
   if long_exts:
 new_arch += "_" + "_".join(long_exts)
+
   return new_arch
 
 if len(sys.argv) < 2:
   print ("Usage: %s  [*]" % sys.argv)
   sys.exit(1)
 
-for arg in sys.argv[1:]:
-  print (arch_canonicalize(arg))
+parser = argparse.ArgumentParser()
+parser.add_argument('-misa-spec', type=str,
+default='20191213',
+choices=SUPPORTED_ISA_SPEC)
+parser.add_argument('arch_strs', nargs=argparse.REMAINDER)
+
+args = parser.parse_args()
+
+for arch in args.arch_strs:
+  print (arch_canonicalize(arch, args.misa_spec))
diff --git a/gcc/config/riscv/multilib-generator 
b/gcc/config/riscv/multilib-generator
index 1ea2fb25566..36698d48f56 100755
--- a/gcc/config/riscv/multilib-generator
+++ b/gcc/config/riscv/multilib-generator
@@ -46,16 +46,18 @@ import argparse
 # TODO: Add test for this script.
 #
 
+SUPPORTED_ISA_S

[PATCH] RISC-V: Handle different sigcontext struct layout.

[Kito Cheng]

RISC-V glibc intend to removed its own `sigcontext.h`[1] and use the linux
kernel's one, however the struct layout is slightly different between those two
version, fortunately they have identical layout, so we just need a
magical way to detect which one we are used.

libgcc/ChangeLog:

* config/riscv/linux-unwind.h (SIGCONTEXT_PC): New.
(riscv_fallback_frame_state): Use SIGCONTEXT_PC rather than
sc->gregs[i].

[1] https://sourceware.org/pipermail/libc-alpha/2022-January/135417.html
---
 libgcc/config/riscv/linux-unwind.h | 22 --
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/libgcc/config/riscv/linux-unwind.h 
b/libgcc/config/riscv/linux-unwind.h
index c86df2f85bc..4919facb36b 100644
--- a/libgcc/config/riscv/linux-unwind.h
+++ b/libgcc/config/riscv/linux-unwind.h
@@ -30,6 +30,16 @@
 
 #define MD_FALLBACK_FRAME_STATE_FOR riscv_fallback_frame_state
 
+/* RISC-V Glibc has removed its own sigcontext.h and use the linux kernel's
+   one, however the struct layout is little different between those two
+   version, fortunately they have identical layout, so we just need a
+   magical way to detect which one we are used.  */
+#ifdef _ASM_RISCV_SIGCONTEXT_H
+#define SIGCONTEXT_PC(SC) (SC)->sc_regs.pc
+#else
+#define SIGCONTEXT_PC(SC) (SC)->gregs[0]
+#endif
+
 static _Unwind_Reason_Code
 riscv_fallback_frame_state (struct _Unwind_Context *context,
_Unwind_FrameState * fs)
@@ -50,6 +60,8 @@ riscv_fallback_frame_state (struct _Unwind_Context *context,
   uint16_t *pc = context->ra;
   struct sigcontext *sc;
   int i;
+  /* Get regsister offest from register size.  */
+  _Unwind_Ptr reg_offset = __riscv_xlen / 8;
 
   /* A signal frame will have a return address pointing to
  __default_sa_restorer. This code is hardwired as:
@@ -73,17 +85,23 @@ riscv_fallback_frame_state (struct _Unwind_Context *context,
 
   for (i = 0; i < 32; i++)
 {
+  /* Restore all registers value from kernel structures.
+The corresponding bits in the Linux kernel are in
+arch/riscv/include/asm/ptrace.h.  */
   fs->regs.reg[i].how = REG_SAVED_OFFSET;
-  fs->regs.reg[i].loc.offset = (_Unwind_Ptr) &sc->gregs[i] - new_cfa;
+  fs->regs.reg[i].loc.offset
+   = (_Unwind_Ptr) &SIGCONTEXT_PC (sc) + (i * reg_offset) - new_cfa;
 }
 
   fs->signal_frame = 1;
   fs->retaddr_column = __LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__;
   fs->regs.reg[fs->retaddr_column].how = REG_SAVED_VAL_OFFSET;
   fs->regs.reg[fs->retaddr_column].loc.offset =
-(_Unwind_Ptr) sc->gregs[0] - new_cfa;
+(_Unwind_Ptr) SIGCONTEXT_PC (sc) - new_cfa;
 
   return _URC_NO_REASON;
 }
 
+#undef SIGCONTEXT_PC
+
 #endif
-- 
2.34.0

[committed] RISC-V: Fix testcase after bump isa spec version

[Kito Cheng]

Extension version might be different among different ISA spec version,
add explicitly isa-spec version to prevent that might fail when build
GCC with different default ISA version.

gcc/testsuite/ChangeLog

* gcc.target/riscv/attribute-19.c: Add -misa-spec=2.2
---
 gcc/testsuite/gcc.target/riscv/attribute-19.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/riscv/attribute-19.c 
b/gcc/testsuite/gcc.target/riscv/attribute-19.c
index 18f68d98561..562f8089361 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-19.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-19.c
@@ -1,4 +1,4 @@
 /* { dg-do compile } */
-/* { dg-options "-mriscv-attribute -march=rv64imp0p9 -mabi=lp64" } */
+/* { dg-options "-mriscv-attribute -march=rv64imp0p9 -mabi=lp64 
-misa-spec=2.2" } */
 int foo() {}
 /* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_p0p9\"" } } */
-- 
2.34.0

[committed] RISC-V: Do not emit zcisr and zifencei if i-ext is 2.0

[Kito Cheng]

I-ext 2.0 already included zicsr and zifencei, skip that prevent
confusing binutils.

gcc/ChangeLog

* common/config/riscv/riscv-common.cc (riscv_subset_list::to_string):
Skip zicsr and zifencei if I-ext is 2.0.
---
 gcc/common/config/riscv/riscv-common.cc | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 25f56707d94..a904893b9ed 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -488,6 +488,7 @@ riscv_subset_list::to_string (bool version_p) const
 
   bool skip_zifencei = false;
   bool skip_zicsr = false;
+  bool i2p0 = false;
 
   /* For RISC-V ISA version 2.2 or earlier version, zicsr and zifencei is
  included in the base ISA.  */
@@ -497,6 +498,13 @@ riscv_subset_list::to_string (bool version_p) const
   skip_zicsr = true;
 }
 
+  for (subset = m_head; subset != NULL; subset = subset->next)
+if (subset->name == "i")
+  {
+   i2p0 = subset->major_version == 2 && subset->minor_version == 0;
+   break;
+  }
+
 #ifndef HAVE_AS_MISA_SPEC
   /* Skip since older binutils doesn't recognize zicsr.  */
   skip_zicsr = true;
@@ -509,10 +517,12 @@ riscv_subset_list::to_string (bool version_p) const
 
   for (subset = m_head; subset != NULL; subset = subset->next)
 {
-  if (subset->implied_p && skip_zifencei && subset->name == "zifencei")
+  if (((subset->implied_p && skip_zifencei) || i2p0) &&
+ subset->name == "zifencei")
continue;
 
-  if (subset->implied_p && skip_zicsr && subset->name == "zicsr")
+  if (((subset->implied_p && skip_zicsr) || i2p0) &&
+ subset->name == "zicsr")
continue;
 
   /* For !version_p, we only separate extension with underline for
-- 
2.34.0

[PATCH] RISC-V: Always pass -misa-spec to assembler [PR104219]

[Kito Cheng]

Add -misa-spec to OPTION_DEFAULT_SPECS to make sure -misa-spec will
always pass that into assembler, that prevent GCC and binutils using
different way to interpret the ISA string.

gcc/ChangeLog:

PR target/104219
* config.gcc (riscv*-*-*): Normalize the with_isa_spec value.
(all_defaults): Add isa_spec.
* config/riscv/riscv.h (OPTION_DEFAULT_SPECS): Add isa_spec.
---
 gcc/config.gcc   | 4 +++-
 gcc/config/riscv/riscv.h | 2 ++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 90aec3f8f3f..0bb8c63a46e 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4643,12 +4643,14 @@ case "${target}" in
case "${with_isa_spec}" in
""|default|20191213|201912)
tm_defines="${tm_defines} 
TARGET_DEFAULT_ISA_SPEC=ISA_SPEC_CLASS_20191213"
+   with_isa_spec=20191213
;;
2.2)
tm_defines="${tm_defines} 
TARGET_DEFAULT_ISA_SPEC=ISA_SPEC_CLASS_2P2"
;;
20190608 | 201906)
tm_defines="${tm_defines} 
TARGET_DEFAULT_ISA_SPEC=ISA_SPEC_CLASS_20190608"
+   with_isa_spec=20190608
;;
*)
echo "--with-isa-spec only accept 2.2, 20191213, 
201912, 20190608 or 201906" 1>&2
@@ -5430,7 +5432,7 @@ case ${target} in
 esac
 
 t=
-all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 
schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls 
lxc1-sxc1 madd4"
+all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 
schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls 
lxc1-sxc1 madd4 isa_spec"
 for option in $all_defaults
 do
eval "val=\$with_"`echo $option | sed s/-/_/g`
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 695668424c3..8a4d2cf7f85 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -60,6 +60,7 @@ extern const char *riscv_default_mtune (int argc, const char 
**argv);
--with-arch is ignored if -march or -mcpu is specified.
--with-abi is ignored if -mabi is specified.
--with-tune is ignored if -mtune or -mcpu is specified.
+   --with-isa-spec is ignored if -misa-spec is specified.
 
But using default -march/-mtune value if -mcpu don't have valid option.  */
 #define OPTION_DEFAULT_SPECS \
@@ -70,6 +71,7 @@ extern const char *riscv_default_mtune (int argc, const char 
**argv);
   "  %{!mcpu=*:-march=%(VALUE)}"   \
   "  %{mcpu=*:%:riscv_expand_arch_from_cpu(%* %(VALUE))}}" },  \
   {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
+  {"isa_spec", "%{!misa-spec=*:-misa-spec=%(VALUE)}" }, \
 
 #ifdef IN_LIBGCC2
 #undef TARGET_64BIT
-- 
2.34.0

[committed] RISC-V: Fix detection of zifencei support for binutils

[Kito Cheng]

- binutils will complain version info is not found if default ISA spec
  is 2.2 for binutils.

Error: cannot find default versions of the ISA extension `zifencei'

gcc/ChangeLog:

* configure.ac: Fix detection for zifencei support.
* configure: Regenerate.
---
 gcc/configure| 2 +-
 gcc/configure.ac | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/configure b/gcc/configure
index bd4d4721868..258b17a226e 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -28746,7 +28746,7 @@ else
   gcc_cv_as_riscv_march_zifencei=no
   if test x$gcc_cv_as != x; then
 $as_echo '' > conftest.s
-if { ac_try='$gcc_cv_as $gcc_cv_as_flags -march=rv32i_zifencei -o 
conftest.o conftest.s >&5'
+if { ac_try='$gcc_cv_as $gcc_cv_as_flags -march=rv32i_zifencei2p0 -o 
conftest.o conftest.s >&5'
   { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
   (eval $ac_try) 2>&5
   ac_status=$?
diff --git a/gcc/configure.ac b/gcc/configure.ac
index 1171c946e6e..06750cee977 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -5286,7 +5286,7 @@ configured with --enable-newlib-nano-formatted-io.])
 [Define if the assembler understands -misa-spec=.])])
 gcc_GAS_CHECK_FEATURE([-march=rv32i_zifencei support],
   gcc_cv_as_riscv_march_zifencei,
-  [-march=rv32i_zifencei],,,
+  [-march=rv32i_zifencei2p0],,,
   [AC_DEFINE(HAVE_AS_MARCH_ZIFENCEI, 1,
 [Define if the assembler understands -march=rv*_zifencei.])])
 ;;
-- 
2.34.0