[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 4
https://gcc.gnu.org/g:2372ebbb3417b446dfb76bd6390f3a510a357934
commit 2372ebbb3417b446dfb76bd6390f3a510a357934
Author: Pan Li
Date: Sun Jun 30 16:48:19 2024 +0800
RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 4
This patch would like to add test cases for the unsigned scalar
.SAT_ADD IMM form 4. Aka:
Form 4:
#define DEF_SAT_U_ADD_IMM_FMT_4(T)\
T __attribute__((noinline)) \
sat_u_add_imm_##T##_fmt_4 (T x) \
{ \
T ret; \
return __builtin_add_overflow (x, 9, &ret) == 0 ? ret : -1; \
}
DEF_SAT_U_ADD_IMM_FMT_4(uint64_t)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper test macro.
* gcc.target/riscv/sat_u_add_imm-13.c: New test.
* gcc.target/riscv/sat_u_add_imm-14.c: New test.
* gcc.target/riscv/sat_u_add_imm-15.c: New test.
* gcc.target/riscv/sat_u_add_imm-16.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-13.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-14.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-15.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-16.c: New test.
Signed-off-by: Pan Li
(cherry picked from commit 7a65ab6b5f38d3018ffd456f278a9fd885487a27)
Diff:
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 11 ++
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-13.c | 19 +
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-14.c | 21 ++
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-15.c | 18 +
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-16.c | 17
.../gcc.target/riscv/sat_u_add_imm-run-13.c| 46 ++
.../gcc.target/riscv/sat_u_add_imm-run-14.c| 46 ++
.../gcc.target/riscv/sat_u_add_imm-run-15.c| 46 ++
.../gcc.target/riscv/sat_u_add_imm-run-16.c| 46 ++
9 files changed, 270 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 83b294db476..75442c94dc1 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -82,6 +82,14 @@ sat_u_add_imm##IMM##_##T##_fmt_3 (T x) \
return __builtin_add_overflow (x, IMM, &ret) ? -1 : ret; \
}
+#define DEF_SAT_U_ADD_IMM_FMT_4(T, IMM) \
+T __attribute__((noinline)) \
+sat_u_add_imm##IMM##_##T##_fmt_4 (T x) \
+{ \
+ T ret;\
+ return __builtin_add_overflow (x, IMM, &ret) == 0 ? ret : -1; \
+}
+
#define RUN_SAT_U_ADD_IMM_FMT_1(T, x, IMM, expect) \
if (sat_u_add_imm##IMM##_##T##_fmt_1(x) != expect) __builtin_abort ()
@@ -91,6 +99,9 @@ sat_u_add_imm##IMM##_##T##_fmt_3 (T x) \
#define RUN_SAT_U_ADD_IMM_FMT_3(T, x, IMM, expect) \
if (sat_u_add_imm##IMM##_##T##_fmt_3(x) != expect) __builtin_abort ()
+#define RUN_SAT_U_ADD_IMM_FMT_4(T, x, IMM, expect) \
+ if (sat_u_add_imm##IMM##_##T##_fmt_4(x) != expect) __builtin_abort ()
+
/**/
/* Saturation Sub (Unsigned and Signed)
*/
/**/
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-13.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-13.c
new file mode 100644
index 000..a3b2679233c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-13.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm9_uint8_t_fmt_4:
+** addi\s+[atx][0-9]+,\s*a0,\s*9
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_4(uint8_t, 9)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-14.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-14.c
new file mode 100644
index 000..968534b74da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-14.c
@@ -0,0 +1,21 @@
+/* { dg-do compile }
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix asm check failure for truncated after SAT_SUB
https://gcc.gnu.org/g:9de4cfd56a65e70bf5f4fa50ed2326a632befef4 commit 9de4cfd56a65e70bf5f4fa50ed2326a632befef4 Author: Pan Li Date: Wed Jul 3 13:17:16 2024 +0800 RISC-V: Fix asm check failure for truncated after SAT_SUB It seems that the asm check is incorrect for truncated after SAT_SUB, we should take the vx check for vssubu instead of vv check. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c: Update vssubu check from vv to vx. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c: Ditto. Signed-off-by: Pan Li (cherry picked from commit ab3e3d2f0564c2eb0640de3f4d0a50e1fcc8c318) Diff: --- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c index dd9e3999a29..1e380657d74 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c @@ -11,7 +11,7 @@ ** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma ** ... ** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+ ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma ** vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+ ** ... diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c index 738d1465a01..d7b8931f0ec 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c @@ -11,7 +11,7 @@ ** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma ** ... ** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+ ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma ** vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+ ** ... diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c index b008b21cf0c..edf42a1f776 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c @@ -11,7 +11,7 @@ ** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma ** ... ** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) -** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+ ** vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma ** vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+ ** ...
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add support for Zabha extension
https://gcc.gnu.org/g:0d3084a47182fc04b2cb1fdf4ce240074a953534 commit 0d3084a47182fc04b2cb1fdf4ce240074a953534 Author: Gianluca Guida Date: Tue Jul 2 18:05:14 2024 -0700 RISC-V: Add support for Zabha extension The Zabha extension adds support for subword Zaamo ops. Extension: https://github.com/riscv/riscv-zabha.git Ratification: https://jira.riscv.org/browse/RVS-1685 gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::to_string): Skip zabha when not supported by the assembler. * config.in: Regenerate. * config/riscv/arch-canonicalize: Make zabha imply zaamo. * config/riscv/iterators.md (amobh): Add iterator for amo byte/halfword. * config/riscv/riscv.opt: Add zabha. * config/riscv/sync.md (atomic_): Add subword atomic op pattern. (zabha_atomic_fetch_): Add subword atomic_fetch op pattern. (lrsc_atomic_fetch_): Prefer zabha over lrsc for subword atomic ops. (zabha_atomic_exchange): Add subword atomic exchange pattern. (lrsc_atomic_exchange): Prefer zabha over lrsc for subword atomic exchange ops. * configure: Regenerate. * configure.ac: Add zabha assembler check. * doc/sourcebuild.texi: Add zabha documentation. gcc/testsuite/ChangeLog: * lib/target-supports.exp: Add zabha testsuite infra support. * gcc.target/riscv/amo/inline-atomics-1.c: Remove zabha to continue to test the lr/sc subword patterns. * gcc.target/riscv/amo/inline-atomics-2.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c: Ditto. * gcc.target/riscv/amo/zabha-all-amo-ops-char-run.c: New test. * gcc.target/riscv/amo/zabha-all-amo-ops-short-run.c: New test. * gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c: New test. * gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c: New test. * gcc.target/riscv/amo/zabha-rvwmo-amo-add-char.c: New test. * gcc.target/riscv/amo/zabha-rvwmo-amo-add-short.c: New test. * gcc.target/riscv/amo/zabha-ztso-amo-add-char.c: New test. * gcc.target/riscv/amo/zabha-ztso-amo-add-short.c: New test. Co-Authored-By: Patrick O'Neill Signed-Off-By: Gianluca Guida Tested-by: Andrea Parri (cherry picked from commit 7b2b2e3d660edc8ef3a8cfbdfc2b0fd499459601) Diff: --- gcc/common/config/riscv/riscv-common.cc| 12 gcc/config.in | 6 ++ gcc/config/riscv/arch-canonicalize | 3 + gcc/config/riscv/iterators.md | 3 + gcc/config/riscv/riscv.opt | 2 + gcc/config/riscv/sync.md | 81 +- gcc/configure | 31 + gcc/configure.ac | 5 ++ gcc/doc/sourcebuild.texi | 12 +++- .../gcc.target/riscv/amo/inline-atomics-1.c| 1 + .../gcc.target/riscv/amo/inline-atomics-2.c| 1 + .../riscv/amo/zabha-all-amo-ops-char-run.c | 5 ++ .../riscv/amo/zabha-all-amo-ops-short-run.c| 5 ++ .../riscv/amo/zabha-rvwmo-all-amo-ops-char.c | 23 ++ .../riscv/amo/zabha-rvwmo-all-amo-ops-short.c | 23 ++ .../riscv/amo/zabha-rvwmo-amo-add-char.c | 57 +++ .../riscv/amo/zabha-rvwmo-amo-add-short.c | 57 +++ .../gcc.target/riscv/amo/zabha-ztso-amo-add-char.c | 57 +++ .../riscv/amo/zabha-ztso-amo-add-short.c | 57 +++ .../zalrsc-rvwmo-subword-amo-add-char-acq-rel.c| 1 + .../zalrsc-rvwmo-subword-amo-add-char-acquire.c| 1 + .../zalrsc-rvwmo-subword-amo-add-char-relaxed.c| 1 + .../zalrsc-rvwmo-subword-amo-add-char-release.c| 1 + .../zalrsc-rvwmo-subword-amo-add-char-seq-cst.c| 1 + .../amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c | 1 + .../
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1
https://gcc.gnu.org/g:8ab0fc4d6a5a5d458f74e7d58ead9f07aa3444fc
commit 8ab0fc4d6a5a5d458f74e7d58ead9f07aa3444fc
Author: Pan Li
Date: Sun Jun 30 16:03:41 2024 +0800
RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1
This patch would like to add test cases for the unsigned scalar
.SAT_ADD IMM form 1. Aka:
Form 1:
#define DEF_SAT_U_ADD_IMM_FMT_1(T) \
T __attribute__((noinline)) \
sat_u_add_imm_##T##_fmt_1 (T x) \
{\
return (T)(x + 9) >= x ? (x + 9) : -1; \
}
DEF_SAT_U_ADD_IMM_FMT_1(uint64_t)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper test macro.
* gcc.target/riscv/sat_u_add_imm-1.c: New test.
* gcc.target/riscv/sat_u_add_imm-2.c: New test.
* gcc.target/riscv/sat_u_add_imm-3.c: New test.
* gcc.target/riscv/sat_u_add_imm-4.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-1.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-2.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-3.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-4.c: New test.
Signed-off-by: Pan Li
(cherry picked from commit ed213b384fdca9375c3ec53c2a0eae134fb98612)
Diff:
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 10 +
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-1.c | 19 +
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-2.c | 21 ++
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-3.c | 18 +
gcc/testsuite/gcc.target/riscv/sat_u_add_imm-4.c | 17
.../gcc.target/riscv/sat_u_add_imm-run-1.c | 46 ++
.../gcc.target/riscv/sat_u_add_imm-run-2.c | 46 ++
.../gcc.target/riscv/sat_u_add_imm-run-3.c | 46 ++
.../gcc.target/riscv/sat_u_add_imm-run-4.c | 46 ++
9 files changed, 269 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 0c2e44af718..4ec4ec36cc1 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -60,6 +60,16 @@ sat_u_add_##T##_fmt_6 (T x, T y)\
#define RUN_SAT_U_ADD_FMT_5(T, x, y) sat_u_add_##T##_fmt_5(x, y)
#define RUN_SAT_U_ADD_FMT_6(T, x, y) sat_u_add_##T##_fmt_6(x, y)
+#define DEF_SAT_U_ADD_IMM_FMT_1(T, IMM) \
+T __attribute__((noinline)) \
+sat_u_add_imm##IMM##_##T##_fmt_1 (T x) \
+{\
+ return (T)(x + IMM) >= x ? (x + IMM) : -1; \
+}
+
+#define RUN_SAT_U_ADD_IMM_FMT_1(T, x, IMM, expect) \
+ if (sat_u_add_imm##IMM##_##T##_fmt_1(x) != expect) __builtin_abort ()
+
/**/
/* Saturation Sub (Unsigned and Signed)
*/
/**/
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-1.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-1.c
new file mode 100644
index 000..14e9b7595a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm9_uint8_t_fmt_1:
+** addi\s+[atx][0-9]+,\s*a0,\s*9
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_1(uint8_t, 9)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-2.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-2.c
new file mode 100644
index 000..c1a3c6ff21d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-2.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm3_uint16_t_fmt_1:
+** addi\s+[atx][0-9]+,\s*a0,\s*3
+** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_1(uint16_t, 3)
+
+/* { dg-final { scan-rtl-du
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Describe -march behavior for dependent extensions
https://gcc.gnu.org/g:db238f5ae70cb461f0f9d7309208c6b36616b547
commit db238f5ae70cb461f0f9d7309208c6b36616b547
Author: Palmer Dabbelt
Date: Tue Jul 2 18:20:39 2024 -0700
RISC-V: Describe -march behavior for dependent extensions
gcc/ChangeLog:
* doc/invoke.texi: Describe -march behavior for dependent
extensions on
RISC-V.
(cherry picked from commit 70f6bc39c4b0e147a816ad1dad583f944616c367)
Diff:
---
gcc/doc/invoke.texi | 4
1 file changed, 4 insertions(+)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 1663ddc2252..ede749f645a 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -30927,6 +30927,10 @@ If both @option{-march} and @option{-mcpu=} are not
specified, the default for
this argument is system dependent, users who want a specific architecture
extensions should specify one explicitly.
+When the RISC-V specifications define an extension as depending on other
+extensions, GCC will implicitly add the dependent extensions to the enabled
+extension set if they weren't added explicitly.
+
@opindex mcpu
@item -mcpu=@var{processor-string}
Use architecture of and optimize the output for the given processor, specified
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed][RISC-V] Fix test expectations after recent late-combine changes
https://gcc.gnu.org/g:cb9f4cb1077bf480b1bb766cde024207f406d69a
commit cb9f4cb1077bf480b1bb766cde024207f406d69a
Author: Jeff Law
Date: Thu Jul 4 09:25:20 2024 -0600
[committed][RISC-V] Fix test expectations after recent late-combine changes
With the recent DCE related adjustment to late-combine the
rvv/base/vcreate.c
test no longer has those undesirable vmvNr statements.
It's a bit unclear why this wasn't written as a scan-assembler-not and
xfailed
given the comment says we don't want to see vmvNr insructions. I must have
missed that during review.
This patch adjusts the test to expect no vmvNr statements and if they're
ever
re-introduced, we'll get a nice unexpected failure.
gcc/testsuite
* gcc.target/riscv/rvv/base/vcreate.c: Update expected output.
(cherry picked from commit b611f3969249967d7f098c6adfcf5f701192a2d0)
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c
index 01006de7c81..1c7c154637e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c
@@ -256,6 +256,6 @@ test_vcreate_v_i64m2x4 (vint64m2_t v0, vint64m2_t v1,
vint64m2_t v2,
}
// Ideally with O3, should find 0 instances of any vmvnr.v PR113913
-/* { dg-final { scan-assembler-times {vmv1r.v\s+v[0-9]+,\s*v[0-9]+} 72 } } */
-/* { dg-final { scan-assembler-times {vmv2r.v\s+v[0-9]+,\s*v[0-9]+} 36 } } */
-/* { dg-final { scan-assembler-times {vmv4r.v\s+v[0-9]+,\s*v[0-9]+} 16 } } */
+/* { dg-final { scan-assembler-not {vmv1r.v\s+v[0-9]+,\s*v[0-9]+} } } */
+/* { dg-final { scan-assembler-not {vmv2r.v\s+v[0-9]+,\s*v[0-9]+} } } */
+/* { dg-final { scan-assembler-not {vmv4r.v\s+v[0-9]+,\s*v[0-9]+} } } */
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed][v3][RISC-V] Handle bit manipulation of SImode values
https://gcc.gnu.org/g:49d192288ec101216cd22b0f701b04f6d99c3821
commit 49d192288ec101216cd22b0f701b04f6d99c3821
Author: Jeff Law
Date: Sat Jul 6 12:57:59 2024 -0600
[to-be-committed][v3][RISC-V] Handle bit manipulation of SImode values
Last patch in this round of bitmanip work... At least I think I'm going to
pause here and switch gears to other projects that need attention 🙂
This patch introduces the ability to generate bitmanip instructions for rv64
when operating on SI objects when we know something about the range of the
bit
position (due to masking of the position).
I've got note that the (7-pos % 8) bit position form was discovered by RAU
in
500.perl. I took that and expanded it to the simple (pos & mask) form as
well
as covering bset, binv and bclr.
As far as the implementation is concerned
This turns the recently added define_splits into define_insn_and_split
constructs. This allows combine to "see" enough RTL to realize a sign
extension is unnecessary. Otherwise we get undesirable sign extensions for
the
new testcases.
Second it adds new patterns for the logical operations. Two patterns for
IOR/XOR and two patterns for AND.
I think a key concept to keep in mind is that once we determine a Zbs
operation
is safe to perform on a SI value, we can rewrite the RTL in 64bit form. If
we
were ever to try and use range information at expand time for this stuff
(and
we probably should investigate that), that's the path I'd suggest.
This is notably cleaner than my original implementation which actually kept
the
more complex RTL form through final and emitted 2/3 instructions (mask the
bit
position, then the bset/bclr/binv).
Tested in my tester, but waiting for pre-commit CI to report back before
taking
further action.
gcc/
* config/riscv/bitmanip.md (bset splitters): Turn into
define_and_splits.
Don't depend on combine splitting the "andn with constant" form.
(bset, binv, bclr with masked bit position): New patterns.
gcc/testsuite
* gcc.target/riscv/binv-for-simode-1.c: New test.
* gcc.target/riscv/bset-for-simode-1.c: New test.
* gcc.target/riscv/bclr-for-simode-1.c: New test.
(cherry picked from commit 273f16a125c4fab664683376ae04a9a31e7d6a22)
Diff:
---
gcc/config/riscv/bitmanip.md | 135 ++---
gcc/testsuite/gcc.target/riscv/bclr-for-simode-1.c | 25
gcc/testsuite/gcc.target/riscv/binv-for-simode-1.c | 24
gcc/testsuite/gcc.target/riscv/bset-for-simode-1.c | 24
4 files changed, 192 insertions(+), 16 deletions(-)
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 3a47668397b..6b720992ca3 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -615,37 +615,140 @@
;; shift constant. With the limited range we know the SImode sign
;; bit is never set, thus we can treat this as zero extending and
;; generate the bsetdi_2 pattern.
-(define_split
- [(set (match_operand:DI 0 "register_operand")
+(define_insn_and_split ""
+ [(set (match_operand:DI 0 "register_operand" "=r")
(any_extend:DI
(ashift:SI (const_int 1)
(subreg:QI
- (and:DI (not:DI (match_operand:DI 1 "register_operand"))
+ (and:DI (not:DI (match_operand:DI 1 "register_operand"
"r"))
(match_operand 2 "const_int_operand")) 0
- (clobber (match_operand:DI 3 "register_operand"))]
+ (clobber (match_scratch:X 3 "=&r"))]
"TARGET_64BIT
&& TARGET_ZBS
&& (TARGET_ZBB || TARGET_ZBKB)
&& (INTVAL (operands[2]) & 0x1f) != 0x1f"
- [(set (match_dup 0) (and:DI (not:DI (match_dup 1)) (match_dup 2)))
-(set (match_dup 0) (zero_extend:DI (ashift:SI
- (const_int 1)
- (subreg:QI (match_dup 0) 0])
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 3) (match_dup 2))
+(set (match_dup 3) (and:DI (not:DI (match_dup 1)) (match_dup 3)))
+(set (match_dup 0) (zero_extend:DI
+(ashift:SI (const_int 1) (match_dup 4]
+ { operands[4] = gen_lowpart (QImode, operands[3]); }
+ [(set_attr "type" "bitmanip")])
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (any_extend:DI
+(define_insn_and_split ""
+ [(set (match_operand:DI 0 "register_operand" "=r")
+(any_extend:DI
(ashift:SI (const_int 1)
(subreg:QI
- (and:DI (match_operand:DI 1 "register_operand")
+ (and:DI (match_operand:DI 1 "register_operand" "r")
(match_operand 2 "const_int_operand")) 0]
"TARGET_64BIT
&& TARGET_ZBS
&& (INTVAL (operands[2]) & 0x1f) != 0x1f"
- [(set
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement .SAT_TRUNC for vector unsigned int
https://gcc.gnu.org/g:34f337a787ebcefc68b18734ae0ab72a1a8d0a22
commit 34f337a787ebcefc68b18734ae0ab72a1a8d0a22
Author: Pan Li
Date: Fri Jul 5 09:02:47 2024 +0800
RISC-V: Implement .SAT_TRUNC for vector unsigned int
This patch would like to implement the .SAT_TRUNC for the RISC-V
backend. With the help of the RVV Vector Narrowing Fixed-Point
Clip Instructions. The below SEW(S) are supported:
* e64 => e32
* e64 => e16
* e64 => e8
* e32 => e16
* e32 => e8
* e16 => e8
Take below example to see the changes to asm.
Form 1:
#define DEF_VEC_SAT_U_TRUNC_FMT_1(NT, WT) \
void __attribute__((noinline))\
vec_sat_u_trunc_##NT##_##WT##_fmt_1 (NT *out, WT *in, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
WT x = in[i]; \
bool overflow = x > (WT)(NT)(-1); \
out[i] = ((NT)x) | (NT)-overflow; \
} \
}
DEF_VEC_SAT_U_TRUNC_FMT_1 (uint32_t, uint64_t)
Before this patch:
.L3:
vsetvli a5,a2,e64,m1,ta,ma
vle64.v v1,0(a1)
vmsgtu.vvv0,v1,v2
vsetvli zero,zero,e32,mf2,ta,ma
vncvt.x.x.w v1,v1
vmerge.vim v1,v1,-1,v0
vse32.v v1,0(a0)
slli a4,a5,3
add a1,a1,a4
slli a4,a5,2
add a0,a0,a4
sub a2,a2,a5
bne a2,zero,.L3
After this patch:
.L3:
vsetvli a5,a2,e32,mf2,ta,ma
vle64.v v1,0(a1)
vnclipu.wi v1,v1,0
vse32.v v1,0(a0)
slli a4,a5,3
add a1,a1,a4
slli a4,a5,2
add a0,a0,a4
sub a2,a2,a5
bne a2,zero,.L3
Passed the rv64gcv fully regression tests.
gcc/ChangeLog:
* config/riscv/autovec.md (ustrunc2): Add
new pattern for double truncation.
(ustrunc2): Ditto but for quad truncation.
(ustrunc2): Ditto but for oct truncation.
* config/riscv/riscv-protos.h (expand_vec_double_ustrunc): Add
new func decl to expand double vec ustrunc.
(expand_vec_quad_ustrunc): Ditto but for quad.
(expand_vec_oct_ustrunc): Ditto but for oct.
* config/riscv/riscv-v.cc (expand_vec_double_ustrunc): Add new
func impl to expand vector double ustrunc.
(expand_vec_quad_ustrunc): Ditto but for quad.
(expand_vec_oct_ustrunc): Ditto but for oct.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
test macros.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_data.h: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c: New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-1.c: New
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-2.c: New
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-3.c: New
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-4.c: New
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-5.c: New
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-6.c: New
test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_unary_vv_run.h: New
test.
Signed-off-by: Pan Li
(cherry picked from commit dafd63d7c5cddce1e00803606e742d75927b1a1e)
Diff:
---
gcc/config/riscv/autovec.md| 35 ++
gcc/config/riscv/riscv-protos.h| 4 +
gcc/config/riscv/riscv-v.cc| 46 +++
.../riscv/rvv/autovec/binop/vec_sat_arith.h| 22 ++
.../riscv/rvv/autovec/unop/vec_sat_data.h | 394 +
.../riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c | 19 +
.../riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c | 21 ++
.../riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c | 23 ++
.../riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed][RISC-V][V3] DCE analysis for extension elimination
https://gcc.gnu.org/g:3837405f64cef75f61c383df6c57c9442e71402c commit 3837405f64cef75f61c383df6c57c9442e71402c Author: Jeff Law Date: Mon Jul 8 17:06:55 2024 -0600 [to-be-committed][RISC-V][V3] DCE analysis for extension elimination The pre-commit testing showed that making ext-dce only active at -O2 and above would require minor edits to the tests. In some cases we had specified -O1 in the test or specified no optimization level at all. Those need to be bumped to -O2. In one test we had one set of dg-options overriding another. The other approach that could have been taken would be to drop the -On argument, add an explicit -fext-dce and add dg-skip-if options. I originally thought that was going to be way to go, but the dg-skip-if aspect was going to get ugly as things like interaction between unrolling, peeling and -ftracer would have to be accounted for and would likely need semi-regular adjustment. Changes since V2: Testsuite changes to deal with pass only being enabled at -O2 or higher. -- Changes since V1: Check flag_ext_dce before running the new pass. I'd forgotten that I had removed that part of the gate to facilitate more testing. Turn flag_ext_dce on at -O2 and above. Adjust one of the riscv tests to explicitly avoid vectors Adjust a few aarch64 tests In tbz_2.c we remove an unnecessary extension which causes us to use "x" registers instead of "w" registers. In the pred_clobber tests we also remove an extension and that ultimately causes a reg->reg copy to change locations. -- This was actually ack'd late in the gcc-14 cycle, but I chose not to integrate it given how late we were in the cycle. The basic idea here is to track liveness of subobjects within a word and if we find an extension where the bits set aren't actually used, then we convert the extension into a subreg. The subreg typically simplifies away. I've seen this help a few routines in coremark, fix one bug in the testsuite (pr111384) and fix a couple internally reported bugs in Ventana. The original idea and code were from Joern; Jivan and I hacked it into usable shape. I've had this in my tester for ~8 months, so it's been through more build/test cycles than I care to contemplate and nearly every architecture we support. But just in case, I'm going to wait for it to spin through the pre-commit CI tester. I'll find my old ChangeLog before committing. gcc/ * Makefile.in (OBJS): Add ext-dce.o * common.opt (ext-dce): Document new option. * df-scan.cc (df_get_ext_block_use_set): Delete prototype and make extern. * df.h (df_get_exit_block_use_set): Prototype. * ext-dce.cc: New file/pass. * opts.cc (default_options_table): Handle ext-dce at -O2 or higher. * passes.def: Add ext-dce before combine. * tree-pass.h (make_pass_ext_dce): Prototype. gcc/testsuite * gcc.target/aarch64/sve/pred_clobber_1.c: Update expected output. * gcc.target/aarch64/sve/pred_clobber_2.c: Likewise. * gcc.target/aarch64/sve/pred_clobber_3.c: Likewise. * gcc.target/aarch64/tbz_2.c: Likewise. * gcc.target/riscv/core_bench_list.c: New test. * gcc.target/riscv/core_init_matrix.c: New test. * gcc.target/riscv/core_list_init.c: New test. * gcc.target/riscv/matrix_add_const.c: New test. * gcc.target/riscv/mem-extend.c: New test. * gcc.target/riscv/pr111384.c: New test. Co-authored-by: Jivan Hakobyan Co-authored-by: Joern Rennecke (cherry picked from commit 98914f9eba5f19d3eb93fbce8726b5264631cba0) Diff: --- gcc/Makefile.in | 1 + gcc/common.opt| 4 + gcc/df-scan.cc| 3 +- gcc/df.h | 1 + gcc/ext-dce.cc| 943 ++ gcc/opts.cc | 1 + gcc/passes.def| 1 + gcc/testsuite/gcc.target/aarch64/tbz_2.c | 6 +- gcc/testsuite/gcc.target/riscv/core_bench_list.c | 15 + gcc/testsuite/gcc.target/riscv/core_init_matrix.c | 17 + gcc/testsuite/gcc.target/riscv/core_list_init.c | 18 + gcc/testsuite/gcc.target/riscv/matrix_add_const.c | 13 + gcc/testsuite/gcc.target/riscv/mem-extend.c | 14 + gcc/testsuite/gcc.target/riscv/pr111384.c | 11 + gcc/tree-pass.h | 1 + 15 files changed, 1044 insertions(+), 5 deletions(-) diff --git a/gcc/Makefile.in b/gcc/Makefile.in index a74761b7ab3..c070a38f
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 1
https://gcc.gnu.org/g:c75ea600c62ad1b735f7baa8fcef3d96a4615fec
commit c75ea600c62ad1b735f7baa8fcef3d96a4615fec
Author: Pan Li
Date: Mon Jul 8 20:31:31 2024 +0800
RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 1
After the middle-end supported the vector mode of .SAT_ADD, add more
testcases to ensure the correctness of RISC-V backend for form 1. Aka:
Form 1:
#define DEF_VEC_SAT_U_ADD_IMM_FMT_1(T, IMM) \
T __attribute__((noinline)) \
vec_sat_u_add_imm##IMM##_##T##_fmt_1 (T *out, T *in, unsigned limit) \
{\
unsigned i;\
for (i = 0; i < limit; i++)\
out[i] = (T)(in[i] + IMM) >= in[i] ? (in[i] + IMM) : -1; \
}
DEF_VEC_SAT_U_ADD_IMM_FMT_1 (uint64_t, 9)
Passed the fully rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add help
test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-1.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-2.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-3.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-4.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-1.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-2.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-3.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-4.c: New
test.
Signed-off-by: Pan Li
(cherry picked from commit 35b1096896a94a90d787f5ef402ba009dd4f0393)
Diff:
---
.../riscv/rvv/autovec/binop/vec_sat_arith.h| 25 ++
.../riscv/rvv/autovec/binop/vec_sat_data.h | 256 +
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-1.c | 14 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-2.c | 14 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-3.c | 14 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-4.c | 14 ++
.../rvv/autovec/binop/vec_sat_u_add_imm-run-1.c| 28 +++
.../rvv/autovec/binop/vec_sat_u_add_imm-run-2.c| 28 +++
.../rvv/autovec/binop/vec_sat_u_add_imm-run-3.c| 28 +++
.../rvv/autovec/binop/vec_sat_u_add_imm-run-4.c| 28 +++
10 files changed, 449 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index b55a589e019..3733c8fd2c1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -4,6 +4,14 @@
#include
#include
+#define VALIDATE_RESULT(out, expect, N) \
+ do \
+{\
+ for (unsigned i = 0; i < N; i++) \
+if (out[i] != expect[i]) __builtin_abort (); \
+}\
+ while (false)
+
/**/
/* Saturation Add (unsigned and signed)
*/
/**/
@@ -139,6 +147,23 @@ vec_sat_u_add_##T##_fmt_8 (T *out, T *op_1, T *op_2,
unsigned limit) \
#define RUN_VEC_SAT_U_ADD_FMT_8(T, out, op_1, op_2, N) \
vec_sat_u_add_##T##_fmt_8(out, op_1, op_2, N)
+#define DEF_VEC_SAT_U_ADD_IMM_FMT_1(T, IMM) \
+T __attribute__((noinline)) \
+vec_sat_u_add_imm##IMM##_##T##_fmt_1 (T *out, T *in, unsigned limit) \
+{\
+ unsigned i;\
+ for (i = 0; i < limit; i++)\
+out[i] = (T)(in[i] + IMM) >= in[i] ? (in[i] + IMM) : -1; \
+}
+#define DEF_VEC_SAT_U_ADD_IMM_FMT_1_WRAP(T, IMM) \
+ DEF_VEC_SAT_U_ADD_IMM_FMT_1(T, IMM)
+
+#define RUN_VEC_SAT_U_ADD_IMM_FMT_1(T, out, op_1, expect, IMM, N) \
+ vec_sat_u_add_imm##IMM##_##T##_fmt_1(out, op_1, N); \
+ VALIDATE_RESULT (out, expect, N)
+#define RUN_VEC_SAT_U_ADD_IMM_FMT_1_WRAP(T, out, op_1, expect, IMM, N) \
+ RUN_VEC_SAT_U_ADD_IMM_FMT_1(T, out, op_1, expect, IMM, N)
+
/**/
/* Saturation Sub (Unsigned and Signed)
*/
/***
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 2
https://gcc.gnu.org/g:6add49f7ac9bca9e04f04a66d4e46db43618ef71
commit 6add49f7ac9bca9e04f04a66d4e46db43618ef71
Author: Pan Li
Date: Mon Jul 8 21:58:59 2024 +0800
RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 2
After the middle-end supported the vector mode of .SAT_ADD, add more
testcases to ensure the correctness of RISC-V backend for form 2. Aka:
Form 2:
#define DEF_VEC_SAT_U_ADD_IMM_FMT_2(T, IMM) \
T __attribute__((noinline)) \
vec_sat_u_add_imm##IMM##_##T##_fmt_2 (T *out, T *in, unsigned limit) \
{\
unsigned i;\
for (i = 0; i < limit; i++)\
out[i] = (T)(in[i] + IMM) < in[i] ? -1 : (in[i] + IMM); \
}
DEF_VEC_SAT_U_ADD_IMM_FMT_2 (uint64_t, 9)
Passed the fully rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add help
test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-6.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-8.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-5.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-6.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-7.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-8.c: New
test.
Signed-off-by: Pan Li
(cherry picked from commit ecde8d50bea3573194f21277666f83463cbbe9c9)
Diff:
---
.../riscv/rvv/autovec/binop/vec_sat_arith.h| 17 +
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c | 14 +++
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-6.c | 14 +++
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c | 14 +++
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-8.c | 14 +++
.../rvv/autovec/binop/vec_sat_u_add_imm-run-5.c| 28 ++
.../rvv/autovec/binop/vec_sat_u_add_imm-run-6.c| 28 ++
.../rvv/autovec/binop/vec_sat_u_add_imm-run-7.c| 28 ++
.../rvv/autovec/binop/vec_sat_u_add_imm-run-8.c| 28 ++
9 files changed, 185 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index 3733c8fd2c1..10459807b2c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -158,12 +158,29 @@ vec_sat_u_add_imm##IMM##_##T##_fmt_1 (T *out, T *in,
unsigned limit) \
#define DEF_VEC_SAT_U_ADD_IMM_FMT_1_WRAP(T, IMM) \
DEF_VEC_SAT_U_ADD_IMM_FMT_1(T, IMM)
+#define DEF_VEC_SAT_U_ADD_IMM_FMT_2(T, IMM) \
+T __attribute__((noinline)) \
+vec_sat_u_add_imm##IMM##_##T##_fmt_2 (T *out, T *in, unsigned limit) \
+{\
+ unsigned i;\
+ for (i = 0; i < limit; i++)\
+out[i] = (T)(in[i] + IMM) < in[i] ? -1 : (in[i] + IMM); \
+}
+#define DEF_VEC_SAT_U_ADD_IMM_FMT_2_WRAP(T, IMM) \
+ DEF_VEC_SAT_U_ADD_IMM_FMT_2(T, IMM)
+
#define RUN_VEC_SAT_U_ADD_IMM_FMT_1(T, out, op_1, expect, IMM, N) \
vec_sat_u_add_imm##IMM##_##T##_fmt_1(out, op_1, N); \
VALIDATE_RESULT (out, expect, N)
#define RUN_VEC_SAT_U_ADD_IMM_FMT_1_WRAP(T, out, op_1, expect, IMM, N) \
RUN_VEC_SAT_U_ADD_IMM_FMT_1(T, out, op_1, expect, IMM, N)
+#define RUN_VEC_SAT_U_ADD_IMM_FMT_2(T, out, op_1, expect, IMM, N) \
+ vec_sat_u_add_imm##IMM##_##T##_fmt_2(out, op_1, N); \
+ VALIDATE_RESULT (out, expect, N)
+#define RUN_VEC_SAT_U_ADD_IMM_FMT_2_WRAP(T, out, op_1, expect, IMM, N) \
+ RUN_VEC_SAT_U_ADD_IMM_FMT_2(T, out, op_1, expect, IMM, N)
+
/**/
/* Saturation Sub (Unsigned and Signed)
*/
/**/
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c
new file mode 100644
index 000..d25fdcf78f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c
@@ -0,0 +1,14 @@
+/*
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add support for B standard extension
https://gcc.gnu.org/g:03d27d8b26649675e4258248db98b58f493a6d0d
commit 03d27d8b26649675e4258248db98b58f493a6d0d
Author: Edwin Lu
Date: Wed Jul 10 09:44:48 2024 -0700
RISC-V: Add support for B standard extension
This patch adds support for recognizing the B standard extension to be the
collection of Zba, Zbb, Zbs extensions for consistency and conciseness
across toolchains
https://github.com/riscv/riscv-b/tags
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add imply rules for B
extension
* config/riscv/arch-canonicalize: Ditto
Signed-off-by: Edwin Lu
(cherry picked from commit 2a90c41a131080e5fdd2b5554fcdba5c654cb93f)
Diff:
---
gcc/common/config/riscv/riscv-common.cc | 7 +++
gcc/config/riscv/arch-canonicalize | 1 +
2 files changed, 8 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index f09dc300dd8..ee8397260f2 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -84,6 +84,10 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zabha", "zaamo"},
+ {"b", "zba"},
+ {"b", "zbb"},
+ {"b", "zbs"},
+
{"zdinx", "zfinx"},
{"zfinx", "zicsr"},
{"zdinx", "zicsr"},
@@ -245,6 +249,8 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
{"c", ISA_SPEC_CLASS_20190608, 2, 0},
{"c", ISA_SPEC_CLASS_2P2, 2, 0},
+ {"b", ISA_SPEC_CLASS_NONE, 1, 0},
+
{"h", ISA_SPEC_CLASS_NONE, 1, 0},
{"v", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -405,6 +411,7 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
static const struct riscv_ext_version riscv_combine_info[] =
{
{"a", ISA_SPEC_CLASS_20191213, 2, 1},
+ {"b", ISA_SPEC_CLASS_NONE, 1, 0},
{"zk", ISA_SPEC_CLASS_NONE, 1, 0},
{"zkn", ISA_SPEC_CLASS_NONE, 1, 0},
{"zks", ISA_SPEC_CLASS_NONE, 1, 0},
diff --git a/gcc/config/riscv/arch-canonicalize
b/gcc/config/riscv/arch-canonicalize
index 35a7fe4455a..2ea514dd986 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -45,6 +45,7 @@ IMPLIED_EXT = {
"zabha" : ["zaamo"],
"f" : ["zicsr"],
+ "b" : ["zba", "zbb", "zbs"],
"zdinx" : ["zfinx", "zicsr"],
"zfinx" : ["zicsr"],
"zhinx" : ["zhinxmin", "zfinx", "zicsr"],
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Update testsuite to use b
https://gcc.gnu.org/g:bcb9efbd9bb2e90115f65348f47ea2721ff53855
commit bcb9efbd9bb2e90115f65348f47ea2721ff53855
Author: Edwin Lu
Date: Wed Jul 3 17:17:27 2024 -0700
RISC-V: Update testsuite to use b
Update all instances of zba_zbb_zbs in the testsuite to use b instead
gcc/testsuite/ChangeLog:
* g++.target/riscv/redundant-bitmap-1.C: Use gcb instead of
zba_zbb_zbs
* g++.target/riscv/redundant-bitmap-2.C: Ditto
* g++.target/riscv/redundant-bitmap-3.C: Ditto
* g++.target/riscv/redundant-bitmap-4.C: Ditto
* gcc.target/riscv/shift-add-1.c: Ditto
* gcc.target/riscv/shift-add-2.c: Ditto
* gcc.target/riscv/synthesis-1.c: Ditto
* gcc.target/riscv/synthesis-2.c: Ditto
* gcc.target/riscv/synthesis-3.c: Ditto
* gcc.target/riscv/synthesis-4.c: Ditto
* gcc.target/riscv/synthesis-5.c: Ditto
* gcc.target/riscv/synthesis-6.c: Ditto
* gcc.target/riscv/synthesis-7.c: Ditto
* gcc.target/riscv/synthesis-8.c: Ditto
* gcc.target/riscv/zba_zbs_and-1.c: Ditto
* gcc.target/riscv/zbs-zext-3.c: Ditto
* lib/target-supports.exp: Add b to riscv_get_arch
Signed-off-by: Edwin Lu
(cherry picked from commit 04df2a924bba38c271bfe4ed0e94af1877413818)
Diff:
---
gcc/testsuite/g++.target/riscv/redundant-bitmap-1.C | 2 +-
gcc/testsuite/g++.target/riscv/redundant-bitmap-2.C | 2 +-
gcc/testsuite/g++.target/riscv/redundant-bitmap-3.C | 2 +-
gcc/testsuite/g++.target/riscv/redundant-bitmap-4.C | 2 +-
gcc/testsuite/gcc.target/riscv/shift-add-1.c| 2 +-
gcc/testsuite/gcc.target/riscv/shift-add-2.c| 2 +-
gcc/testsuite/gcc.target/riscv/synthesis-1.c| 2 +-
gcc/testsuite/gcc.target/riscv/synthesis-2.c| 2 +-
gcc/testsuite/gcc.target/riscv/synthesis-3.c| 2 +-
gcc/testsuite/gcc.target/riscv/synthesis-4.c| 2 +-
gcc/testsuite/gcc.target/riscv/synthesis-5.c| 2 +-
gcc/testsuite/gcc.target/riscv/synthesis-6.c| 2 +-
gcc/testsuite/gcc.target/riscv/synthesis-7.c| 2 +-
gcc/testsuite/gcc.target/riscv/synthesis-8.c| 2 +-
gcc/testsuite/gcc.target/riscv/zba_zbs_and-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/zbs-zext-3.c | 4 ++--
gcc/testsuite/lib/target-supports.exp | 2 +-
17 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/gcc/testsuite/g++.target/riscv/redundant-bitmap-1.C
b/gcc/testsuite/g++.target/riscv/redundant-bitmap-1.C
index 37066f10eea..62bb2ab7b67 100644
--- a/gcc/testsuite/g++.target/riscv/redundant-bitmap-1.C
+++ b/gcc/testsuite/g++.target/riscv/redundant-bitmap-1.C
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc_zba_zbb_zbs -mabi=lp64" } */
+/* { dg-options "-O2 -march=rv64gcb -mabi=lp64" } */
void setBit(char &a, int b) {
char c = 0x1UL << b;
diff --git a/gcc/testsuite/g++.target/riscv/redundant-bitmap-2.C
b/gcc/testsuite/g++.target/riscv/redundant-bitmap-2.C
index 86acaba298f..52204daecd1 100644
--- a/gcc/testsuite/g++.target/riscv/redundant-bitmap-2.C
+++ b/gcc/testsuite/g++.target/riscv/redundant-bitmap-2.C
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc_zba_zbb_zbs -mabi=lp64" } */
+/* { dg-options "-O2 -march=rv64gcb -mabi=lp64" } */
void setBit(char &a, int b) {
char c = 0x1UL << b;
diff --git a/gcc/testsuite/g++.target/riscv/redundant-bitmap-3.C
b/gcc/testsuite/g++.target/riscv/redundant-bitmap-3.C
index 16bd7c1785e..6745220f2f4 100644
--- a/gcc/testsuite/g++.target/riscv/redundant-bitmap-3.C
+++ b/gcc/testsuite/g++.target/riscv/redundant-bitmap-3.C
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc_zba_zbb_zbs -mabi=lp64" } */
+/* { dg-options "-O2 -march=rv64gcb -mabi=lp64" } */
void setBit(char &a, int b) {
char c = 0x1UL << b;
diff --git a/gcc/testsuite/g++.target/riscv/redundant-bitmap-4.C
b/gcc/testsuite/g++.target/riscv/redundant-bitmap-4.C
index f664ee01a01..5e351fe457e 100644
--- a/gcc/testsuite/g++.target/riscv/redundant-bitmap-4.C
+++ b/gcc/testsuite/g++.target/riscv/redundant-bitmap-4.C
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc_zba_zbb_zbs -mabi=lp64" } */
+/* { dg-options "-O2 -march=rv64gcb -mabi=lp64" } */
void setBit(char &a, int b) {
char c = 0x1UL << b;
diff --git a/gcc/testsuite/gcc.target/riscv/shift-add-1.c
b/gcc/testsuite/gcc.target/riscv/shift-add-1.c
index d98875c3271..db84a51a222 100644
--- a/gcc/testsuite/gcc.target/riscv/shift-add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/shift-add-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zba_zbb_zbs -mabi=lp64" } */
+/* { dg-options "-march=rv64gcb -mabi=lp64" } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
int composeFromSurrogate(const unsigned short high) {
diff --git a/gcc/testsuite/gcc.target/ris
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: c implies zca, and conditionally zcf & zcd
https://gcc.gnu.org/g:921baffaadbe71518d881da39f9d1bbcdcc31509
commit 921baffaadbe71518d881da39f9d1bbcdcc31509
Author: Fei Gao
Date: Wed Jul 10 10:12:02 2024 +
RISC-V: c implies zca, and conditionally zcf & zcd
According to Zc-1.0.4-3.pdf from
https://github.com/riscvarchive/riscv-code-size-reduction/releases/tag/v1.0.4-3
The rule is that:
- C always implies Zca
- C+F implies Zcf (RV32 only)
- C+D implies Zcd
Signed-off-by: Fei Gao
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc:
c implies zca, and conditionally zcf & zcd.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/attribute-15.c: adapt TC.
* gcc.target/riscv/attribute-16.c: likewise.
* gcc.target/riscv/attribute-17.c: likewise.
* gcc.target/riscv/attribute-18.c: likewise.
* gcc.target/riscv/pr110696.c: likewise.
* gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c: likewise.
* gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c: likewise.
* gcc.target/riscv/rvv/base/pr114352-1.c: likewise.
* gcc.target/riscv/rvv/base/pr114352-3.c: likewise.
* gcc.target/riscv/arch-39.c: New test.
* gcc.target/riscv/arch-40.c: New test.
(cherry picked from commit 36e5e409190e595638cec053ea034d20d5c74d6b)
Diff:
---
gcc/common/config/riscv/riscv-common.cc | 12
gcc/testsuite/gcc.target/riscv/arch-39.c | 7 +++
gcc/testsuite/gcc.target/riscv/arch-40.c | 7 +++
gcc/testsuite/gcc.target/riscv/attribute-15.c| 2 +-
gcc/testsuite/gcc.target/riscv/attribute-16.c| 2 +-
gcc/testsuite/gcc.target/riscv/attribute-17.c| 2 +-
gcc/testsuite/gcc.target/riscv/attribute-18.c| 2 +-
gcc/testsuite/gcc.target/riscv/pr110696.c| 2 +-
.../gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c | 2 +-
.../gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c | 4 ++--
gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c | 8
12 files changed, 39 insertions(+), 13 deletions(-)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index ee8397260f2..e682b0f5c67 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -82,6 +82,18 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"a", "zaamo"},
{"a", "zalrsc"},
+ {"c", "zca"},
+ {"c", "zcf",
+ [] (const riscv_subset_list *subset_list) -> bool
+ {
+ return subset_list->xlen () == 32 && subset_list->lookup ("f");
+ }},
+ {"c", "zcd",
+ [] (const riscv_subset_list *subset_list) -> bool
+ {
+ return subset_list->lookup ("d");
+ }},
+
{"zabha", "zaamo"},
{"b", "zba"},
diff --git a/gcc/testsuite/gcc.target/riscv/arch-39.c
b/gcc/testsuite/gcc.target/riscv/arch-39.c
new file mode 100644
index 000..beeb81e44c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-39.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64idc_zcmt -mabi=lp64d" } */
+int
+foo ()
+{}
+
+/* { dg-error "zcd conflicts with zcmt" "" { target *-*-* } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/arch-40.c
b/gcc/testsuite/gcc.target/riscv/arch-40.c
new file mode 100644
index 000..eaefaf1d0d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-40.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64idc_zcmp -mabi=lp64d" } */
+int
+foo ()
+{}
+
+/* { dg-error "zcd conflicts with zcmp" "" { target *-*-* } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-15.c
b/gcc/testsuite/gcc.target/riscv/attribute-15.c
index a2e394b6489..ac6caaecd4f 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-15.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-15.c
@@ -3,4 +3,4 @@
int foo()
{
}
-/* { dg-final { scan-assembler ".attribute arch,
\"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */
+/* { dg-final { scan-assembler ".attribute arch,
\"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\""
} } */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-16.c
b/gcc/testsuite/gcc.target/riscv/attribute-16.c
index d2b18160cb5..539e426ca97 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-16.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-16.c
@@ -3,4 +3,4 @@
int foo()
{
}
-/* { dg-final { scan-assembler ".attribute arch,
\"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\""
} } */
+/* { dg-final { scan-assembler ".attribute arch,
\"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\""
} } */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-17.c
b/gcc/testsui
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for vector .SAT_SUB in zip benchmark
https://gcc.gnu.org/g:9996d074b720b565e043792070cefe84a4572ef1
commit 9996d074b720b565e043792070cefe84a4572ef1
Author: Pan Li
Date: Thu Jul 11 15:54:32 2024 +0800
RISC-V: Add testcases for vector .SAT_SUB in zip benchmark
This patch would like to add the test cases for the vector .SAT_SUB in
the zip benchmark. Aka:
Form in zip benchmark:
#define DEF_VEC_SAT_U_SUB_ZIP(T1, T2) \
void __attribute__((noinline))\
vec_sat_u_sub_##T1##_##T2##_fmt_zip (T1 *x, T2 b, unsigned limit) \
{ \
T2 a; \
T1 *p = x; \
do {\
a = *--p; \
*p = (T1)(a >= b ? a - b : 0);\
} while (--limit); \
}
DEF_VEC_SAT_U_SUB_ZIP(uint8_t, uint16_t)
vec_sat_u_sub_uint16_t_uint32_t_fmt_zip:
...
vsetvli a4,zero,e32,m1,ta,ma
vmv.v.x v6,a1
vsetvli zero,zero,e16,mf2,ta,ma
vid.v v2
lia4,-1
vnclipu.wiv6,v6,0 // .SAT_TRUNC
.L3:
vle16.v v3,0(a3)
vrsub.vx v5,v2,a6
mva7,a4
addw a4,a4,t3
vrgather.vv v1,v3,v5
vssubu.vv v1,v1,v6 // .SAT_SUB
vrgather.vv v3,v1,v5
vse16.v v3,0(a3)
sub a3,a3,t1
bgtu t4,a4,.L3
Passed the rv64gcv tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test
helper macros.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h: Add test
data for .SAT_SUB in zip benchmark.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip-run.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c: New test.
Signed-off-by: Pan Li
(cherry picked from commit b3c686416e88bf135def0e72d316713af01445a1)
Diff:
---
.../riscv/rvv/autovec/binop/vec_sat_arith.h| 18 +
.../riscv/rvv/autovec/binop/vec_sat_binary_vx.h| 22 ++
.../riscv/rvv/autovec/binop/vec_sat_data.h | 81 ++
.../rvv/autovec/binop/vec_sat_u_sub_zip-run.c | 16 +
.../riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c| 18 +
5 files changed, 155 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index 10459807b2c..416a1e49a47 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -322,6 +322,19 @@ vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2,
unsigned limit) \
} \
}
+#define DEF_VEC_SAT_U_SUB_ZIP(T1, T2) \
+void __attribute__((noinline))\
+vec_sat_u_sub_##T1##_##T2##_fmt_zip (T1 *x, T2 b, unsigned limit) \
+{ \
+ T2 a; \
+ T1 *p = x; \
+ do {\
+a = *--p; \
+*p = (T1)(a >= b ? a - b : 0);\
+ } while (--limit); \
+}
+#define DEF_VEC_SAT_U_SUB_ZIP_WRAP(T1, T2) DEF_VEC_SAT_U_SUB_ZIP(T1, T2)
+
#define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \
vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N)
@@ -352,6 +365,11 @@ vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2,
unsigned limit) \
#define RUN_VEC_SAT_U_SUB_FMT_10(T, out, op_1, op_2, N) \
vec_sat_u_sub_##T##_fmt_10(out, op_1, op_2, N)
+#define RUN_VEC_SAT_U_SUB_FMT_ZIP(T1, T2, x, b, N) \
+ vec_sat_u_sub_##T1##_##T2##_fmt_zip(x, b, N)
+#define RUN_VEC_SAT_U_SUB_FMT_ZIP_WRAP(T1, T2, x, b, N) \
+ RUN_VEC_SAT_U_SUB_FMT_ZIP(T1, T2, x, b, N) \
+
/**/
/* Saturation Sub Truncated (Unsigned and Signed)
*/
/**/
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h
new file mode 100644
index 000
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Eliminate unnecessary sign extension after inlined str[n]cmp
https://gcc.gnu.org/g:2360e1573b25467a62ed84a478f33e488230ad07
commit 2360e1573b25467a62ed84a478f33e488230ad07
Author: Jeff Law
Date: Thu Jul 11 12:05:56 2024 -0600
[to-be-committed,RISC-V] Eliminate unnecessary sign extension after inlined
str[n]cmp
This patch eliminates an unnecessary sign extension for scalar inlined
string comparisons on rv64.
Conceptually this is pretty simple. Prove all the paths which "return"
a value from the inlined string comparison already have sign extended
values.
FINAL_LABEL is the point after the calculation of the return value. So
if we have a jump to FINAL_LABEL, we must have a properly extended
result value at that point.
Second we're going to arrange in the .md part of the expander to use an
X mode temporary for the result. After computing the result we will (if
necessary) extract the low part of the result using a SUBREG tagged with
the appropriate SUBREG_PROMOTED_* bits.
So with that background.
We find a jump to FINAL_LABEL in emit_strcmp_scalar_compare_byte. Since
we know the result is X mode, we can just emit the subtraction of the
two chars in X mode and we'll have a properly sign extended result.
There's 4 jumps to final_label in emit_strcmp_scalar.
The first is just returning zero and needs trivial simplification to not
force the result into SImode.
The second is after calling strcmp in the library. The ABI mandates
that value is sign extended, so there's nothing to do for that case.
The 3rd occurs after a call to
emit_strcmp_scalar_result_calculation_nonul. If we dive into that
routine it needs simplificationq similar to what we did in
emit_strcmp_scalar_compare_byte
The 4th occurs after a call to emit_strcmp_scalar_result_calculation
which again needs trivial adjustment like we've done in the other routines.
Finally, at the end of expand_strcmp, just store the X mode result
sitting in SUB to RESULT.
The net of all that is we know every path has its result properly
extended to X mode. Standard redundant extension removal will take care
of the rest.
We've been running this within Ventana for about 6 months, so naturally
it's been through various QA cycles, dhrystone, spec2017, etc. It's
also been through a build/test cycle in my tester. Waiting on results
from the pre-commit testing before moving forward.
gcc/
* config/riscv/riscv-string.cc
(emit_strcmp_scalar_compare_byte): Set RESULT directly rather
than using a new temporary.
(emit_strcmp_scalar_result_calculation_nonul): Likewise.
(emit_strcmp_scalar_result_calculation): Likewise.
(riscv_expand_strcmp_scalar): Use CONST0_RTX rather than
generating a new node.
(expand_strcmp): Copy directly from SUB to RESULT.
* config/riscv/riscv.md (cmpstrnsi, cmpstrsi): Pass an X
mode temporary to the expansion routines. If necessary
extract low part of the word to store in final result location.
(cherry picked from commit 74d8accaf88f83bfcab1150bf9be5140e7ac0e94)
Diff:
---
gcc/config/riscv/riscv-string.cc | 15 +--
gcc/config/riscv/riscv.md| 28
2 files changed, 29 insertions(+), 14 deletions(-)
diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc
index 257a514d290..4736228e6f1 100644
--- a/gcc/config/riscv/riscv-string.cc
+++ b/gcc/config/riscv/riscv-string.cc
@@ -140,9 +140,7 @@ static void
emit_strcmp_scalar_compare_byte (rtx result, rtx data1, rtx data2,
rtx final_label)
{
- rtx tmp = gen_reg_rtx (Xmode);
- do_sub3 (tmp, data1, data2);
- emit_insn (gen_movsi (result, gen_lowpart (SImode, tmp)));
+ do_sub3 (result, data1, data2);
emit_jump_insn (gen_jump (final_label));
emit_barrier (); /* No fall-through. */
}
@@ -310,8 +308,7 @@ emit_strcmp_scalar_result_calculation_nonul (rtx result,
rtx data1, rtx data2)
rtx tmp = gen_reg_rtx (Xmode);
emit_insn (gen_slt_3 (LTU, Xmode, Xmode, tmp, data1, data2));
do_neg2 (tmp, tmp);
- do_ior3 (tmp, tmp, const1_rtx);
- emit_insn (gen_movsi (result, gen_lowpart (SImode, tmp)));
+ do_ior3 (result, tmp, const1_rtx);
}
/* strcmp-result calculation.
@@ -367,9 +364,7 @@ emit_strcmp_scalar_result_calculation (rtx result, rtx
data1, rtx data2,
unsigned int shiftr = (xlen - 1) * BITS_PER_UNIT;
do_lshr3 (data1, data1, GEN_INT (shiftr));
do_lshr3 (data2, data2, GEN_INT (shiftr));
- rtx tmp = gen_reg_rtx (Xmode);
- do_sub3 (tmp, data1, data2);
- emit_insn (gen_movsi (result, gen_lowpart (SImode, tmp)));
+ do_sub3 (result, data1, data2);
}
/* Expand str(n)cmp using Zbb/TheadBb instructions.
@@ -444,7 +439,7 @@ riscv_expand_strcmp_scalar (rtx result, rtx src1, rt
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add SiFive extensions, xsfvcp and xsfcease
https://gcc.gnu.org/g:dd3171eebd56f22cf06afbc9fbe992709d41965e
commit dd3171eebd56f22cf06afbc9fbe992709d41965e
Author: Kito Cheng
Date: Tue Jul 9 15:50:57 2024 +0800
RISC-V: Add SiFive extensions, xsfvcp and xsfcease
We have already upstreamed these extensions into binutils, and now we need
GCC
to recognize these extensions and pass them to binutils as well. We also
plan
to upstream intrinsics in the near future. :)
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (riscv_implied_info): Add
xsfvcp.
(riscv_ext_version_table): Add xsfvcp, xsfcease.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv.opt (riscv_sifive_subext): New.
(XSFVCP): New.
(XSFCEASE): New.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-sf-1.c: New.
* gcc.target/riscv/predef-sf-2.c: New.
(cherry picked from commit 3ea47ea1fcab95fd1b80acc724fdbb27fc436985)
Diff:
---
gcc/common/config/riscv/riscv-common.cc | 8
gcc/config/riscv/riscv.opt | 7 +++
gcc/testsuite/gcc.target/riscv/predef-sf-1.c | 19 +++
gcc/testsuite/gcc.target/riscv/predef-sf-2.c | 14 ++
4 files changed, 48 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index e682b0f5c67..682826c0e34 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -216,6 +216,8 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"ssstateen", "zicsr"},
{"sstc", "zicsr"},
+ {"xsfvcp", "zve32x"},
+
{NULL, NULL}
};
@@ -415,6 +417,9 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
{"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"xsfvcp", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"xsfcease", ISA_SPEC_CLASS_NONE, 1, 0},
+
/* Terminate the list. */
{NULL, ISA_SPEC_CLASS_NONE, 0, 0}
};
@@ -1730,6 +1735,9 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
{"xventanacondops", &gcc_options::x_riscv_xventana_subext,
MASK_XVENTANACONDOPS},
+ {"xsfvcp", &gcc_options::x_riscv_sifive_subext, MASK_XSFVCP},
+ {"xsfcease", &gcc_options::x_riscv_sifive_subext, MASK_XSFCEASE},
+
{NULL, NULL, 0}
};
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index e882caa8b7f..edf1c6d85f3 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -507,6 +507,13 @@ int riscv_xventana_subext
Mask(XVENTANACONDOPS) Var(riscv_xventana_subext)
+TargetVariable
+int riscv_sifive_subext
+
+Mask(XSFVCP) Var(riscv_sifive_subext)
+
+Mask(XSFCEASE) Var(riscv_sifive_subext)
+
Enum
Name(isa_spec_class) Type(enum riscv_isa_spec_class)
Supported ISA specs (for use with the -misa-spec= option):
diff --git a/gcc/testsuite/gcc.target/riscv/predef-sf-1.c
b/gcc/testsuite/gcc.target/riscv/predef-sf-1.c
new file mode 100644
index 000..d6c07e7d920
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-sf-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_xsfvcp -mabi=lp64" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if !defined(__riscv_zve32x)
+#error "__riscv_zve32x"
+#endif
+
+
+#if !defined(__riscv_xsfvcp)
+#error "__riscv_xsfvcp"
+#endif
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-sf-2.c
b/gcc/testsuite/gcc.target/riscv/predef-sf-2.c
new file mode 100644
index 000..dcb746bcd26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-sf-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_xsfcease -mabi=lp64" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if !defined(__riscv_xsfcease)
+#error "__riscv_xsfvcp"
+#endif
+
+ return 0;
+}
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Disable misaligned vector access in hook riscv_slow_unaligned_access[PR115862]
https://gcc.gnu.org/g:493983818e91105cf1b48cc30865ff218a73223d
commit 493983818e91105cf1b48cc30865ff218a73223d
Author: xuli
Date: Thu Jul 11 04:29:11 2024 +
RISC-V: Disable misaligned vector access in hook
riscv_slow_unaligned_access[PR115862]
The reason is that in the following code, icode = movmisalignv8si has
already been rejected by TARGET_VECTOR_MISALIGN_SUPPORTED, but it is
allowed by targetm.slow_unaligned_access,which is contradictory.
(((icode = optab_handler (movmisalign_optab, mode))
!= CODE_FOR_nothing)
|| targetm.slow_unaligned_access (mode, align))
misaligned vector access should be enabled by -mno-vector-strict-align
option.
PR target/115862
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_slow_unaligned_access): Disable
vector misalign.
Signed-off-by: Li Xu
(cherry picked from commit 63d7d5998e3768f6e3703c29e8774e8b54af108c)
Diff:
---
gcc/config/riscv/riscv.cc | 5 ++-
gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c | 52 ++
2 files changed, 55 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index fd4b81e61ae..c0f3c1d7244 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -10277,9 +10277,10 @@ riscv_cannot_copy_insn_p (rtx_insn *insn)
/* Implement TARGET_SLOW_UNALIGNED_ACCESS. */
static bool
-riscv_slow_unaligned_access (machine_mode, unsigned int)
+riscv_slow_unaligned_access (machine_mode mode, unsigned int)
{
- return riscv_slow_unaligned_access_p;
+ return VECTOR_MODE_P (mode) ? TARGET_VECTOR_MISALIGN_SUPPORTED
+ : riscv_slow_unaligned_access_p;
}
static bool
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c
new file mode 100644
index 000..3cbc3c3a0ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gcv_zvl512b -mabi=lp64d" } */
+
+struct mallinfo2
+{
+ int arena;
+ int ordblks;
+ int smblks;
+ int hblks;
+ int hblkhd;
+ int usmblks;
+ int fsmblks;
+ int uordblks;
+ int fordblks;
+ int keepcost;
+};
+
+struct mallinfo
+{
+ int arena;
+ int ordblks;
+ int smblks;
+ int hblks;
+ int hblkhd;
+ int usmblks;
+ int fsmblks;
+ int uordblks;
+ int fordblks;
+ int keepcost;
+};
+
+struct mallinfo
+__libc_mallinfo (void)
+{
+ struct mallinfo m;
+ struct mallinfo2 m2;
+
+ m.arena = m2.arena;
+ m.ordblks = m2.ordblks;
+ m.smblks = m2.smblks;
+ m.hblks = m2.hblks;
+ m.hblkhd = m2.hblkhd;
+ m.usmblks = m2.usmblks;
+ m.fsmblks = m2.fsmblks;
+ m.uordblks = m2.uordblks;
+ m.fordblks = m2.fordblks;
+ m.keepcost = m2.keepcost;
+
+ return m;
+}
+
+/* { dg-final { scan-assembler {vle32\.v} } } */
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V] Avoid unnecessary sign extension after memcmp
https://gcc.gnu.org/g:587dbc1ee0c2bc56dd1edfc4b3a1f8dc9abf2760
commit 587dbc1ee0c2bc56dd1edfc4b3a1f8dc9abf2760
Author: Jeff Law
Date: Fri Jul 12 07:53:41 2024 -0600
[RISC-V] Avoid unnecessary sign extension after memcmp
Similar to the str[n]cmp work, this adjusts the block compare expansion to
do
its work in X mode with an appropriate lowpart extraction of the results at
the
end of the sequence.
This has gone through my tester on rv32 and rv64, but that's it. Waiting on
pre-commit testing before moving forward.
gcc/
* config/riscv/riscv-string.cc
(emit_memcmp_scalar_load_and_compare):
Set RESULT directly rather than using a temporary.
(emit_memcmp_scalar_result_calculation): Similarly.
(riscv_expand_block_compare_scalar): Use CONST0_RTX rather than
generating new RTL.
* config/riscv/riscv.md (cmpmemsi): Pass an X mode temporary to the
expansion routines. If necessary extract low part of the word to
store
in final result location.
(cherry picked from commit ae829a27785307232e4db0df6a30ca275941b613)
Diff:
---
gcc/config/riscv/riscv-string.cc | 15 ++-
gcc/config/riscv/riscv.md| 14 --
2 files changed, 18 insertions(+), 11 deletions(-)
diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc
index 4736228e6f1..80d22e87d57 100644
--- a/gcc/config/riscv/riscv-string.cc
+++ b/gcc/config/riscv/riscv-string.cc
@@ -663,9 +663,7 @@ emit_memcmp_scalar_load_and_compare (rtx result, rtx src1,
rtx src2,
/* Fast-path for a single byte. */
if (cmp_bytes == 1)
{
- rtx tmp = gen_reg_rtx (Xmode);
- do_sub3 (tmp, data1, data2);
- emit_insn (gen_movsi (result, gen_lowpart (SImode, tmp)));
+ do_sub3 (result, data1, data2);
emit_jump_insn (gen_jump (final_label));
emit_barrier (); /* No fall-through. */
return;
@@ -702,12 +700,11 @@ emit_memcmp_scalar_result_calculation (rtx result, rtx
data1, rtx data2)
/* Get bytes in big-endian order and compare as words. */
do_bswap2 (data1, data1);
do_bswap2 (data2, data2);
+
/* Synthesize (data1 >= data2) ? 1 : -1 in a branchless sequence. */
- rtx tmp = gen_reg_rtx (Xmode);
- emit_insn (gen_slt_3 (LTU, Xmode, Xmode, tmp, data1, data2));
- do_neg2 (tmp, tmp);
- do_ior3 (tmp, tmp, const1_rtx);
- emit_insn (gen_movsi (result, gen_lowpart (SImode, tmp)));
+ emit_insn (gen_slt_3 (LTU, Xmode, Xmode, result, data1, data2));
+ do_neg2 (result, result);
+ do_ior3 (result, result, const1_rtx);
}
/* Expand memcmp using scalar instructions (incl. Zbb).
@@ -773,7 +770,7 @@ riscv_expand_block_compare_scalar (rtx result, rtx src1,
rtx src2, rtx nbytes)
data1, data2,
diff_label, final_label);
- emit_insn (gen_rtx_SET (result, gen_rtx_CONST_INT (SImode, 0)));
+ emit_move_insn (result, CONST0_RTX (GET_MODE (result)));
emit_jump_insn (gen_jump (final_label));
emit_barrier (); /* No fall-through. */
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 2e2379dfca4..5dee837a587 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2675,9 +2675,19 @@
operands[2], operands[3]))
DONE;
- if (riscv_expand_block_compare (operands[0], operands[1], operands[2],
+ rtx temp = gen_reg_rtx (word_mode);
+ if (riscv_expand_block_compare (temp, operands[1], operands[2],
operands[3]))
-DONE;
+{
+ if (TARGET_64BIT)
+ {
+ temp = gen_lowpart (SImode, temp);
+ SUBREG_PROMOTED_VAR_P (temp) = 1;
+ SUBREG_PROMOTED_SET (temp, SRP_SIGNED);
+ }
+ emit_move_insn (operands[0], temp);
+ DONE;
+}
else
FAIL;
})
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PR rtl-optimization/115876] Fix one of two ubsan reported issues in new ext-dce.cc code
https://gcc.gnu.org/g:d38da39f34be9914f25b0db1e8054a74a8f7abe0
commit d38da39f34be9914f25b0db1e8054a74a8f7abe0
Author: Jeff Law
Date: Fri Jul 12 13:11:33 2024 -0600
[PR rtl-optimization/115876] Fix one of two ubsan reported issues in new
ext-dce.cc code
David Binderman did a bootstrap build with ubsan enabled which triggered a
few
errors in the new ext-dce.cc code. This fixes the trivial case of shifting
negative values.
Bootstrapped and regression tested on x86.
Pushing to the trunk.
gcc/
PR rtl-optimization/115876
* ext-dce.cc (carry_backpropagate): Make mask and mmask unsigned.
(cherry picked from commit a6f551d079de1d151b272bcdd3d42316857c9d4e)
Diff:
---
gcc/ext-dce.cc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/ext-dce.cc b/gcc/ext-dce.cc
index adc9084df57..91789d283fc 100644
--- a/gcc/ext-dce.cc
+++ b/gcc/ext-dce.cc
@@ -374,13 +374,13 @@ binop_implies_op2_fully_live (rtx_code code)
exclusively pertain to the first operand. */
HOST_WIDE_INT
-carry_backpropagate (HOST_WIDE_INT mask, enum rtx_code code, rtx x)
+carry_backpropagate (unsigned HOST_WIDE_INT mask, enum rtx_code code, rtx x)
{
if (mask == 0)
return 0;
enum machine_mode mode = GET_MODE_INNER (GET_MODE (x));
- HOST_WIDE_INT mmask = GET_MODE_MASK (mode);
+ unsigned HOST_WIDE_INT mmask = GET_MODE_MASK (mode);
switch (code)
{
case PLUS:
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add vector type of BFloat16 format
https://gcc.gnu.org/g:27cd96d5b1f12955f01f3a104d6701cb48bb20f9 commit 27cd96d5b1f12955f01f3a104d6701cb48bb20f9 Author: Feng Wang Date: Thu Jun 13 00:32:14 2024 + RISC-V: Add vector type of BFloat16 format v3: Rebase v2: Rebase The vector type of BFloat16 format is added in this patch, subsequent extensions to zvfbfmin and zvfwma need to be based on this patch. Signed-off-by: Feng Wang gcc/ChangeLog: * config/riscv/genrvv-type-indexer.cc (bfloat16_type): Generate bf16 vector_type and scalar_type in DEF_RVV_TYPE_INDEX. (bfloat16_wide_type): Ditto. (same_ratio_eew_bf16_type): Ditto. (main): Ditto. * config/riscv/riscv-modes.def (ADJUST_BYTESIZE): Add vector type for BFloat16. (RVV_WHOLE_MODES): Add vector type for BFloat16. (RVV_FRACT_MODE): Ditto. (RVV_NF4_MODES): Ditto. (RVV_NF8_MODES): Ditto. (RVV_NF2_MODES): Ditto. * config/riscv/riscv-vector-builtins-types.def (vbfloat16mf4_t): Add builtin vector type for BFloat16. (vbfloat16mf2_t): Add builtin vector type for BFloat16. (vbfloat16m1_t): Ditto. (vbfloat16m2_t): Ditto. (vbfloat16m4_t): Ditto. (vbfloat16m8_t): Ditto. (vbfloat16mf4x2_t): Ditto. (vbfloat16mf4x3_t): Ditto. (vbfloat16mf4x4_t): Ditto. (vbfloat16mf4x5_t): Ditto. (vbfloat16mf4x6_t): Ditto. (vbfloat16mf4x7_t): Ditto. (vbfloat16mf4x8_t): Ditto. (vbfloat16mf2x2_t): Ditto. (vbfloat16mf2x3_t): Ditto. (vbfloat16mf2x4_t): Ditto. (vbfloat16mf2x5_t): Ditto. (vbfloat16mf2x6_t): Ditto. (vbfloat16mf2x7_t): Ditto. (vbfloat16mf2x8_t): Ditto. (vbfloat16m1x2_t): Ditto. (vbfloat16m1x3_t): Ditto. (vbfloat16m1x4_t): Ditto. (vbfloat16m1x5_t): Ditto. (vbfloat16m1x6_t): Ditto. (vbfloat16m1x7_t): Ditto. (vbfloat16m1x8_t): Ditto. (vbfloat16m2x2_t): Ditto. (vbfloat16m2x3_t): Ditto. (vbfloat16m2x4_t): Ditto. (vbfloat16m4x2_t): Ditto. * config/riscv/riscv-vector-builtins.cc (check_required_extensions): Add required_ext checking for BFloat16. * config/riscv/riscv-vector-builtins.def (vbfloat16mf4_t): Add vector_type for BFloat16 in builtins.def. (vbfloat16mf4x2_t): Ditto. (vbfloat16mf4x3_t): Ditto. (vbfloat16mf4x4_t): Ditto. (vbfloat16mf4x5_t): Ditto. (vbfloat16mf4x6_t): Ditto. (vbfloat16mf4x7_t): Ditto. (vbfloat16mf4x8_t): Ditto. (vbfloat16mf2_t): Ditto. (vbfloat16mf2x2_t): Ditto. (vbfloat16mf2x3_t): Ditto. (vbfloat16mf2x4_t): Ditto. (vbfloat16mf2x5_t): Ditto. (vbfloat16mf2x6_t): Ditto. (vbfloat16mf2x7_t): Ditto. (vbfloat16mf2x8_t): Ditto. (vbfloat16m1_t): Ditto. (vbfloat16m1x2_t): Ditto. (vbfloat16m1x3_t): Ditto. (vbfloat16m1x4_t): Ditto. (vbfloat16m1x5_t): Ditto. (vbfloat16m1x6_t): Ditto. (vbfloat16m1x7_t): Ditto. (vbfloat16m1x8_t): Ditto. (vbfloat16m2_t): Ditto. (vbfloat16m2x2_t): Ditto. (vbfloat16m2x3_t): Ditto. (vbfloat16m2x4_t): Ditto. (vbfloat16m4_t): Ditto. (vbfloat16m4x2_t): Ditto. (vbfloat16m8_t): Ditto. (double_trunc_bfloat_scalar): Add scalar_type def for BFloat16. (double_trunc_bfloat_vector): Add vector_type def for BFloat16. * config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_ELEN_BF_16): Add required defination of BFloat16 ext. * config/riscv/riscv-vector-switch.def (ENTRY): Add vector_type information for BFloat16. (TUPLE_ENTRY): Add tuple vector_type information for BFloat16. (cherry picked from commit 666f167bec09d1234e6496c86b566fe1a71f61f0) Diff: --- gcc/config/riscv/genrvv-type-indexer.cc | 115 +++ gcc/config/riscv/riscv-modes.def | 30 +- gcc/config/riscv/riscv-vector-builtins-types.def | 50 ++ gcc/config/riscv/riscv-vector-builtins.cc| 7 +- gcc/config/riscv/riscv-vector-builtins.def | 55 ++- gcc/config/riscv/riscv-vector-builtins.h | 1 + gcc/config/riscv/riscv-vector-switch.def | 36 +++ 7 files changed, 291 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/genrvv-type-indexer.cc b/gcc/config/riscv/genrvv-type-indexer.cc index 27cbd14982c..8626ddeaaa8 100644 --- a/gcc/config/riscv/genrvv-type-indexer.cc +++ b/gc
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add Zvfbfmin and Zvfbfwma intrinsic
https://gcc.gnu.org/g:21c85f996289427e61ae22eec8061620cc562d8c
commit 21c85f996289427e61ae22eec8061620cc562d8c
Author: Feng Wang
Date: Mon Jun 17 01:59:57 2024 +
RISC-V: Add Zvfbfmin and Zvfbfwma intrinsic
v3: Modify warning message in riscv.cc
v2: Rebase
Accroding to the intrinsic doc, the 'Zvfbfmin' and 'Zvfbfwma' intrinsic
functions are added by this patch.
Signed-off-by: Feng Wang
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (class vfncvtbf16_f):
Add 'Zvfbfmin' intrinsic in bases.
(class vfwcvtbf16_f): Ditto.
(class vfwmaccbf16): Add 'Zvfbfwma' intrinsic in bases.
(BASE): Add BASE macro for 'Zvfbfmin' and 'Zvfbfwma'.
* config/riscv/riscv-vector-builtins-bases.h: Add declaration for
'Zvfbfmin' and 'Zvfbfwma'.
* config/riscv/riscv-vector-builtins-functions.def
(REQUIRED_EXTENSIONS):
Add builtins def for 'Zvfbfmin' and 'Zvfbfwma'.
(vfncvtbf16_f): Ditto.
(vfncvtbf16_f_frm): Ditto.
(vfwcvtbf16_f): Ditto.
(vfwmaccbf16): Ditto.
(vfwmaccbf16_frm): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (supports_vectype_p):
Add vector intrinsic build judgment for BFloat16.
(build_all): Ditto.
(BASE_NAME_MAX_LEN): Adjust max length.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_F32_OPS):
Add new operand type for BFloat16.
(vfloat32mf2_t): Ditto.
(vfloat32m1_t): Ditto.
(vfloat32m2_t): Ditto.
(vfloat32m4_t): Ditto.
(vfloat32m8_t): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_F32_OPS): Ditto.
(validate_instance_type_required_extensions):
Add required_ext checking for 'Zvfbfmin' and 'Zvfbfwma'.
* config/riscv/riscv-vector-builtins.h (enum required_ext):
Add required_ext declaration for 'Zvfbfmin' and 'Zvfbfwma'.
(reqired_ext_to_isa_name): Ditto.
(required_extensions_specified): Ditto.
(struct function_group_info): Add match case for 'Zvfbfmin' and
'Zvfbfwma'.
* config/riscv/riscv.cc (riscv_validate_vector_type):
Add required_ext checking for 'Zvfbfmin' and 'Zvfbfwma'.
(cherry picked from commit 281f021ed4fbf9c2336048e34b6b40c6f7119baa)
Diff:
---
gcc/config/riscv/riscv-vector-builtins-bases.cc| 69 ++
gcc/config/riscv/riscv-vector-builtins-bases.h | 7 +++
.../riscv/riscv-vector-builtins-functions.def | 15 +
gcc/config/riscv/riscv-vector-builtins-shapes.cc | 31 +-
gcc/config/riscv/riscv-vector-builtins-types.def | 13
gcc/config/riscv/riscv-vector-builtins.cc | 67 +
gcc/config/riscv/riscv-vector-builtins.h | 34 +++
gcc/config/riscv/riscv.cc | 13 ++--
8 files changed, 232 insertions(+), 17 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 6483faba39c..193392fbcc2 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2417,6 +2417,60 @@ public:
}
};
+/* Implements vfncvtbf16_f. */
+template
+class vfncvtbf16_f : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override
+ {
+return FRM_OP == HAS_FRM;
+ }
+
+ bool may_require_frm_p () const override { return true; }
+
+ rtx expand (function_expander &e) const override
+ {
+return e.use_exact_insn (code_for_pred_trunc_to_bf16 (e.vector_mode ()));
+ }
+};
+
+/* Implements vfwcvtbf16_f. */
+class vfwcvtbf16_f : public function_base
+{
+public:
+ rtx expand (function_expander &e) const override
+ {
+return e.use_exact_insn (code_for_pred_extend_bf16_to (e.vector_mode ()));
+ }
+};
+
+/* Implements vfwmaccbf16. */
+template
+class vfwmaccbf16 : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override
+ {
+return FRM_OP == HAS_FRM;
+ }
+
+ bool may_require_frm_p () const override { return true; }
+
+ bool has_merge_operand_p () const override { return false; }
+
+ rtx expand (function_expander &e) const override
+ {
+if (e.op_info->op == OP_TYPE_vf)
+ return e.use_widen_ternop_insn (
+ code_for_pred_widen_bf16_mul_scalar (e.vector_mode ()));
+if (e.op_info->op == OP_TYPE_vv)
+ return e.use_widen_ternop_insn (
+ code_for_pred_widen_bf16_mul (e.vector_mode ()));
+gcc_unreachable ();
+ }
+};
+
static CONSTEXPR const vsetvl vsetvl_obj;
static CONSTEXPR const vsetvl vsetvlmax_obj;
static CONSTEXPR const loadstore vle_obj;
@@ -2734,6 +2788,14 @@ static CONSTEXPR const crypto_vv
vsm4r_obj;
static CONSTEXPR const vsm3me vsm3me_obj;
static CONSTEXPR const vaeskf2_vsm3c vs
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add md files for vector BFloat16
https://gcc.gnu.org/g:ae8af3ab0ae12793d35d37d9744f3cd0ceaa98b3 commit ae8af3ab0ae12793d35d37d9744f3cd0ceaa98b3 Author: Feng Wang Date: Tue Jun 18 06:13:35 2024 + RISC-V: Add md files for vector BFloat16 V3: Add Bfloat16 vector insn in generic-vector-ooo.md v2: Rebase Accroding to the BFloat16 spec, some vector iterators and new pattern are added in md files. Signed-off-by: Feng Wang gcc/ChangeLog: * config/riscv/generic-vector-ooo.md: Add def_insn_reservation for vector BFloat16. * config/riscv/riscv.md: Add new insn name for vector BFloat16. * config/riscv/vector-iterators.md: Add some iterators for vector BFloat16. * config/riscv/vector.md: Add some attribute for vector BFloat16. * config/riscv/vector-bfloat16.md: New file. Add insn pattern vector BFloat16. (cherry picked from commit 9f521632dd9ce71ce28ff1da9c161f76bc20fe3e) Diff: --- gcc/config/riscv/generic-vector-ooo.md | 4 +- gcc/config/riscv/riscv.md | 13 ++- gcc/config/riscv/vector-bfloat16.md| 135 ++ gcc/config/riscv/vector-iterators.md | 169 - gcc/config/riscv/vector.md | 103 +--- 5 files changed, 407 insertions(+), 17 deletions(-) diff --git a/gcc/config/riscv/generic-vector-ooo.md b/gcc/config/riscv/generic-vector-ooo.md index 5e933c83841..efe6bc41e86 100644 --- a/gcc/config/riscv/generic-vector-ooo.md +++ b/gcc/config/riscv/generic-vector-ooo.md @@ -53,7 +53,7 @@ (define_insn_reservation "vec_fcmp" 3 (eq_attr "type" "vfrecp,vfminmax,vfcmp,vfsgnj,vfclass,vfcvtitof,\ vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\ - vfncvtftoi,vfncvtftof") + vfncvtftoi,vfncvtftof,vfncvtbf16,vfwcvtbf16") "vxu_ooo_issue,vxu_ooo_alu") ;; Vector integer multiplication. @@ -69,7 +69,7 @@ ;; Vector float multiplication and FMA. (define_insn_reservation "vec_fmul" 6 - (eq_attr "type" "vfmul,vfwmul,vfmuladd,vfwmuladd") + (eq_attr "type" "vfmul,vfwmul,vfmuladd,vfwmuladd,vfwmaccbf16") "vxu_ooo_issue,vxu_ooo_alu") ;; Vector crypto, assumed to be a generic operation for now. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 5dee837a587..379015c60de 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -200,6 +200,7 @@ RVVMF64BI,RVVMF32BI,RVVMF16BI,RVVMF8BI,RVVMF4BI,RVVMF2BI,RVVM1BI, RVVM8QI,RVVM4QI,RVVM2QI,RVVM1QI,RVVMF2QI,RVVMF4QI,RVVMF8QI, RVVM8HI,RVVM4HI,RVVM2HI,RVVM1HI,RVVMF2HI,RVVMF4HI, + RVVM8BF,RVVM4BF,RVVM2BF,RVVM1BF,RVVMF2BF,RVVMF4BF, RVVM8HF,RVVM4HF,RVVM2HF,RVVM1HF,RVVMF2HF,RVVMF4HF, RVVM8SI,RVVM4SI,RVVM2SI,RVVM1SI,RVVMF2SI, RVVM8SF,RVVM4SF,RVVM2SF,RVVM1SF,RVVMF2SF, @@ -219,6 +220,11 @@ RVVM2x4HI,RVVM1x4HI,RVVMF2x4HI,RVVMF4x4HI, RVVM2x3HI,RVVM1x3HI,RVVMF2x3HI,RVVMF4x3HI, RVVM4x2HI,RVVM2x2HI,RVVM1x2HI,RVVMF2x2HI,RVVMF4x2HI, + RVVM1x8BF,RVVMF2x8BF,RVVMF4x8BF,RVVM1x7BF,RVVMF2x7BF, + RVVMF4x7BF,RVVM1x6BF,RVVMF2x6BF,RVVMF4x6BF,RVVM1x5BF, + RVVMF2x5BF,RVVMF4x5BF,RVVM2x4BF,RVVM1x4BF,RVVMF2x4BF, + RVVMF4x4BF,RVVM2x3BF,RVVM1x3BF,RVVMF2x3BF,RVVMF4x3BF, + RVVM4x2BF,RVVM2x2BF,RVVM1x2BF,RVVMF2x2BF,RVVMF4x2BF, RVVM1x8HF,RVVMF2x8HF,RVVMF4x8HF,RVVM1x7HF,RVVMF2x7HF, RVVMF4x7HF,RVVM1x6HF,RVVMF2x6HF,RVVMF4x6HF,RVVM1x5HF, RVVMF2x5HF,RVVMF4x5HF,RVVM2x4HF,RVVM1x4HF,RVVMF2x4HF, @@ -462,6 +468,10 @@ ;; vsm4rcrypto vector SM4 Rounds instructions ;; vsm3me crypto vector SM3 Message Expansion instructions ;; vsm3ccrypto vector SM3 Compression instructions +;; 18.Vector BF16 instrctions +;; vfncvtbf16 vector narrowing single floating-point to brain floating-point instruction +;; vfwcvtbf16 vector widening brain floating-point to single floating-point instruction +;; vfwmaccbf16 vector BF16 widening multiply-accumulate (define_attr "type" "unknown,branch,jump,jalr,ret,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, @@ -483,7 +493,7 @@ vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down, vgather,vcompress,vmov,vector,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpop,vrol,vror,vwsll, vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz, - vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c" + vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,vfncvtbf16,vfwcvtbf16,vfwmaccbf16" (cond [(eq_attr "got" "load") (const_string "load") ;; If a doubleword move uses these expensive instructions, @@ -4373,6 +4383,7 @@ (include "generic-ooo.md") (include "vector.md") (include "vector-crypto.md") +(include "vector-bfloat16.md") (include "zicond.md") (include "sfb.md") (include "zc.md") diff --git a/gcc/config/riscv/vector-bfloat16.md b/gcc/config/riscv/vector-bfloat16.md new file mode 100644 index 000..562aa8ee5ed --- /dev/null +++ b/gcc/con
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement locality for __builtin_prefetch
https://gcc.gnu.org/g:5975c3c8d167f4e0f41893ed90334a1aaef91441
commit 5975c3c8d167f4e0f41893ed90334a1aaef91441
Author: Monk Chiang
Date: Thu Jul 6 14:05:17 2023 +0800
RISC-V: Implement locality for __builtin_prefetch
The patch add the Zihintntl instructions in the prefetch pattern.
Zicbop has prefetch instructions. Zihintntl has NTL instructions.
Insert NTL instructions before prefetch instruction, if target
has Zihintntl extension.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_print_operand): Add 'L' letter
to print zihintntl instructions string.
* config/riscv/riscv.md (prefetch): Add zihintntl instructions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/prefetch-zicbop.c: New test.
* gcc.target/riscv/prefetch-zihintntl.c: New test.
(cherry picked from commit bf26413fc4081dfd18b915580b35bdb71481327e)
Diff:
---
gcc/config/riscv/riscv.cc | 22 ++
gcc/config/riscv/riscv.md | 10 +++---
gcc/testsuite/gcc.target/riscv/prefetch-zicbop.c | 20
.../gcc.target/riscv/prefetch-zihintntl.c | 20
4 files changed, 69 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 04c0faacef7..2d6269704ac 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -6497,6 +6497,7 @@ riscv_asm_output_opcode (FILE *asm_out_file, const char
*p)
'A' Print the atomic operation suffix for memory model OP.
'I' Print the LR suffix for memory model OP.
'J' Print the SC suffix for memory model OP.
+ 'L' Print a non-temporal locality hints instruction.
'z' Print x0 if OP is zero, otherwise print OP normally.
'i' Print i if the operand is not a register.
'S' Print shift-index of single-bit mask OP.
@@ -6691,6 +6692,27 @@ riscv_print_operand (FILE *file, rtx op, int letter)
break;
}
+case 'L':
+ {
+ const char *ntl_hint = NULL;
+ switch (INTVAL (op))
+ {
+ case 0:
+ ntl_hint = "ntl.all";
+ break;
+ case 1:
+ ntl_hint = "ntl.pall";
+ break;
+ case 2:
+ ntl_hint = "ntl.p1";
+ break;
+ }
+
+ if (ntl_hint)
+ asm_fprintf (file, "%s\n\t", ntl_hint);
+ break;
+ }
+
case 'i':
if (code != REG)
fputs ("i", file);
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 379015c60de..46c46039c33 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -4113,12 +4113,16 @@
{
switch (INTVAL (operands[1]))
{
-case 0: return "prefetch.r\t%a0";
-case 1: return "prefetch.w\t%a0";
+case 0: return TARGET_ZIHINTNTL ? "%L2prefetch.r\t%a0" : "prefetch.r\t%a0";
+case 1: return TARGET_ZIHINTNTL ? "%L2prefetch.w\t%a0" : "prefetch.w\t%a0";
default: gcc_unreachable ();
}
}
- [(set_attr "type" "store")])
+ [(set_attr "type" "store")
+ (set (attr "length") (if_then_else (and (match_test "TARGET_ZIHINTNTL")
+ (match_test "IN_RANGE (INTVAL
(operands[2]), 0, 2)"))
+ (const_string "8")
+ (const_string "4")))])
(define_insn "riscv_prefetchi_"
[(unspec_volatile:X [(match_operand:X 0 "address_operand" "r")
diff --git a/gcc/testsuite/gcc.target/riscv/prefetch-zicbop.c
b/gcc/testsuite/gcc.target/riscv/prefetch-zicbop.c
new file mode 100644
index 000..0faa120f1f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/prefetch-zicbop.c
@@ -0,0 +1,20 @@
+/* { dg-do compile target { { rv64-*-*}}} */
+/* { dg-options "-march=rv64gc_zicbop -mabi=lp64" } */
+
+void foo (char *p)
+{
+ __builtin_prefetch (p, 0, 0);
+ __builtin_prefetch (p, 0, 1);
+ __builtin_prefetch (p, 0, 2);
+ __builtin_prefetch (p, 0, 3);
+ __builtin_prefetch (p, 1, 0);
+ __builtin_prefetch (p, 1, 1);
+ __builtin_prefetch (p, 1, 2);
+ __builtin_prefetch (p, 1, 3);
+}
+
+/* { dg-final { scan-assembler-not "ntl.all\t" } } */
+/* { dg-final { scan-assembler-not "ntl.pall\t" } } */
+/* { dg-final { scan-assembler-not "ntl.p1\t" } } */
+/* { dg-final { scan-assembler-times "prefetch.r" 4 } } */
+/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c
b/gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c
new file mode 100644
index 000..78a3afe6833
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c
@@ -0,0 +1,20 @@
+/* { dg-do compile target { { rv64-*-*}}} */
+/* { dg-options "-march=rv64gc_zicbop_zihintntl -mabi=lp64" } */
+
+void foo (char *p)
+{
+ __builtin_prefetch (p, 0, 0);
+ __builtin_prefetch (p, 0, 1);
+ __builtin_prefetch (p, 0, 2);
+ __builtin_prefetch (p, 0, 3);
+ __builtin_prefetch (p, 1, 0);
+ __bui
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix testcase for vector .SAT_SUB in zip benchmark
https://gcc.gnu.org/g:25e37abccfcdd4604e5d917d98d537aa33a53a82
commit 25e37abccfcdd4604e5d917d98d537aa33a53a82
Author: Edwin Lu
Date: Fri Jul 12 11:31:16 2024 -0700
RISC-V: Fix testcase for vector .SAT_SUB in zip benchmark
The following testcase was not properly testing anything due to an
uninitialized variable. As a result, the loop was not iterating through
the testing data, but instead on undefined values which could cause an
unexpected abort.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h:
initialize variable
Signed-off-by: Edwin Lu
(cherry picked from commit 4306f76192bc7ab71c5997a7e2c95320505029ab)
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h | 1 +
1 file changed, 1 insertion(+)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h
index d238c6392de..309d63377d5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h
@@ -9,6 +9,7 @@ main ()
for (i = 0; i < sizeof (DATA) / sizeof (DATA[0]); i++)
{
+ d = DATA[i];
RUN_BINARY_VX (&d.x[N], d.b, N);
for (k = 0; k < N; k++)
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Attribute parser: Use alloca() instead of new + std::unique_ptr
https://gcc.gnu.org/g:894c444b23ca83d8333cc0a475545099c2ffa8d4
commit 894c444b23ca83d8333cc0a475545099c2ffa8d4
Author: Christoph Müllner
Date: Fri Jul 5 04:48:15 2024 +0200
RISC-V: Attribute parser: Use alloca() instead of new + std::unique_ptr
Allocating an object on the heap with new, wrapping it in a
std::unique_ptr and finally getting the buffer via buf.get()
is a correct way to allocate a buffer that is automatically
freed on return. However, a simple invocation of alloca()
does the same with less overhead.
gcc/ChangeLog:
* config/riscv/riscv-target-attr.cc
(riscv_target_attr_parser::parse_arch):
Replace new + std::unique_ptr by alloca().
(riscv_process_one_target_attr): Likewise.
(riscv_process_target_attr): Likewise.
Signed-off-by: Christoph Müllner
(cherry picked from commit 5040c273484d7123a40a99cdeb434cecbd17a2e9)
Diff:
---
gcc/config/riscv/riscv-target-attr.cc | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/riscv-target-attr.cc
b/gcc/config/riscv/riscv-target-attr.cc
index 1645a669217..57235c9c0a7 100644
--- a/gcc/config/riscv/riscv-target-attr.cc
+++ b/gcc/config/riscv/riscv-target-attr.cc
@@ -101,8 +101,7 @@ riscv_target_attr_parser::parse_arch (const char *str)
{
/* Parsing the extension list like "+[,+]*". */
size_t len = strlen (str);
- std::unique_ptr buf (new char[len+1]);
- char *str_to_check = buf.get ();
+ char *str_to_check = (char *) alloca (len + 1);
strcpy (str_to_check, str);
const char *token = strtok_r (str_to_check, ",", &str_to_check);
const char *local_arch_str = global_options.x_riscv_arch_string;
@@ -254,8 +253,7 @@ riscv_process_one_target_attr (char *arg_str,
return false;
}
- std::unique_ptr buf (new char[len+1]);
- char *str_to_check = buf.get();
+ char *str_to_check = (char *) alloca (len + 1);
strcpy (str_to_check, arg_str);
char *arg = strchr (str_to_check, '=');
@@ -341,8 +339,7 @@ riscv_process_target_attr (tree args, location_t loc)
return false;
}
- std::unique_ptr buf (new char[len+1]);
- char *str_to_check = buf.get ();
+ char *str_to_check = (char *) alloca (len + 1);
strcpy (str_to_check, TREE_STRING_POINTER (args));
/* Used to catch empty spaces between semi-colons i.e.
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Rewrite target attribute handling
https://gcc.gnu.org/g:9fb79576bb1a0a31e31a50436e99a9507021aed4 commit 9fb79576bb1a0a31e31a50436e99a9507021aed4 Author: Christoph Müllner Date: Sat Jun 22 21:59:04 2024 +0200 RISC-V: Rewrite target attribute handling The target-arch attribute handling in RISC-V is only a few months old, but already saw a rewrite (9941f0295a14), which addressed an important issue. This rewrite introduced a hash table in the backend, which is used to keep track of target-arch attributes of all functions. The index of this hash table is the pointer to the function declaration object (fndecl). However, objects like these don't have the lifetime that is assumed here, which resulted in observing two fndecl objects with the same address for different objects (triggering the assertion in riscv_func_target_put() -- see also PR115562). This patch removes the hash table approach in favor of storing target specific options using the DECL_FUNCTION_SPECIFIC_TARGET() macro, which is also used by other backends and is specifically designed for this purpose (https://gcc.gnu.org/onlinedocs/gccint/Function-Properties.html). To have an accessible field in the target options, we need to adjust riscv.opt and introduce the field riscv_arch_string (for the already existing option '-march='). Using this macro allows to remove much code from riscv-common.cc, which controls access to the objects 'func_target_table' and 'current_subset_list'. One thing to mention is, that we had two subset lists: current_subset_list and cmdline_subset_list, with the latter being introduced recently for target attribute handling. This patch reduces them back to one (cmdline_subset_list) which contains the list of extensions that have been enabled by the command line arguments. Note that the patch keeps the existing behavior of rejecting duplications of extensions when added via the '+' operator in a function target attribute. E.g. "-march=rv64gc_zbb" and "arch=+zbb" will trigger an error (see pr115554.c). However, at the same time this patch breaks the acceptance of adding implied extensions, which causes the following six regressions (with the error "extension 'EXT' appear more than one time"): * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-39.c * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-42.c * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-43.c * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-44.c * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-45.c * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-46.c New tests were added to document the behavior and to ensure it won't regress. This patch did not show any regressions for rv32/rv64 and fixes the ICEs from PR115554 and PR115562. PR target/115554 PR target/115562 gcc/ChangeLog: * common/config/riscv/riscv-common.cc (struct riscv_func_target_info): Remove. (struct riscv_func_target_hasher): Likewise. (riscv_func_decl_hash): Likewise. (riscv_func_target_hasher::hash): Likewise. (riscv_func_target_hasher::equal): Likewise. (riscv_current_subset_list): Likewise. (riscv_cmdline_subset_list): Remove obsolete space. (riscv_func_target_table_lazy_init): Remove. (riscv_func_target_get): Likewise. (riscv_func_target_put): Likewise. (riscv_func_target_remove_and_destory): Likewise. (riscv_arch_str): Generate from cmdline_subset_list. (riscv_set_arch_by_subset_list): Don't set current_subset_list. (riscv_parse_arch_string): Remove current_subset_list. * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Get subset list via riscv_cmdline_subset_list(). * config/riscv/riscv-subset.h (riscv_current_subset_list): Remove prototype. (riscv_func_target_get): Likewise. (riscv_func_target_put): Likewise. (riscv_func_target_remove_and_destory): Likewise. * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch): Build base arch string from existing target options, if any. (riscv_target_attr_parser::update_settings): Store new arch string in target options. (riscv_process_one_target_attr): Whitespace fix. (riscv_process_target_attr): Drop opts argument. (riscv_option_valid_attribute_p): Properly save, change and restore target options. * config/riscv/riscv.cc (get_arch_str): New function. (riscv_declare_function_name): Get arch string for option-arch directive from function's target options. *
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Allow adding enabled extension via target arch attributes
https://gcc.gnu.org/g:0315d0f04f07ff89c6af32212f9f6bdc0a94d21d
commit 0315d0f04f07ff89c6af32212f9f6bdc0a94d21d
Author: Christoph Müllner
Date: Sat Jul 6 17:03:18 2024 +0200
RISC-V: Allow adding enabled extension via target arch attributes
The set of enabled extensions can be extended via target arch function
attributes by listing each extension with a '+' prefix and a comma as
list separator. E.g.:
__attribute__((target("arch=+zba,+zbb"))) void foo();
The programmer intends to ensure that one or more extensions
are enabled when building the code. This is independent of the arch
string that is passed at build time via the -march= option.
Therefore, it is reasonable to allow enabling extensions via target arch
attributes, which have already been enabled via the -march= string.
The subset list code already supports such duplication for implied
extensions. This patch adds an interface so the subset list
parser can be switched into a mode where duplication is allowed.
This commit fixes the following regressed test cases:
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-39.c
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-42.c
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-43.c
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-44.c
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-45.c
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-46.c
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (riscv_subset_list::add):
Allow adding enabled extension if m_allow_adding_dup is set.
* config/riscv/riscv-subset.h: Add m_allow_adding_dup and setter.
* config/riscv/riscv-target-attr.cc
(riscv_target_attr_parser::parse_arch):
Allow adding enabled extensions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr115554.c: Change expected fail to expected
pass.
* gcc.target/riscv/target-attr-16.c: New test.
Signed-off-by: Christoph Müllner
(cherry picked from commit 61c21a719e205f70bd046c6a0275d1a3fd6341a4)
Diff:
---
gcc/config/riscv/riscv-subset.h | 3 +++
gcc/testsuite/gcc.target/riscv/target-attr-16.c | 4 ++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-subset.h
index 4d2bf9d9201..ed7ca4d44fd 100644
--- a/gcc/config/riscv/riscv-subset.h
+++ b/gcc/config/riscv/riscv-subset.h
@@ -68,6 +68,9 @@ private:
/* Number of subsets. */
unsigned m_subset_num;
+ /* Allow adding the same extension more than once. */
+ bool m_allow_adding_dup;
+
riscv_subset_list (const char *, location_t);
const char *parsing_subset_version (const char *, const char *, unsigned *,
diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-16.c
b/gcc/testsuite/gcc.target/riscv/target-attr-16.c
index 81ef2d72792..1c7badccdee 100644
--- a/gcc/testsuite/gcc.target/riscv/target-attr-16.c
+++ b/gcc/testsuite/gcc.target/riscv/target-attr-16.c
@@ -24,5 +24,5 @@ void bar (void)
{
}
-/* { dg-final { scan-assembler-times ".option arch,
rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zba1p0_zbb1p0" 4 {
target { rv32 } } } } */
-/* { dg-final { scan-assembler-times ".option arch,
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zba1p0_zbb1p0" 4 {
target { rv64 } } } } */
+/* { dg-final { scan-assembler-times ".option arch,
rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0"
4 { target { rv32 } } } } */
+/* { dg-final { scan-assembler-times ".option arch,
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0"
4 { target { rv64 } } } } */
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Revert "RISC-V: Attribute parser: Use alloca() instead of new + std::unique_ptr"
https://gcc.gnu.org/g:820041b0a5f4e6c3ecc8cabf16a409fe37a4b29d
commit 820041b0a5f4e6c3ecc8cabf16a409fe37a4b29d
Author: Christoph Müllner
Date: Mon Jul 15 23:42:39 2024 +0200
Revert "RISC-V: Attribute parser: Use alloca() instead of new +
std::unique_ptr"
This reverts commit 5040c273484d7123a40a99cdeb434cecbd17a2e9.
(cherry picked from commit eb0c163aada970b8351067b17121f013fc58dbc9)
Diff:
---
gcc/config/riscv/riscv-target-attr.cc | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv-target-attr.cc
b/gcc/config/riscv/riscv-target-attr.cc
index 57235c9c0a7..1645a669217 100644
--- a/gcc/config/riscv/riscv-target-attr.cc
+++ b/gcc/config/riscv/riscv-target-attr.cc
@@ -101,7 +101,8 @@ riscv_target_attr_parser::parse_arch (const char *str)
{
/* Parsing the extension list like "+[,+]*". */
size_t len = strlen (str);
- char *str_to_check = (char *) alloca (len + 1);
+ std::unique_ptr buf (new char[len+1]);
+ char *str_to_check = buf.get ();
strcpy (str_to_check, str);
const char *token = strtok_r (str_to_check, ",", &str_to_check);
const char *local_arch_str = global_options.x_riscv_arch_string;
@@ -253,7 +254,8 @@ riscv_process_one_target_attr (char *arg_str,
return false;
}
- char *str_to_check = (char *) alloca (len + 1);
+ std::unique_ptr buf (new char[len+1]);
+ char *str_to_check = buf.get();
strcpy (str_to_check, arg_str);
char *arg = strchr (str_to_check, '=');
@@ -339,7 +341,8 @@ riscv_process_target_attr (tree args, location_t loc)
return false;
}
- char *str_to_check = (char *) alloca (len + 1);
+ std::unique_ptr buf (new char[len+1]);
+ char *str_to_check = buf.get ();
strcpy (str_to_check, TREE_STRING_POINTER (args));
/* Used to catch empty spaces between semi-colons i.e.
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Fix liveness computation for shift/rotate counts in ext-dce
https://gcc.gnu.org/g:6e008e50050b6bcb0706f9f9e305fa17c4265142 commit 6e008e50050b6bcb0706f9f9e305fa17c4265142 Author: Jeff Law Date: Mon Jul 15 18:15:33 2024 -0600 Fix liveness computation for shift/rotate counts in ext-dce So as I've noted before I believe the control flow in ext-dce.cc is horribly messy. While investigating a fix for 115877 I came across another problem related to control flow handling. Specifically, if we have an binary op which implies the 2nd operand is fully live, then we'd actually fail to mark that operand as live. We essentially broke out of the loop which was supposed to be safe. But Y was a REG and if Y is a REG or CONST_INT we skip sub-rtxs and thus failed to process that operand (the shift count) at all. Rather than muck around with control flow, we can just set all the bits as live in DST_MASK and let normal processing continue. With all the bits live IN DST_MASK all the bits implied by the mode of the argument will also be live. No testcase. Bootstrapped and regression tested on x86. Pushing to the trunk. gcc/ * ext-dce.cc (ext_dce_process_uses): Simplify control flow and fix liveness computation for shift/rotate counts. (cherry picked from commit b31b8af807f5459674b0b310cb62a5bc81b676e7) Diff: --- gcc/ext-dce.cc | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/gcc/ext-dce.cc b/gcc/ext-dce.cc index 91789d283fc..7ecb99fef81 100644 --- a/gcc/ext-dce.cc +++ b/gcc/ext-dce.cc @@ -632,10 +632,11 @@ ext_dce_process_uses (rtx_insn *insn, rtx obj, bitmap live_tmp) else if (!CONSTANT_P (y)) break; - /* We might have (ashift (const_int 1) (reg...)) */ - /* XXX share this logic with code below. */ + /* We might have (ashift (const_int 1) (reg...)) +By setting dst_mask we can continue iterating on the +the next operand and it will be considered fully live. */ if (binop_implies_op2_fully_live (GET_CODE (src))) - break; + dst_mask = -1; /* If this was anything but a binary operand, break the inner loop. This is conservatively correct as it will cause the
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Add debug counter for ext_dce
https://gcc.gnu.org/g:0af6332920c401a77feee16dcad16015b4f8e065
commit 0af6332920c401a77feee16dcad16015b4f8e065
Author: Andrew Pinski
Date: Tue Jul 16 09:53:20 2024 -0700
Add debug counter for ext_dce
Like r15-1610-gb6215065a5b143 (which adds one for late_combine),
adding one for ext_dce is useful to debug some issues with this pass.
Bootstrapped and tested on x86_64-linux-gnu with no regressions.
gcc/ChangeLog:
* dbgcnt.def (ext_dce): New debug counter.
* ext-dce.cc (ext_dce_try_optimize_insn): Reject the insn
if the debug counter says so.
(ext_dce): Rename to ...
(ext_dce_execute): This.
(pass_ext_dce::execute): Update for the name of ext_dce.
Signed-off-by: Andrew Pinski
(cherry picked from commit 7c3287f3613210d4f98c8095bc739bea6582bfbb)
Diff:
---
gcc/dbgcnt.def | 1 +
gcc/ext-dce.cc | 16 +---
2 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/gcc/dbgcnt.def b/gcc/dbgcnt.def
index ed9f062eac2..4e7aaeae2da 100644
--- a/gcc/dbgcnt.def
+++ b/gcc/dbgcnt.def
@@ -162,6 +162,7 @@ DEBUG_COUNTER (dom_unreachable_edges)
DEBUG_COUNTER (dse)
DEBUG_COUNTER (dse1)
DEBUG_COUNTER (dse2)
+DEBUG_COUNTER (ext_dce)
DEBUG_COUNTER (form_fma)
DEBUG_COUNTER (gcse2_delete)
DEBUG_COUNTER (gimple_unroll)
diff --git a/gcc/ext-dce.cc b/gcc/ext-dce.cc
index 7ecb99fef81..7270de2a3bf 100644
--- a/gcc/ext-dce.cc
+++ b/gcc/ext-dce.cc
@@ -33,6 +33,7 @@ along with GCC; see the file COPYING3. If not see
#include "rtl-iter.h"
#include "df.h"
#include "print-rtl.h"
+#include "dbgcnt.h"
/* These should probably move into a C++ class. */
static vec livein;
@@ -312,6 +313,15 @@ ext_dce_try_optimize_insn (rtx_insn *insn, rtx set)
print_rtl_single (dump_file, SET_SRC (set));
}
+ /* We decided to turn do the optimization but allow it to be rejected for
+ bisection purposes. */
+ if (!dbg_cnt (::ext_dce))
+{
+ if (dump_file)
+ fprintf (dump_file, "Rejected due to debug counter.\n");
+ return;
+}
+
new_pattern = simplify_gen_subreg (GET_MODE (src), inner,
GET_MODE (inner), 0);
/* simplify_gen_subreg may fail in which case NEW_PATTERN will be NULL.
@@ -881,8 +891,8 @@ static bool ext_dce_rd_confluence_n (edge) { return true; }
are never read. Turn such extensions into SUBREGs instead which
can often be propagated away. */
-static void
-ext_dce (void)
+void
+ext_dce_execute (void)
{
df_analyze ();
ext_dce_init ();
@@ -929,7 +939,7 @@ public:
virtual bool gate (function *) { return flag_ext_dce && optimize > 0; }
virtual unsigned int execute (function *)
{
- ext_dce ();
+ ext_dce_execute ();
return 0;
}
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix testcase missing arch attribute
https://gcc.gnu.org/g:f2048cdfc401782a93585cf2ae9383941b8bb67b
commit f2048cdfc401782a93585cf2ae9383941b8bb67b
Author: Edwin Lu
Date: Tue Jul 16 17:43:45 2024 -0700
RISC-V: Fix testcase missing arch attribute
The C + F extention implies the zcf extension on rv32. Add missing zcf
extension for the rv32 target.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/target-attr-16.c: Update expected assembly
Signed-off-by: Edwin Lu
(cherry picked from commit 5bb01e91d40c34e8f8230b142f7ebff3d6aa88d1)
Diff:
---
gcc/testsuite/gcc.target/riscv/target-attr-16.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-16.c
b/gcc/testsuite/gcc.target/riscv/target-attr-16.c
index 1c7badccdee..c6b626d0c6c 100644
--- a/gcc/testsuite/gcc.target/riscv/target-attr-16.c
+++ b/gcc/testsuite/gcc.target/riscv/target-attr-16.c
@@ -24,5 +24,5 @@ void bar (void)
{
}
-/* { dg-final { scan-assembler-times ".option arch,
rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0"
4 { target { rv32 } } } } */
+/* { dg-final { scan-assembler-times ".option arch,
rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0"
4 { target { rv32 } } } } */
/* { dg-final { scan-assembler-times ".option arch,
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0"
4 { target { rv64 } } } } */
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PR rtl-optimization/115877] Fix livein computation for ext-dce
https://gcc.gnu.org/g:16ec69161c3a3537076cea467e3622bb4a2550d0
commit 16ec69161c3a3537076cea467e3622bb4a2550d0
Author: Jeff Law
Date: Sun Jul 21 07:36:37 2024 -0600
[PR rtl-optimization/115877] Fix livein computation for ext-dce
So I'm not yet sure how I'm going to break everything down, but this is easy
enough to break out as 1/N of ext-dce fixes/improvements.
When handling uses in an insn, we first determine what bits are set in the
destination which is represented in DST_MASK. Then we use that to refine
what
bits are live in the source operands.
In the source operand handling section we *modify* DST_MASK if the source
operand is a SUBREG (ugh!). So if the first operand is a SUBREG, then we
can
incorrectly compute which bit groups are live in the second operand,
especially
if it is a SUBREG as well.
This was seen when testing a larger set of patches on the rl78 port
(builtin-arith-overflow-p-7 & pr71631 execution failures), so no new test
for
this bugfix.
Run through my tester (in conjunction with other ext-dce changes) on the
various cross targets. Run individually through a bootstrap and regression
test cycle on x86_64 as well.
Pushing to the trunk.
PR rtl-optimization/115877
gcc/
* ext-dce.cc (ext_dce_process_uses): Restore the value of DST_MASK
for reach operand.
(cherry picked from commit 91e468b72dafc9dcd5dcf7915f1d0ef172264d53)
Diff:
---
gcc/ext-dce.cc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/gcc/ext-dce.cc b/gcc/ext-dce.cc
index 7270de2a3bf..d431f8ac12d 100644
--- a/gcc/ext-dce.cc
+++ b/gcc/ext-dce.cc
@@ -591,8 +591,10 @@ ext_dce_process_uses (rtx_insn *insn, rtx obj, bitmap
live_tmp)
making things live. Breaking from this loop will cause
the iterator to work on sub-rtxs, so it is safe to break
if we see something we don't know how to handle. */
+ unsigned HOST_WIDE_INT save_mask = dst_mask;
for (;;)
{
+ dst_mask = save_mask;
/* Strip an outer paradoxical subreg. The bits outside
the inner mode are don't cares. So we can just strip
and process the inner object. */
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PR rtl-optimization/115877][2/n] Improve liveness computation for constant initialization
https://gcc.gnu.org/g:1a05bff037dd32f73e1135d4ba2737167104c528
commit 1a05bff037dd32f73e1135d4ba2737167104c528
Author: Jeff Law
Date: Sun Jul 21 08:41:28 2024 -0600
[PR rtl-optimization/115877][2/n] Improve liveness computation for constant
initialization
While debugging pr115877, I noticed we were failing to remove the
destination
register from LIVENOW bitmap when it was set to a constant value. ie (set
(dest) (const_int)). This was a trivial oversight in
safe_for_live_propagation.
I don't have an example of this affecting code generation, but it certainly
could. More importantly, by making LIVENOW more accurate it's easier to
debug
when LIVENOW differs from expectations.
As with the prior patch this has been tested as part of a larger patchset
with
the crosses as well as individually on x86_64.
Pushing to the trunk,
PR rtl-optimization/115877
gcc/
* ext-dce.cc (safe_for_live_propagation): Handle RTX_CONST_OBJ.
(cherry picked from commit 9d8ef2711dfecd093077aef6123d9e93ea23454e)
Diff:
---
gcc/ext-dce.cc | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/ext-dce.cc b/gcc/ext-dce.cc
index d431f8ac12d..59bcc4572d5 100644
--- a/gcc/ext-dce.cc
+++ b/gcc/ext-dce.cc
@@ -69,6 +69,7 @@ safe_for_live_propagation (rtx_code code)
switch (GET_RTX_CLASS (code))
{
case RTX_OBJ:
+ case RTX_CONST_OBJ:
return true;
case RTX_COMPARE:
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Rearrange the test helper files for vector .SAT_*
https://gcc.gnu.org/g:cb6bdd5811aed672c32b92263e8c2c3cd24bd880 commit cb6bdd5811aed672c32b92263e8c2c3cd24bd880 Author: Pan Li Date: Sat Jul 20 10:43:44 2024 +0800 RISC-V: Rearrange the test helper files for vector .SAT_* Rearrange the test help header files, as well as align the name conventions. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_binary.h: Move to... * gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vvv_run.h: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_scalar.h: Move to... * gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vvx_run.h: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h: Move to... * gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx_run.h: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c: Adjust the include file names. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-10.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-11.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-12.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-13.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-14.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-15.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-16.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-17.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-18.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-19.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-20.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-21.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-22.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-23.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-24.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-25.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-26.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-27.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-28.c: Ditto.
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [NFC][PR rtl-optimization/115877] Avoid setting irrelevant bit groups as live in ext-dce
https://gcc.gnu.org/g:7c7b6fda23363220c874786ea0800b24a76fcd10
commit 7c7b6fda23363220c874786ea0800b24a76fcd10
Author: Jeff Law
Date: Mon Jul 22 08:45:10 2024 -0600
[NFC][PR rtl-optimization/115877] Avoid setting irrelevant bit groups as
live in ext-dce
Another patch to refine liveness computations. This should be NFC and is
designed to help debugging.
In simplest terms the patch avoids setting bit groups outside the size of a
pseudo as live. Consider a HImode pseudo, bits 16..63 for such a pseudo
don't
really have meaning, yet we often set bit groups related to bits 16.63 on in
the liveness bitmaps.
This makes debugging harder than it needs to be by simply having larger
bitmaps
to verify when walking through the code in a debugger.
This has been bootstrapped and regression tested on x86_64. It's also been
tested on the crosses in my tester without regressions.
Pushing to the trunk,
PR rtl-optimization/115877
gcc/
* ext-dce.cc (group_limit): New function.
(mark_reg_live): Likewise.
(ext_dce_process_sets): Use new functions.
(ext_dce_process_uses): Likewise.
(ext_dce_init): Likewise.
(cherry picked from commit 88d16194d0c8a6bdc2896c8944bfbf3e6038c9d2)
Diff:
---
gcc/ext-dce.cc | 64 +++---
1 file changed, 57 insertions(+), 7 deletions(-)
diff --git a/gcc/ext-dce.cc b/gcc/ext-dce.cc
index 59bcc4572d5..d1a31e1819e 100644
--- a/gcc/ext-dce.cc
+++ b/gcc/ext-dce.cc
@@ -48,6 +48,57 @@ static bool modify;
bit 16..31
bit 32..BITS_PER_WORD-1 */
+/* For the given REG, return the number of bit groups implied by the
+ size of the REG's mode, up to a maximum of 4 (number of bit groups
+ tracked by this pass).
+
+ For partial integer and variable sized modes also return 4. This
+ could possibly be refined for something like PSI mode, but it
+ does not seem worth the effort. */
+
+static int
+group_limit (const_rtx reg)
+{
+ machine_mode mode = GET_MODE (reg);
+
+ if (!GET_MODE_BITSIZE (mode).is_constant ())
+return 4;
+
+ int size = GET_MODE_SIZE (mode).to_constant ();
+
+ size = exact_log2 (size);
+
+ if (size < 0)
+return 4;
+
+ size++;
+ return (size > 4 ? 4 : size);
+}
+
+/* Make all bit groups live for REGNO in bitmap BMAP. For hard regs,
+ we assume all groups are live. For a pseudo we consider the size
+ of the pseudo to avoid creating unnecessarily live chunks of data. */
+
+static void
+make_reg_live (bitmap bmap, int regno)
+{
+ int limit;
+
+ /* For pseudos we can use the mode to limit how many bit groups
+ are marked as live since a pseudo only has one mode. Hard
+ registers have to be handled more conservatively. */
+ if (regno > FIRST_PSEUDO_REGISTER)
+{
+ rtx reg = regno_reg_rtx[regno];
+ limit = group_limit (reg);
+}
+ else
+limit = 4;
+
+ for (int i = 0; i < limit; i++)
+bitmap_set_bit (bmap, regno * 4 + i);
+}
+
/* Note this pass could be used to narrow memory loads too. It's
not clear if that's profitable or not in general. */
@@ -196,7 +247,8 @@ ext_dce_process_sets (rtx_insn *insn, rtx obj, bitmap
live_tmp)
/* Transfer all the LIVENOW bits for X into LIVE_TMP. */
HOST_WIDE_INT rn = REGNO (SUBREG_REG (x));
- for (HOST_WIDE_INT i = 4 * rn; i < 4 * rn + 4; i++)
+ int limit = group_limit (SUBREG_REG (x));
+ for (HOST_WIDE_INT i = 4 * rn; i < 4 * rn + limit; i++)
if (bitmap_bit_p (livenow, i))
bitmap_set_bit (live_tmp, i);
@@ -260,7 +312,8 @@ ext_dce_process_sets (rtx_insn *insn, rtx obj, bitmap
live_tmp)
/* Transfer the appropriate bits from LIVENOW into
LIVE_TMP. */
HOST_WIDE_INT rn = REGNO (x);
- for (HOST_WIDE_INT i = 4 * rn; i < 4 * rn + 4; i++)
+ int limit = group_limit (x);
+ for (HOST_WIDE_INT i = 4 * rn; i < 4 * rn + limit; i++)
if (bitmap_bit_p (livenow, i))
bitmap_set_bit (live_tmp, i);
@@ -692,7 +745,7 @@ ext_dce_process_uses (rtx_insn *insn, rtx obj, bitmap
live_tmp)
/* If we have a register reference that is not otherwise handled,
just assume all the chunks are live. */
else if (REG_P (x))
- bitmap_set_range (livenow, REGNO (x) * 4, 4);
+ bitmap_set_range (livenow, REGNO (x) * 4, group_limit (x));
}
}
@@ -819,10 +872,7 @@ ext_dce_init (void)
unsigned i;
bitmap_iterator bi;
EXECUTE_IF_SET_IN_BITMAP (refs, 0, i, bi)
-{
- for (int j = 0; j < 4; j++)
- bitmap_set_bit (&livein[EXIT_BLOCK], i * 4 + j);
-}
+make_reg_live (&livein[EXIT_BLOCK], i);
livenow = BITMAP_ALLOC (NULL);
all_blocks = BITMAP_ALLOC (NULL);
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [4/n][PR rtl-optimization/115877] Correct SUBREG handling in a destination
https://gcc.gnu.org/g:0d84f3d3150a72632293b3de0e2b97531615bd00
commit 0d84f3d3150a72632293b3de0e2b97531615bd00
Author: Jeff Law
Date: Mon Jul 22 10:11:57 2024 -0600
[4/n][PR rtl-optimization/115877] Correct SUBREG handling in a destination
If we encounter something during SET handling that we can not handle, the
safe
thing to do is to ignore the destination and continue the loop.
We've actually been trying to do slightly better with SUBREG destinations by
iterating into SUBREG_REG. It turns out that wasn't working as expected.
The problem is once we "continue" we lose the state that we were inside the
SET
and thus we ended up ignoring the destination completely rather than
tracking
the SUBREG_REG object. This could be fixed by restarting SET processing,
but I
just don't see this as all that important to handle. So rather than leave
the
code as-is, not working per design, I'm twiddling it to use the common 'skip
subrtxs and continue' idiom used elsewhere.
This is a prerequisite for another patch in this series. Specifically I
have a
patch that explicitly tracks if we skipped a destination rather than trying
to
imply it from the state of LIVE_TMP. So this is probably NFC right now, but
that's a short-lived NFC.
Bootstrapped and regression tested on x86 and also run as part of a larger
kit
on the crosses in my tester.
PR rtl-optimization/115877
gcc/
* ext-dce.cc (ext_dce_process_sets): More correctly handle SUBREG
destinations.
(cherry picked from commit ab7c0aed52054976d0b5e12c52e82239d4277b98)
Diff:
---
gcc/ext-dce.cc | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/gcc/ext-dce.cc b/gcc/ext-dce.cc
index d1a31e1819e..7f0a6d725f1 100644
--- a/gcc/ext-dce.cc
+++ b/gcc/ext-dce.cc
@@ -270,11 +270,18 @@ ext_dce_process_sets (rtx_insn *insn, rtx obj, bitmap
live_tmp)
= GET_MODE_MASK (GET_MODE_INNER (GET_MODE (x)));
if (SUBREG_P (x))
{
- /* If we have a SUBREG that is too wide, just continue the loop
-and let the iterator go down into SUBREG_REG. */
+ /* If we have a SUBREG destination that is too wide, just
+skip the destination rather than continuing this iterator.
+While continuing would be better, we'd need to strip the
+subreg and restart within the SET processing rather than
+the top of the loop which just complicates the flow even
+more. */
if (!is_a (GET_MODE (SUBREG_REG (x)),
&outer_mode)
|| GET_MODE_BITSIZE (outer_mode) > 64)
- continue;
+ {
+ iter.skip_subrtxes ();
+ continue;
+ }
/* We can safely strip a paradoxical subreg. The inner mode will
be narrower than the outer mode. We'll clear fewer bits in
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement the .SAT_TRUNC for scalar
https://gcc.gnu.org/g:eb6ee8d59d7000e2083a6be84ed2d34fd5b60e3d
commit eb6ee8d59d7000e2083a6be84ed2d34fd5b60e3d
Author: Pan Li
Date: Mon Jul 1 16:36:35 2024 +0800
RISC-V: Implement the .SAT_TRUNC for scalar
This patch would like to implement the simple .SAT_TRUNC pattern
in the riscv backend. Aka:
Form 1:
#define DEF_SAT_U_TRUC_FMT_1(NT, WT) \
NT __attribute__((noinline)) \
sat_u_truc_##WT##_to_##NT##_fmt_1 (WT x) \
{\
bool overflow = x > (WT)(NT)(-1); \
return ((NT)x) | (NT)-overflow;\
}
DEF_SAT_U_TRUC_FMT_1(uint32_t, uint64_t)
Before this patch:
__attribute__((noinline))
uint8_t sat_u_truc_uint16_t_to_uint8_t_fmt_1 (uint16_t x)
{
_Bool overflow;
unsigned char _1;
unsigned char _2;
unsigned char _3;
uint8_t _6;
;; basic block 2, loop depth 0
;;pred: ENTRY
overflow_5 = x_4(D) > 255;
_1 = (unsigned char) x_4(D);
_2 = (unsigned char) overflow_5;
_3 = -_2;
_6 = _1 | _3;
return _6;
;;succ: EXIT
}
After this patch:
__attribute__((noinline))
uint8_t sat_u_truc_uint16_t_to_uint8_t_fmt_1 (uint16_t x)
{
uint8_t _6;
;; basic block 2, loop depth 0
;;pred: ENTRY
_6 = .SAT_TRUNC (x_4(D)); [tail call]
return _6;
;;succ: EXIT
}
The below tests suites are passed for this patch
1. The rv64gcv fully regression test.
2. The rv64gcv build with glibc
gcc/ChangeLog:
* config/riscv/iterators.md (ANYI_DOUBLE_TRUNC): Add new iterator
for int double truncation.
(ANYI_DOUBLE_TRUNCATED): Add new attr for int double truncation.
(anyi_double_truncated): Ditto but for lowercase.
* config/riscv/riscv-protos.h (riscv_expand_ustrunc): Add new
func decl for expanding ustrunc
* config/riscv/riscv.cc (riscv_expand_ustrunc): Add new func
impl to expand ustrunc.
* config/riscv/riscv.md (ustrunc2):
Impl
the new pattern ustrunc2 for int.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add test helper macro.
* gcc.target/riscv/sat_arith_data.h: New test.
* gcc.target/riscv/sat_u_trunc-1.c: New test.
* gcc.target/riscv/sat_u_trunc-2.c: New test.
* gcc.target/riscv/sat_u_trunc-3.c: New test.
* gcc.target/riscv/sat_u_trunc-run-1.c: New test.
* gcc.target/riscv/sat_u_trunc-run-2.c: New test.
* gcc.target/riscv/sat_u_trunc-run-3.c: New test.
* gcc.target/riscv/scalar_sat_unary.h: New test.
Signed-off-by: Pan Li
(cherry picked from commit 5d2115b850df63b0ecdf56efb720ad848e7afe21)
Diff:
---
gcc/config/riscv/iterators.md | 10
gcc/config/riscv/riscv-protos.h| 1 +
gcc/config/riscv/riscv.cc | 40
gcc/config/riscv/riscv.md | 10
gcc/testsuite/gcc.target/riscv/sat_arith.h | 16 +++
gcc/testsuite/gcc.target/riscv/sat_arith_data.h| 56 ++
gcc/testsuite/gcc.target/riscv/sat_u_trunc-1.c | 17 +++
gcc/testsuite/gcc.target/riscv/sat_u_trunc-2.c | 20
gcc/testsuite/gcc.target/riscv/sat_u_trunc-3.c | 19
gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-1.c | 16 +++
gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-2.c | 16 +++
gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-3.c | 16 +++
gcc/testsuite/gcc.target/riscv/scalar_sat_unary.h | 22 +
13 files changed, 259 insertions(+)
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index d61ed53a8b1..734da041f0c 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -65,6 +65,16 @@
;; Iterator for hardware-supported integer modes.
(define_mode_iterator ANYI [QI HI SI (DI "TARGET_64BIT")])
+(define_mode_iterator ANYI_DOUBLE_TRUNC [HI SI (DI "TARGET_64BIT")])
+
+(define_mode_attr ANYI_DOUBLE_TRUNCATED [
+ (HI "QI") (SI "HI") (DI "SI")
+])
+
+(define_mode_attr anyi_double_truncated [
+ (HI "qi") (SI "hi") (DI "si")
+])
+
;; Iterator for hardware-supported floating-point modes.
(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT || TARGET_ZFINX")
(DF "TARGET_DOUBLE_FLOAT || TARGET_ZDINX")
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 7c0ea1b445b..ce5e38d3dbb 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -135,6 +135,7 @@ riscv_zcmp_valid_stack_adj_bytes_p (HOST_WIDE_INT, int);
extern void riscv_legitimize_poly_move (machine_mode, rtx, rtx, rtx);
extern void riscv_expand_usadd (rtx, rtx, rtx);
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [5/n][PR rtl-optimization/115877] Fix handling of input/output operands
https://gcc.gnu.org/g:bb7633d7de5bd5a0227cae624a7ee1a97a89c28a
commit bb7633d7de5bd5a0227cae624a7ee1a97a89c28a
Author: Jeff Law
Date: Mon Jul 22 21:48:28 2024 -0600
[5/n][PR rtl-optimization/115877] Fix handling of input/output operands
So in this patch we're correcting a failure to mark objects live in
scenarios
like
(set (dest) (plus (dest) (src))
When handling set pseudos, we transfer the liveness information from LIVENOW
into LIVE_TMP. LIVE_TMP is subsequently used to narrow what bit groups are
live for the inputs.
The first time we process the block we may not have DEST in the LIVENOW set
(it
may be live across the loop, but not live after the loop). Thus we can
totally
miss making certain objects live, resulting in incorrect code.
The fix is pretty simple. If LIVE_TMP is empty, then we should go ahead and
mark all the bit groups for the set object in LIVE_TMP. This also removes
an
invalid gcc_assert on the state of the liveness bitmaps.
This showed up on pru, rl78 and/or msp430 in the testsuite. So no new test.
Bootstrapped and regression tested on x86_64 and also run through my tester
on
all the cross platforms.
Pushing to the trunk.
PR rtl-optimization/115877
gcc/
* ext-dce.cc (ext_dce_process_sets): Reasonably handle input/output
operands.
(ext_dce_rd_transfer_n): Drop bogus assertion.
(cherry picked from commit ad642d2c950657539777ea436b787e7fff4ec09e)
Diff:
---
gcc/ext-dce.cc | 31 ++-
1 file changed, 26 insertions(+), 5 deletions(-)
diff --git a/gcc/ext-dce.cc b/gcc/ext-dce.cc
index 7f0a6d725f1..43d2447acb5 100644
--- a/gcc/ext-dce.cc
+++ b/gcc/ext-dce.cc
@@ -245,13 +245,25 @@ ext_dce_process_sets (rtx_insn *insn, rtx obj, bitmap
live_tmp)
continue;
}
- /* Transfer all the LIVENOW bits for X into LIVE_TMP. */
+ /* LIVE_TMP contains the set groups that are live-out and set in
+this insn. It is used to narrow the groups live-in for the
+inputs of this insn.
+
+The simple thing to do is mark all the groups as live, but
+that will significantly inhibit optimization.
+
+We also need to be careful in the case where we have an in-out
+operand. If we're not careful we'd clear LIVE_TMP
+incorrectly. */
HOST_WIDE_INT rn = REGNO (SUBREG_REG (x));
int limit = group_limit (SUBREG_REG (x));
for (HOST_WIDE_INT i = 4 * rn; i < 4 * rn + limit; i++)
if (bitmap_bit_p (livenow, i))
bitmap_set_bit (live_tmp, i);
+ if (bitmap_empty_p (live_tmp))
+ make_reg_live (live_tmp, rn);
+
/* The mode of the SUBREG tells us how many bits we can
clear. */
machine_mode mode = GET_MODE (x);
@@ -316,14 +328,25 @@ ext_dce_process_sets (rtx_insn *insn, rtx obj, bitmap
live_tmp)
/* Now handle the actual object that was changed. */
if (REG_P (x))
{
- /* Transfer the appropriate bits from LIVENOW into
-LIVE_TMP. */
+ /* LIVE_TMP contains the set groups that are live-out and set in
+this insn. It is used to narrow the groups live-in for the
+inputs of this insn.
+
+The simple thing to do is mark all the groups as live, but
+that will significantly inhibit optimization.
+
+We also need to be careful in the case where we have an in-out
+operand. If we're not careful we'd clear LIVE_TMP
+incorrectly. */
HOST_WIDE_INT rn = REGNO (x);
int limit = group_limit (x);
for (HOST_WIDE_INT i = 4 * rn; i < 4 * rn + limit; i++)
if (bitmap_bit_p (livenow, i))
bitmap_set_bit (live_tmp, i);
+ if (bitmap_empty_p (live_tmp))
+ make_reg_live (live_tmp, rn);
+
/* Now clear the bits known written by this instruction.
Note that BIT need not be a power of two, consider a
ZERO_EXTRACT destination. */
@@ -935,8 +958,6 @@ ext_dce_rd_transfer_n (int bb_index)
the generic dataflow code that something changed. */
if (!bitmap_equal_p (&livein[bb_index], livenow))
{
- gcc_assert (!bitmap_intersect_compl_p (&livein[bb_index], livenow));
-
bitmap_copy (&livein[bb_index], livenow);
return true;
}
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix snafu in SI mode splitters patch
https://gcc.gnu.org/g:bb13ddff10923828389cf21cdb4643aa6225b37c
commit bb13ddff10923828389cf21cdb4643aa6225b37c
Author: Vineet Gupta
Date: Tue Jul 23 15:12:11 2024 -0700
RISC-V: Fix snafu in SI mode splitters patch
SPEC2017 perlbench for RISC-V was broke as runtime output mismatch
failure.
> 3830: mbox2:
dWshe3Aa1EULre4CT5O/ErYFrk+o/EOoebA1kTVjQVQQH2EjT5fHcYnwjj2MdBmZu5y3Ce4Ei4QQZo/SNrry9g
>mbox2:
uuWPimQiU0D4UrwFP+LS0lFNph4qL43WV1A6T3tHleatIOUaHixhrJU9NoA2lc9KjwYpdEL0lNTXkvo8ymNHzA
> ^
> 3832: mbox3:
8f4jdv6GIf0lX3DcdwRdEm6/aZwnmGX6n86GzCvmkwTKFXQjwlwVHc8jy8XlcyiIPr3yXTkgVOiP3cRYvyYQPg
>mbox3:
9xQySgP6qbhfxl8Usu1WfGA5UhStB5AN31wueGM6OF4Jp59DkqJPu6ksGblOU5u0nQapQC1e9oYIs16a2mq2NA
> ^
> specdiff run completed
Edwin bisected this to 273f16a125c4 ("[v3][RISC-V] Handle bit
manipulation of SImode values") which had the operands swapped in one
of the new splitters introduced.
No test as reducer narrows it to down to the exact test introduced by
the original commit.
gcc/ChangeLog:
* config/riscv/bitmanip.md: Fix splitter.
Reported-by: Edwin Lu
Signed-off-by: Vineet Gupta
(cherry picked from commit 806927111cf388a2d8cd54072269601f677767cf)
Diff:
---
gcc/config/riscv/bitmanip.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 6b720992ca3..9fc5215d6e3 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -675,7 +675,7 @@
"#"
"&& reload_completed"
[(set (match_dup 4) (match_dup 2))
-(set (match_dup 4) (and:DI (not:DI (match_dup 4)) (match_dup 1)))
+(set (match_dup 4) (and:DI (not:DI (match_dup 1)) (match_dup 4)))
(set (match_dup 0) (any_or:DI (ashift:DI (const_int 1) (match_dup 5))
(match_dup 3)))]
{ operands[5] = gen_lowpart (QImode, operands[4]); }
[(set_attr "type" "bitmanip")])
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PR rtl-optimization/115877][6/n] Add testcase from pr115877
https://gcc.gnu.org/g:b95ba68bf28a28ec50c3fa96b1587cc9a97af4b9
commit b95ba68bf28a28ec50c3fa96b1587cc9a97af4b9
Author: Jeff Law
Date: Tue Jul 23 19:11:04 2024 -0600
[PR rtl-optimization/115877][6/n] Add testcase from pr115877
This just adds the testcase from pr115877. It's working now on the trunk.
I'm
not done with cleanups/bugfixing, but there's no reason to not have the
testcase installed at this point.
PR rtl-optimization/115877
gcc/testsuite
* gcc.dg/torture/pr115877.c: New test.
(cherry picked from commit f9a60d575f02822852aa22513c636be38f9c63ea)
Diff:
---
gcc/testsuite/gcc.dg/torture/pr115877.c | 20
1 file changed, 20 insertions(+)
diff --git a/gcc/testsuite/gcc.dg/torture/pr115877.c
b/gcc/testsuite/gcc.dg/torture/pr115877.c
new file mode 100644
index 000..432b1280b17
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/pr115877.c
@@ -0,0 +1,20 @@
+/* { dg-do run { target int128 } } */
+
+char a[16];
+unsigned short u;
+
+__int128
+foo (int i)
+{
+ i -= (unsigned short) ~u;
+ a[(unsigned short) i] = 1;
+ return i;
+}
+
+int
+main ()
+{
+ __int128 x = foo (0);
+ if (x != -0x)
+__builtin_abort();
+}
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [rtl-optimization/116037] Explicitly track if a destination was skipped in ext-dce
https://gcc.gnu.org/g:ecbda5a53e691ce963e82aff354f1a43df30d762
commit ecbda5a53e691ce963e82aff354f1a43df30d762
Author: Jeff Law
Date: Wed Jul 24 11:16:26 2024 -0600
[rtl-optimization/116037] Explicitly track if a destination was skipped in
ext-dce
So this has been in the hopper since the first bugs were reported against
ext-dce. It'd been holding off committing as I was finding other issues in
terms of correctness of live computations. There's still problems in that
space, but I think it's time to push this chunk forward. I'm marking it as
116037, but it may impact other bugs.
This patch starts explicitly tracking if set processing skipped a
destination,
which can happen for wide modes (TI+), vectors, certain subregs, etc. This
is
computed during ext_dce_set_processing.
During use processing we use that flag to determine reliably if we need to
make
the inputs fully live and to avoid even trying to eliminate an extension if
we
skipped output processing.
While testing this I found that a recent change to fix cases where we had
two
subreg input operands mucked up the code to make things like a shift/rotate
count fully live. So that goof has been fixed.
Bootstrapped and regression tested on x86. Most, but not all, of these
changes
have also been tested on the crosses. Pushing to the trunk.
I'm not including it in this patch but I'm poking at converting this code to
use note_uses/note_stores to make it more maintainable. The SUBREG and
STRICT_LOW_PART handling of note_stores is problematical, but I think it's
solvable. I haven't tried a conversion to note_uses yet.
PR rtl-optimization/116037
gcc/
* ext-dce.cc (ext_dce_process_sets): Note if we ever skip a dest
and return that info explicitly.
(ext_dce_process_uses): If a set was skipped, then consider all bits
in every input as live. Do not try to optimize away an extension if
we skipped processing a destination in the same insn. Restore code
to make shift/rotate count fully live.
(ext_dce_process_bb): Handle API changes for ext_dce_process_sets.
gcc/testsuite/
* gcc.dg/torture/pr116037.c: New test
(cherry picked from commit 679086172b84be18c55fdbb9cda7e97806e7c083)
Diff:
---
gcc/ext-dce.cc | 42 ++---
gcc/testsuite/gcc.dg/torture/pr116037.c | 36
2 files changed, 69 insertions(+), 9 deletions(-)
diff --git a/gcc/ext-dce.cc b/gcc/ext-dce.cc
index 43d2447acb5..08a8261d7c1 100644
--- a/gcc/ext-dce.cc
+++ b/gcc/ext-dce.cc
@@ -181,9 +181,11 @@ safe_for_live_propagation (rtx_code code)
within an object) are set by INSN, the more aggressive the
optimization phase during use handling will be. */
-static void
+static bool
ext_dce_process_sets (rtx_insn *insn, rtx obj, bitmap live_tmp)
{
+ bool skipped_dest = false;
+
subrtx_iterator::array_type array;
FOR_EACH_SUBRTX (iter, array, obj, NONCONST)
{
@@ -210,6 +212,7 @@ ext_dce_process_sets (rtx_insn *insn, rtx obj, bitmap
live_tmp)
/* Skip the subrtxs of this destination. There is
little value in iterating into the subobjects, so
just skip them for a bit of efficiency. */
+ skipped_dest = true;
iter.skip_subrtxes ();
continue;
}
@@ -241,6 +244,7 @@ ext_dce_process_sets (rtx_insn *insn, rtx obj, bitmap
live_tmp)
/* Skip the subrtxs of the STRICT_LOW_PART. We can't
process them because it'll set objects as no longer
live when they are in fact still live. */
+ skipped_dest = true;
iter.skip_subrtxes ();
continue;
}
@@ -291,6 +295,7 @@ ext_dce_process_sets (rtx_insn *insn, rtx obj, bitmap
live_tmp)
if (!is_a (GET_MODE (SUBREG_REG (x)),
&outer_mode)
|| GET_MODE_BITSIZE (outer_mode) > 64)
{
+ skipped_dest = true;
iter.skip_subrtxes ();
continue;
}
@@ -318,6 +323,7 @@ ext_dce_process_sets (rtx_insn *insn, rtx obj, bitmap
live_tmp)
remain the same. Thus we can not continue here, we must
either figure out what part of the destination is modified
or skip the sub-rtxs. */
+ skipped_dest = true;
iter.skip_subrtxes ();
continue;
}
@@ -370,9 +376,11 @@ ext_dce_process_sets (rtx_insn *insn, rtx obj, bitmap
live_tmp)
else if (GET_CODE (x) == COND_EXEC)
{
/* This isn't ideal, but may not be so bad in practice. */
+ skipped_dest = true;
iter.skip_subrtxes ();
}
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Allow LICM hoist POLY_INT configuration code sequence
https://gcc.gnu.org/g:78e0cd7d2e7f3a09d3ce08a407d91d16e9877246
commit 78e0cd7d2e7f3a09d3ce08a407d91d16e9877246
Author: Juzhe-Zhong
Date: Thu Feb 1 23:45:50 2024 +0800
RISC-V: Allow LICM hoist POLY_INT configuration code sequence
Realize in recent benchmark evaluation (coremark-pro zip-test):
vid.v v2
vmv.v.i v5,0
.L9:
vle16.v v3,0(a4)
vrsub.vxv4,v2,a6 ---> LICM failed to hoist it outside the
loop.
The root cause is:
(insn 56 47 57 4 (set (subreg:DI (reg:HI 220) 0)
(reg:DI 223)) "rvv.c":11:9 208 {*movdi_64bit} -> Its result used
by the following vrsub.vx then supress the hoist of the vrsub.vx
(nil))
(insn 57 56 59 4 (set (reg:RVVMF2HI 216)
(if_then_else:RVVMF2HI (unspec:RVVMF32BI [
(const_vector:RVVMF32BI repeat [
(const_int 1 [0x1])
])
(reg:DI 350)
(const_int 2 [0x2]) repeated x2
(const_int 1 [0x1])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(minus:RVVMF2HI (vec_duplicate:RVVMF2HI (reg:HI 220))
(reg:RVVMF2HI 217))
(unspec:RVVMF2HI [
(reg:DI 0 zero)
] UNSPEC_VUNDEF))) "rvv.c":11:9 6938
{pred_subrvvmf2hi_reverse_scalar}
(expr_list:REG_DEAD (reg:HI 220)
(nil)))
This patch fixes it generate (set (reg:HI) (subreg:HI (reg:DI))) instead of
(set (subreg:DI (reg:DI)) (reg:DI)).
After this patch:
vid.v v2
vrsub.vxv2,v2,a7
vmv.v.i v4,0
.L3:
vle16.v v3,0(a4)
Tested on both RV32 and RV64 no regression.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest
generation.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/poly_licm-1.c: New test.
* gcc.target/riscv/rvv/autovec/poly_licm-2.c: New test.
* gcc.target/riscv/rvv/autovec/poly_licm-3.c: New test.
(cherry picked from commit 4cbbce045681c234387d8d56376ea179dc869229)
Diff:
---
gcc/config/riscv/riscv.cc | 9
.../gcc.target/riscv/rvv/autovec/poly_licm-1.c | 18 +++
.../gcc.target/riscv/rvv/autovec/poly_licm-2.c | 27 ++
.../gcc.target/riscv/rvv/autovec/poly_licm-3.c | 26 +
4 files changed, 76 insertions(+), 4 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5935fb35028..847a85322d5 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3230,16 +3230,17 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx
src)
(const_poly_int:HI [m, n])
(const_poly_int:SI [m, n]). */
rtx tmp = gen_reg_rtx (Pmode);
- riscv_legitimize_poly_move (Pmode, gen_lowpart (Pmode, dest), tmp,
- src);
+ rtx tmp2 = gen_reg_rtx (Pmode);
+ riscv_legitimize_poly_move (Pmode, tmp2, tmp, src);
+ emit_move_insn (dest, gen_lowpart (mode, tmp2));
}
else
{
/* In RV32 system, handle (const_poly_int:SI [m, n])
(const_poly_int:DI [m, n]).
In RV64 system, handle (const_poly_int:DI [m, n]).
- FIXME: Maybe we could gen SImode in RV32 and then sign-extend to DImode,
- the offset should not exceed 4GiB in general. */
+FIXME: Maybe we could gen SImode in RV32 and then sign-extend to
+DImode, the offset should not exceed 4GiB in general. */
rtx tmp = gen_reg_rtx (mode);
riscv_legitimize_poly_move (mode, dest, tmp, src);
}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/poly_licm-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/poly_licm-1.c
new file mode 100644
index 000..b7da65f0996
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/poly_licm-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+extern int wsize;
+
+typedef unsigned short Posf;
+#define NIL 0
+
+void foo (Posf *p)
+{
+ register unsigned n, m;
+ do {
+ m = *--p;
+ *p = (Posf)(m >= wsize ? m-wsize : NIL);
+ } while (--n);
+}
+
+/* { dg-final { scan-assembler-times
{vid\.v\s+v[0-9]+\s+addi\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*-1\s+vrsub\.vx\s+} 1 }
} */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/poly_licm-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/poly_licm-2.c
new file mode 100644
index 000..ffb3c63149f
--- /dev/null
+++ b/gcc/testsuite/
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Error early with V and no M extension.
https://gcc.gnu.org/g:13370bdcaf62a62b59845f9c07c942df7c3a8bd3
commit 13370bdcaf62a62b59845f9c07c942df7c3a8bd3
Author: Robin Dapp
Date: Wed Jul 24 09:08:00 2024 +0200
RISC-V: Error early with V and no M extension.
For calculating the value of a poly_int at runtime we use a
multiplication instruction that requires the M extension.
Instead of just asserting and ICEing this patch emits an early
error at option-parsing time.
gcc/ChangeLog:
PR target/116036
* config/riscv/riscv.cc (riscv_override_options_internal): Error
with TARGET_VECTOR && !TARGET_MUL.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-31.c: Add m to arch string and expect it.
* gcc.target/riscv/arch-32.c: Ditto.
* gcc.target/riscv/arch-37.c: Ditto.
* gcc.target/riscv/arch-38.c: Ditto.
* gcc.target/riscv/predef-14.c: Ditto.
* gcc.target/riscv/predef-15.c: Ditto.
* gcc.target/riscv/predef-16.c: Ditto.
* gcc.target/riscv/predef-26.c: Ditto.
* gcc.target/riscv/predef-27.c: Ditto.
* gcc.target/riscv/predef-32.c: Ditto.
* gcc.target/riscv/predef-33.c: Ditto.
* gcc.target/riscv/predef-36.c: Ditto.
* gcc.target/riscv/predef-37.c: Ditto.
* gcc.target/riscv/rvv/autovec/pr111486.c: Add m to arch string.
* gcc.target/riscv/compare-debug-1.c: Ditto.
* gcc.target/riscv/compare-debug-2.c: Ditto.
* gcc.target/riscv/rvv/base/pr116036.c: New test.
(cherry picked from commit e589ffb6d78881572ddea21df0d9b6c2641d574d)
Diff:
---
gcc/config/riscv/riscv.cc | 5 +
gcc/testsuite/gcc.target/riscv/arch-31.c | 2 +-
gcc/testsuite/gcc.target/riscv/arch-32.c | 2 +-
gcc/testsuite/gcc.target/riscv/arch-37.c | 2 +-
gcc/testsuite/gcc.target/riscv/arch-38.c | 2 +-
gcc/testsuite/gcc.target/riscv/compare-debug-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/compare-debug-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/predef-14.c| 6 +++---
gcc/testsuite/gcc.target/riscv/predef-15.c| 4 ++--
gcc/testsuite/gcc.target/riscv/predef-16.c| 4 ++--
gcc/testsuite/gcc.target/riscv/predef-26.c| 6 +-
gcc/testsuite/gcc.target/riscv/predef-27.c| 6 +-
gcc/testsuite/gcc.target/riscv/predef-32.c| 6 +-
gcc/testsuite/gcc.target/riscv/predef-33.c| 6 +-
gcc/testsuite/gcc.target/riscv/predef-36.c| 6 +-
gcc/testsuite/gcc.target/riscv/predef-37.c| 6 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111486.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr116036.c| 11 +++
18 files changed, 60 insertions(+), 20 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 847a85322d5..e12096242f4 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9691,6 +9691,11 @@ riscv_override_options_internal (struct gcc_options
*opts)
else if (!TARGET_MUL_OPTS_P (opts) && TARGET_DIV_OPTS_P (opts))
error ("%<-mdiv%> requires %<-march%> to subsume the % extension");
+ /* We might use a multiplication to calculate the scalable vector length at
+ runtime. Therefore, require the M extension. */
+ if (TARGET_VECTOR && !TARGET_MUL)
+sorry ("GCC's current % implementation requires the % extension");
+
/* Likewise floating-point division and square root. */
if ((TARGET_HARD_FLOAT_OPTS_P (opts) || TARGET_ZFINX_OPTS_P (opts))
&& ((target_flags_explicit & MASK_FDIV) == 0))
diff --git a/gcc/testsuite/gcc.target/riscv/arch-31.c
b/gcc/testsuite/gcc.target/riscv/arch-31.c
index 5180753b905..9b867c5ecd2 100644
--- a/gcc/testsuite/gcc.target/riscv/arch-31.c
+++ b/gcc/testsuite/gcc.target/riscv/arch-31.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32i_zvfbfmin -mabi=ilp32f" } */
+/* { dg-options "-march=rv32im_zvfbfmin -mabi=ilp32f" } */
int foo()
{
}
diff --git a/gcc/testsuite/gcc.target/riscv/arch-32.c
b/gcc/testsuite/gcc.target/riscv/arch-32.c
index 49616832512..49a3db79489 100644
--- a/gcc/testsuite/gcc.target/riscv/arch-32.c
+++ b/gcc/testsuite/gcc.target/riscv/arch-32.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64iv_zvfbfmin -mabi=lp64d" } */
+/* { dg-options "-march=rv64imv_zvfbfmin -mabi=lp64d" } */
int foo()
{
}
diff --git a/gcc/testsuite/gcc.target/riscv/arch-37.c
b/gcc/testsuite/gcc.target/riscv/arch-37.c
index 5b19a73c556..b56ba77b973 100644
--- a/gcc/testsuite/gcc.target/riscv/arch-37.c
+++ b/gcc/testsuite/gcc.target/riscv/arch-37.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32i_zvfbfwma -mabi=ilp32f" } */
+/* { dg-options "-march=rv32im_zvfbfwma -mabi=ilp32f" } */
int
foo ()
{}
diff --git a/g
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] Trivial testcase adjustment
https://gcc.gnu.org/g:16d1997090340cd587c85450983bf545245dc5bf
commit 16d1997090340cd587c85450983bf545245dc5bf
Author: Jeff Law
Date: Thu Jul 25 08:42:04 2024 -0600
[committed] Trivial testcase adjustment
I made pr116037.c dependent on int32 just based on the constants used
without
noting the int128 vector type. Naturally on targets that don't support
int128
the test fails. Fixed by changing the target selector from int32 to int128.
Pushed to the trunk.
gcc/testsuite
* gcc.dg/torture/pr116037.c: Fix target selector.
(cherry picked from commit 2dd45655db47362153756261881413b368582597)
Diff:
---
gcc/testsuite/gcc.dg/torture/pr116037.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/torture/pr116037.c
b/gcc/testsuite/gcc.dg/torture/pr116037.c
index cb34ba4e5d4..86ab50de4b2 100644
--- a/gcc/testsuite/gcc.dg/torture/pr116037.c
+++ b/gcc/testsuite/gcc.dg/torture/pr116037.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-require-effective-target int32 } */
+/* { dg-require-effective-target int128 } */
/* { dg-additional-options "-Wno-psabi" } */
typedef __attribute__((__vector_size__ (64))) unsigned char VC;
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PR rtl-optimization/116039] Fix life computation for promoted subregs
https://gcc.gnu.org/g:7d226394382ff284f8c24cbbf6a677023b72111d
commit 7d226394382ff284f8c24cbbf6a677023b72111d
Author: Jeff Law
Date: Thu Jul 25 12:32:28 2024 -0600
[PR rtl-optimization/116039] Fix life computation for promoted subregs
So this turned out to be a neat little test and while the fuzzer found it on
RISC-V, I wouldn't be surprised if the underlying issue is also the root
cause
of the loongarch issue with ext-dce.
The key issue is that if we have something like
(set (dest) (any_extend (subreg (source
If the subreg object is marked with SUBREG_PROMOTED and the sign/unsigned
state
matches the any_extend opcode, then combine (and I guess anything using
simplify-rtx) may simplify that to
(set (dest) (source))
That implies that bits outside the mode of the subreg are actually live and
valid. This needs to be accounted for during liveness computation.
We have to be careful here though. If we're too conservative about setting
additional bits live, then we'll inhibit the desired optimization in the
coremark examples. To do a good job we need to know the extension opcode.
I'm extremely unhappy with how the use handling works in ext-dce. It mixes
different conceptual steps and has horribly complex control flow. It only
handles a subset of the unary/binary opcodes, etc etc. It's just damn mess.
It's going to need some more noodling around.
In the mean time this is a bit hacky in that it depends on non-obvious
behavior
to know it can get the extension opcode, but I don't want to leave the
trunk in
a broken state while I figure out the refactoring problem.
Bootstrapped and regression tested on x86 and tested on the crosses.
Pushing to the trunk.
PR rtl-optimization/116039
gcc/
* ext-dce.cc (ext_dce_process_uses): Add some comments about
concerns
with current code. Mark additional bit groups as live when we have
an extension of a suitably promoted subreg.
gcc/testsuite
* gcc.dg/torture/pr116039.c: New test.
(cherry picked from commit 34fb0feca71f763b2fbe832548749666d34a4a76)
Diff:
---
gcc/ext-dce.cc | 43 -
gcc/testsuite/gcc.dg/torture/pr116039.c | 20 +++
2 files changed, 57 insertions(+), 6 deletions(-)
diff --git a/gcc/ext-dce.cc b/gcc/ext-dce.cc
index 08a8261d7c1..2e371fefba0 100644
--- a/gcc/ext-dce.cc
+++ b/gcc/ext-dce.cc
@@ -667,6 +667,12 @@ ext_dce_process_uses (rtx_insn *insn, rtx obj,
if (modify && !skipped_dest && (dst_mask & ~src_mask) == 0)
ext_dce_try_optimize_insn (insn, x);
+ /* Stripping the extension here just seems wrong on multiple
+levels. It's source side handling, so it seems like it
+belongs in the loop below. Stripping here also makes it
+harder than necessary to properly handle live bit groups
+for (ANY_EXTEND (SUBREG)) where the SUBREG has
+SUBREG_PROMOTED state. */
dst_mask &= src_mask;
src = XEXP (src, 0);
code = GET_CODE (src);
@@ -674,8 +680,8 @@ ext_dce_process_uses (rtx_insn *insn, rtx obj,
/* Optimization is done at this point. We just want to make
sure everything that should get marked as live is marked
-from here onward. */
-
+from here onward. Shouldn't the backpropagate step happen
+before optimization? */
dst_mask = carry_backpropagate (dst_mask, code, src);
/* We will handle the other operand of a binary operator
@@ -688,7 +694,11 @@ ext_dce_process_uses (rtx_insn *insn, rtx obj,
/* We're inside a SET and want to process the source operands
making things live. Breaking from this loop will cause
the iterator to work on sub-rtxs, so it is safe to break
-if we see something we don't know how to handle. */
+if we see something we don't know how to handle.
+
+This code is just hokey as it really just handles trivial
+unary and binary cases. Otherwise the loop exits and we
+continue iterating on sub-rtxs, but outside the set context.
*/
unsigned HOST_WIDE_INT save_mask = dst_mask;
for (;;)
{
@@ -704,10 +714,26 @@ ext_dce_process_uses (rtx_insn *insn, rtx obj,
y = XEXP (y, 0);
else if (SUBREG_P (y) && SUBREG_BYTE (y).is_constant ())
{
- /* For anything but (subreg (reg)), break the inner loop
-and process normally (conservatively). */
- if (!RE
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Work around bare apostrophe in error string.
https://gcc.gnu.org/g:37cbd2160d01bea81623f1ca506b731ac0f36bbd
commit 37cbd2160d01bea81623f1ca506b731ac0f36bbd
Author: Robin Dapp
Date: Fri Jul 26 12:58:38 2024 +0200
RISC-V: Work around bare apostrophe in error string.
An unquoted apostrophe slipped through when testing the recent
V/M extension patch. This, again, re-words the message to
"Currently the 'V' implementation requires the 'M' extension".
Going to commit as obvious after testing.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_override_options_internal):
Reword error string without apostrophe.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr116036.c: Adjust expected error
string.
(cherry picked from commit 3f2bf415b447a0f6bc424c688b06e1f5946688a0)
Diff:
---
gcc/config/riscv/riscv.cc | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr116036.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e12096242f4..48a64f3e30d 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9694,7 +9694,7 @@ riscv_override_options_internal (struct gcc_options *opts)
/* We might use a multiplication to calculate the scalable vector length at
runtime. Therefore, require the M extension. */
if (TARGET_VECTOR && !TARGET_MUL)
-sorry ("GCC's current % implementation requires the % extension");
+sorry ("Currently the % implementation requires the % extension");
/* Likewise floating-point division and square root. */
if ((TARGET_HARD_FLOAT_OPTS_P (opts) || TARGET_ZFINX_OPTS_P (opts))
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116036.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116036.c
index a72209593f3..7b39291a91a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116036.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116036.c
@@ -8,4 +8,4 @@ void init() {
a[i_0][i_1] = 1;
}
-/* { dg-excess-errors "sorry, unimplemented: GCC's current 'V' implementation
requires the 'M' extension" } */
+/* { dg-excess-errors "sorry, unimplemented: Currently the 'V' implementation
requires the 'M' extension" } */
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V][target/116085] Fix rv64 minmax extension avoidance splitter
https://gcc.gnu.org/g:ed6d11c16d69b1cf388bfa6dbc00fa3b34ade969
commit ed6d11c16d69b1cf388bfa6dbc00fa3b34ade969
Author: Jeff Law
Date: Fri Jul 26 17:30:08 2024 -0600
[RISC-V][target/116085] Fix rv64 minmax extension avoidance splitter
A patch introduced a pattern to avoid unnecessary extensions when doing a
min/max operation where one of the values is a 32 bit positive constant.
> (define_insn_and_split "*minmax"
> [(set (match_operand:DI 0 "register_operand" "=r")
> (sign_extend:DI
> (subreg:SI
> (bitmanip_minmax:DI (zero_extend:DI (match_operand:SI 1
"register_operand" "r"))
> (match_operand:DI 2
"immediate_operand" "i"))
>0)))
>(clobber (match_scratch:DI 3 "=&r"))
>(clobber (match_scratch:DI 4 "=&r"))]
> "TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0"
> "#"
> "&& reload_completed"
> [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
>(set (match_dup 4) (match_dup 2))
>(set (match_dup 0) (:DI (match_dup 3) (match_dup 4)))]
Lots going on in here. The key is the nonconstant value is zero extended
from
SI to DI in the original RTL and we know the constant value is unchanged if
we
were to sign extend it from 32 to 64 bits.
We change the extension of the nonconstant operand from zero to sign
extension.
I'm pretty confident the goal there is take advantage of the fact that SI
values are kept sign extended and will often be optimized away.
The problem occurs when the nonconstant operand has the SI sign bit set.
As an
example:
smax (0x800, 0x7) resulting in 0x8000
The split RTL will generate
smax (sign_extend (0x8000), 0x7))
smax (0x8000, 0x7) resulting in 0x7
Opps.
We really needed to change the opcode to umax for this transformation to
work.
That's easy enough. But there's further improvements we can make.
First the pattern is a define_and_split with a post-reload split condition.
It
would be better implemented as a 4->3 define_split so that the costing model
just works. Second, if operands[1] is a suitably promoted subreg, then we
can
elide the sign extension when we generate the split code, so often it'll be
a
4->2 split, again with the cost model working with no adjustments needed.
Tested on rv32 and rv64 in my tester. I'll wait for the pre-commit tester
to
spin it as well.
PR target/116085
gcc/
* config/riscv/bitmanip.md (minmax extension avoidance splitter):
Rewrite as a simpler define_split. Adjust the opcode appropriately.
Avoid emitting sign extension if it's clearly not needed.
* config/riscv/iterators.md (minmax_optab): Rename to uminmax_optab
and map everything to unsigned variants.
gcc/testsuite/
* gcc.target/riscv/pr116085.c: New test.
(cherry picked from commit 6e5aae47e3b910f9af6983f744d7a3e2dcecba1d)
Diff:
---
gcc/config/riscv/bitmanip.md | 38 +++
gcc/config/riscv/iterators.md | 9
gcc/testsuite/gcc.target/riscv/pr116085.c | 29 +++
3 files changed, 58 insertions(+), 18 deletions(-)
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 9fc5215d6e3..b19295cd942 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -549,23 +549,33 @@
;; Optimize the common case of a SImode min/max against a constant
;; that is safe both for sign- and zero-extension.
-(define_insn_and_split "*minmax"
- [(set (match_operand:DI 0 "register_operand" "=r")
+(define_split
+ [(set (match_operand:DI 0 "register_operand")
(sign_extend:DI
(subreg:SI
- (bitmanip_minmax:DI (zero_extend:DI (match_operand:SI 1
"register_operand" "r"))
- (match_operand:DI 2
"immediate_operand" "i"))
- 0)))
- (clobber (match_scratch:DI 3 "=&r"))
- (clobber (match_scratch:DI 4 "=&r"))]
+ (bitmanip_minmax:DI (zero_extend:DI
+ (match_operand:SI 1 "register_operand"))
+ (match_operand:DI 2 "immediate_operand")) 0)))
+ (clobber (match_operand:DI 3 "register_operand"))
+ (clobber (match_operand:DI 4 "register_operand"))]
"TARGET_64BIT && TARGET_ZBB && sext_hwi (INTVAL (operands[2]), 32) >= 0"
- "#"
- "&& reload_completed"
- [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
- (set (match_dup 4) (match_dup 2))
- (set (match_dup 0) (:DI (match_dup 3) (match_dup 4)))]
- ""
- [(set_attr "type" "bitmanip")])
+ [(set (match_dup 0) (:DI (match_dup 4) (match_dup 3)))]
+ "
+{
+ /* Load the constant into a register. */
+ emit_move
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [target/116104] Fix test guarding UINTVAL to extract shift count
https://gcc.gnu.org/g:6ca3dabccff3d3cb8ea1a67be38373eebca521c4 commit 6ca3dabccff3d3cb8ea1a67be38373eebca521c4 Author: Jeff Law Date: Mon Jul 29 16:17:25 2024 -0600 [target/116104] Fix test guarding UINTVAL to extract shift count Minor oversight in the ext-dce bits. If the shift count is a constant vector, then we shouldn't be extracting values with [U]INTVAL. We guarded that test with CONSTANT_P, when it should have been CONSTANT_INT_P. Shows up on gcn, but I wouldn't be terribly surprised if it could be triggered elsewhere. Verified the testcase compiles on gcn. Haven't done a libgcc build for gcn though. Also verified x86 bootstraps and regression tests cleanly. Pushing to the trunk. PR target/116104 gcc/ * ext-dce.cc (carry_backpropagate): Fix test guarding UINTVAL extraction of shift count. (cherry picked from commit 5ab9a351247a551c47b0ab9d8e8b907223e7faf6) Diff: --- gcc/ext-dce.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/ext-dce.cc b/gcc/ext-dce.cc index 2e371fefba0..86d7f950e35 100644 --- a/gcc/ext-dce.cc +++ b/gcc/ext-dce.cc @@ -493,7 +493,7 @@ carry_backpropagate (unsigned HOST_WIDE_INT mask, enum rtx_code code, rtx x) /* We propagate for the shifted operand, but not the shift count. The count is handled specially. */ case ASHIFT: - if (CONSTANT_P (XEXP (x, 1)) + if (CONST_INT_P (XEXP (x, 1)) && known_lt (UINTVAL (XEXP (x, 1)), GET_MODE_BITSIZE (mode))) return mask >> INTVAL (XEXP (x, 1)); return (2ULL << floor_log2 (mask)) - 1;
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Remove configure check for zabha
https://gcc.gnu.org/g:b2df229aa9c1b5a9fb77c23456903cf911c5f838
commit b2df229aa9c1b5a9fb77c23456903cf911c5f838
Author: Patrick O'Neill
Date: Mon Jul 29 19:52:02 2024 -0700
RISC-V: Remove configure check for zabha
This patch removes the zabha configure check since it's not a breaking
change
and updates the existing zaamo/zalrsc comment.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
(riscv_subset_list::to_string): Remove zabha configure check
handling and clarify zaamo/zalrsc comment.
* config.in: Regenerate.
* configure: Regenerate.
* configure.ac: Remove zabha configure check.
Signed-off-by: Patrick O'Neill
(cherry picked from commit c0af64af636a801850fc8fabee12635ec73daa22)
Diff:
---
gcc/common/config/riscv/riscv-common.cc | 12 +++-
gcc/config.in | 6 --
gcc/configure | 31 ---
gcc/configure.ac| 5 -
4 files changed, 3 insertions(+), 51 deletions(-)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 682826c0e34..d2912877784 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -855,7 +855,6 @@ riscv_subset_list::to_string (bool version_p) const
bool skip_zifencei = false;
bool skip_zaamo_zalrsc = false;
- bool skip_zabha = false;
bool skip_zicsr = false;
bool i2p0 = false;
@@ -884,13 +883,11 @@ riscv_subset_list::to_string (bool version_p) const
skip_zifencei = true;
#endif
#ifndef HAVE_AS_MARCH_ZAAMO_ZALRSC
- /* Skip since binutils 2.42 and earlier don't recognize zaamo/zalrsc. */
+ /* Skip since binutils 2.42 and earlier don't recognize zaamo/zalrsc.
+ Expanding 'a' to zaamo/zalrsc would otherwise break compilations
+ for users with an older version of binutils. */
skip_zaamo_zalrsc = true;
#endif
-#ifndef HAVE_AS_MARCH_ZABHA
- /* Skip since binutils 2.42 and earlier don't recognize zabha. */
- skip_zabha = true;
-#endif
for (subset = m_head; subset != NULL; subset = subset->next)
{
@@ -908,9 +905,6 @@ riscv_subset_list::to_string (bool version_p) const
if (skip_zaamo_zalrsc && subset->name == "zalrsc")
continue;
- if (skip_zabha && subset->name == "zabha")
- continue;
-
/* For !version_p, we only separate extension with underline for
multi-letter extension. */
if (!first &&
diff --git a/gcc/config.in b/gcc/config.in
index 7f589b5a26f..e73f78d18c3 100644
--- a/gcc/config.in
+++ b/gcc/config.in
@@ -635,12 +635,6 @@
#endif
-/* Define if the assembler understands -march=rv*_zabha. */
-#ifndef USED_FOR_TARGET
-#undef HAVE_AS_MARCH_ZABHA
-#endif
-
-
/* Define if the assembler understands -march=rv*_zifencei. */
#ifndef USED_FOR_TARGET
#undef HAVE_AS_MARCH_ZIFENCEI
diff --git a/gcc/configure b/gcc/configure
index 70169c978e0..a994994eeef 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -31064,37 +31064,6 @@ if test $gcc_cv_as_riscv_march_zaamo_zalrsc = yes; then
$as_echo "#define HAVE_AS_MARCH_ZAAMO_ZALRSC 1" >>confdefs.h
-fi
-
-{ $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for
-march=rv32i_zabha support" >&5
-$as_echo_n "checking assembler for -march=rv32i_zabha support... " >&6; }
-if ${gcc_cv_as_riscv_march_zabha+:} false; then :
- $as_echo_n "(cached) " >&6
-else
- gcc_cv_as_riscv_march_zabha=no
- if test x$gcc_cv_as != x; then
-$as_echo '' > conftest.s
-if { ac_try='$gcc_cv_as $gcc_cv_as_flags -march=rv32i_zabha -o conftest.o
conftest.s >&5'
- { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
- (eval $ac_try) 2>&5
- ac_status=$?
- $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
- test $ac_status = 0; }; }
-then
- gcc_cv_as_riscv_march_zabha=yes
-else
- echo "configure: failed program was" >&5
- cat conftest.s >&5
-fi
-rm -f conftest.o conftest.s
- fi
-fi
-{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_riscv_march_zabha"
>&5
-$as_echo "$gcc_cv_as_riscv_march_zabha" >&6; }
-if test $gcc_cv_as_riscv_march_zabha = yes; then
-
-$as_echo "#define HAVE_AS_MARCH_ZABHA 1" >>confdefs.h
-
fi
;;
diff --git a/gcc/configure.ac b/gcc/configure.ac
index 4202491de97..7c026746c0f 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -5508,11 +5508,6 @@ configured with --enable-newlib-nano-formatted-io.])
[-march=rv32i_zaamo_zalrsc],,,
[AC_DEFINE(HAVE_AS_MARCH_ZAAMO_ZALRSC, 1,
[Define if the assembler understands
-march=rv*_zaamo_zalrsc.])])
-gcc_GAS_CHECK_FEATURE([-march=rv32i_zabha support],
- gcc_cv_as_riscv_march_zabha,
- [-march=rv32i_zabha],,,
- [AC_DEFINE(HAVE_AS_MARCH_ZABHA, 1,
-[Define if the assembler understands -march=rv*_zabha.])])
;;
loongarch*-*-*
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Take Xmode instead of Pmode for ussub expanding
https://gcc.gnu.org/g:6bf3d45cb3d7f54412fd17b7f9452e7ec52d7adf
commit 6bf3d45cb3d7f54412fd17b7f9452e7ec52d7adf
Author: Pan Li
Date: Tue Jul 30 13:56:40 2024 +0800
RISC-V: Take Xmode instead of Pmode for ussub expanding
The Pmode is designed for pointer, thus leverage the Xmode instead
for the expanding of the ussub.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_expand_ussub): Promote to Xmode
instead of Pmode.
Signed-off-by: Pan Li
(cherry picked from commit 85cff6e46d212240f9c15c2d7d614b6089be772a)
Diff:
---
gcc/config/riscv/riscv.cc | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 48a64f3e30d..bf0e0b8a0e7 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -11620,26 +11620,26 @@ void
riscv_expand_ussub (rtx dest, rtx x, rtx y)
{
machine_mode mode = GET_MODE (dest);
- rtx pmode_x = gen_lowpart (Pmode, x);
- rtx pmode_y = gen_lowpart (Pmode, y);
- rtx pmode_lt = gen_reg_rtx (Pmode);
- rtx pmode_minus = gen_reg_rtx (Pmode);
- rtx pmode_dest = gen_reg_rtx (Pmode);
+ rtx xmode_x = gen_lowpart (Xmode, x);
+ rtx xmode_y = gen_lowpart (Xmode, y);
+ rtx xmode_lt = gen_reg_rtx (Xmode);
+ rtx xmode_minus = gen_reg_rtx (Xmode);
+ rtx xmode_dest = gen_reg_rtx (Xmode);
/* Step-1: minus = x - y */
- riscv_emit_binary (MINUS, pmode_minus, pmode_x, pmode_y);
+ riscv_emit_binary (MINUS, xmode_minus, xmode_x, xmode_y);
/* Step-2: lt = x < y */
- riscv_emit_binary (LTU, pmode_lt, pmode_x, pmode_y);
+ riscv_emit_binary (LTU, xmode_lt, xmode_x, xmode_y);
/* Step-3: lt = lt - 1 (lt + (-1)) */
- riscv_emit_binary (PLUS, pmode_lt, pmode_lt, CONSTM1_RTX (Pmode));
+ riscv_emit_binary (PLUS, xmode_lt, xmode_lt, CONSTM1_RTX (Xmode));
- /* Step-4: pmode_dest = minus & lt */
- riscv_emit_binary (AND, pmode_dest, pmode_lt, pmode_minus);
+ /* Step-4: xmode_dest = minus & lt */
+ riscv_emit_binary (AND, xmode_dest, xmode_lt, xmode_minus);
- /* Step-5: dest = pmode_dest */
- emit_move_insn (dest, gen_lowpart (mode, pmode_dest));
+ /* Step-5: dest = xmode_dest */
+ emit_move_insn (dest, gen_lowpart (mode, xmode_dest));
}
/* Implement the unsigned saturation truncation for int mode.
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add basic support for the Zacas extension
https://gcc.gnu.org/g:cbaa7b2663e48ec9fafcad634a8e06c2aa1a32d0
commit cbaa7b2663e48ec9fafcad634a8e06c2aa1a32d0
Author: Gianluca Guida
Date: Mon Jul 29 15:13:46 2024 -0700
RISC-V: Add basic support for the Zacas extension
This patch adds support for amocas.{b|h|w|d}. Support for amocas.q
(64/128 bit cas for rv32/64) will be added in a future patch.
Extension: https://github.com/riscv/riscv-zacas
Ratification: https://jira.riscv.org/browse/RVS-680
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add zacas extension.
* config/riscv/arch-canonicalize: Make zacas imply zaamo.
* config/riscv/riscv.opt: Add zacas.
* config/riscv/sync.md (zacas_atomic_cas_value): New pattern.
(atomic_compare_and_swap): Use new pattern for
compare-and-swap ops.
(zalrsc_atomic_cas_value_strong): Rename
atomic_cas_value_strong.
* doc/sourcebuild.texi: Add Zacas documentation.
gcc/testsuite/ChangeLog:
* lib/target-supports.exp: Add zacas testsuite infra support.
*
gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c:
Remove zacas to continue to test the lr/sc pairs.
* gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c:
Ditto.
* gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c:
Ditto.
* gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c:
Ditto.
* gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c:
Ditto.
*
gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c: Ditto.
* gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c:
Ditto.
*
gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c: Ditto.
* gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c:
Ditto.
* gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c:
Ditto.
* gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c:
Ditto.
* gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c:
Ditto.
*
gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c: Ditto.
* gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c:
Ditto.
* gcc.target/riscv/amo/zabha-zacas-preferred-over-zalrsc.c: New
test.
* gcc.target/riscv/amo/zacas-char-requires-zabha.c: New test.
* gcc.target/riscv/amo/zacas-char-requires-zacas.c: New test.
* gcc.target/riscv/amo/zacas-preferred-over-zalrsc.c: New test.
* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acq-rel.c:
New test.
* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acquire.c:
New test.
* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-relaxed.c:
New test.
* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-release.c:
New test.
* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-seq-cst.c:
New test.
*
gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping-no-fence.c:
New test.
*
gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping.cc: New
test.
* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acq-rel.c:
New test.
* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acquire.c:
New test.
* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-relaxed.c:
New test.
* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-release.c:
New test.
* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-seq-cst.c:
New test.
*
gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acq-rel.c: New test.
*
gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acquire.c: New test.
*
gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-relaxed.c: New test.
*
gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-release.c: New test.
*
gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-seq-cst.c: New test.
* gcc.target/riscv/amo/zacas-ztso-compare-exchange-char-seq-cst.c:
New test.
* gcc.target/riscv/amo/zacas-ztso-compare-exchange-char.c: New test.
*
gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping-no-fence.c:
New test.
*
gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping.cc: New
test.
* gcc.target/riscv/amo/zacas-ztso-compare-exchange-int-seq-cst.c:
New test.
* gcc.target/riscv/amo/zacas-ztso-compare-exchange-int.c: New test.
* gcc.target/riscv/amo/zacas-ztso-compare-exchange-short-seq-cst.c:
New test.
* gcc.target/r
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add configure check for B extention support
https://gcc.gnu.org/g:463bd569ca686a364c0c3442b623759353d84d2f
commit 463bd569ca686a364c0c3442b623759353d84d2f
Author: Edwin Lu
Date: Wed Jul 24 16:37:18 2024 -0700
RISC-V: Add configure check for B extention support
Binutils 2.42 and before don't recognize the b extension in the march
strings even though it supports zba_zbb_zbs. Add a configure check to
ignore the b in the march string if found.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
(riscv_subset_list::to_string):
Skip b in march string
* config.in: Regenerate.
* configure: Regenerate.
* configure.ac: Add B assembler check
Signed-off-by: Edwin Lu
(cherry picked from commit 7ef8a9d4b1cea3fea3791859074df79b71abd549)
Diff:
---
gcc/common/config/riscv/riscv-common.cc | 8
gcc/config.in | 6 ++
gcc/configure | 31 +++
gcc/configure.ac| 5 +
4 files changed, 50 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 0c12e12cde5..1944c7785c4 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -858,6 +858,7 @@ riscv_subset_list::to_string (bool version_p) const
bool skip_zifencei = false;
bool skip_zaamo_zalrsc = false;
bool skip_zicsr = false;
+ bool skip_b = false;
bool i2p0 = false;
/* For RISC-V ISA version 2.2 or earlier version, zicsr and zifencei is
@@ -890,6 +891,10 @@ riscv_subset_list::to_string (bool version_p) const
for users with an older version of binutils. */
skip_zaamo_zalrsc = true;
#endif
+#ifndef HAVE_AS_MARCH_B
+ /* Skip since binutils 2.42 and earlier don't recognize b. */
+ skip_b = true;
+#endif
for (subset = m_head; subset != NULL; subset = subset->next)
{
@@ -907,6 +912,9 @@ riscv_subset_list::to_string (bool version_p) const
if (skip_zaamo_zalrsc && subset->name == "zalrsc")
continue;
+ if (skip_b && subset->name == "b")
+ continue;
+
/* For !version_p, we only separate extension with underline for
multi-letter extension. */
if (!first &&
diff --git a/gcc/config.in b/gcc/config.in
index e73f78d18c3..3e1ba00bb46 100644
--- a/gcc/config.in
+++ b/gcc/config.in
@@ -629,6 +629,12 @@
#endif
+/* Define if the assembler understands -march=rv*_b. */
+#ifndef USED_FOR_TARGET
+#undef HAVE_AS_MARCH_B
+#endif
+
+
/* Define if the assembler understands -march=rv*_zaamo_zalrsc. */
#ifndef USED_FOR_TARGET
#undef HAVE_AS_MARCH_ZAAMO_ZALRSC
diff --git a/gcc/configure b/gcc/configure
index a994994eeef..a1b6db56f69 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -31064,6 +31064,37 @@ if test $gcc_cv_as_riscv_march_zaamo_zalrsc = yes; then
$as_echo "#define HAVE_AS_MARCH_ZAAMO_ZALRSC 1" >>confdefs.h
+fi
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for
-march=rv32i_b support" >&5
+$as_echo_n "checking assembler for -march=rv32i_b support... " >&6; }
+if ${gcc_cv_as_riscv_march_b+:} false; then :
+ $as_echo_n "(cached) " >&6
+else
+ gcc_cv_as_riscv_march_b=no
+ if test x$gcc_cv_as != x; then
+$as_echo '' > conftest.s
+if { ac_try='$gcc_cv_as $gcc_cv_as_flags -march=rv32i_b -o conftest.o
conftest.s >&5'
+ { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+ test $ac_status = 0; }; }
+then
+ gcc_cv_as_riscv_march_b=yes
+else
+ echo "configure: failed program was" >&5
+ cat conftest.s >&5
+fi
+rm -f conftest.o conftest.s
+ fi
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_riscv_march_b" >&5
+$as_echo "$gcc_cv_as_riscv_march_b" >&6; }
+if test $gcc_cv_as_riscv_march_b = yes; then
+
+$as_echo "#define HAVE_AS_MARCH_B 1" >>confdefs.h
+
fi
;;
diff --git a/gcc/configure.ac b/gcc/configure.ac
index 7c026746c0f..07b5996d231 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -5508,6 +5508,11 @@ configured with --enable-newlib-nano-formatted-io.])
[-march=rv32i_zaamo_zalrsc],,,
[AC_DEFINE(HAVE_AS_MARCH_ZAAMO_ZALRSC, 1,
[Define if the assembler understands
-march=rv*_zaamo_zalrsc.])])
+gcc_GAS_CHECK_FEATURE([-march=rv32i_b support],
+ gcc_cv_as_riscv_march_b,
+ [-march=rv32i_b],,,
+ [AC_DEFINE(HAVE_AS_MARCH_B, 1,
+[Define if the assembler understands -march=rv*_b.])])
;;
loongarch*-*-*)
gcc_GAS_CHECK_FEATURE([.dtprelword support],
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PR rtl-optimization/116136] Fix previously latent SUBREG simplification bug
https://gcc.gnu.org/g:0476f5316e781a1ea0d7ef91ed654358f4bccd80 commit 0476f5316e781a1ea0d7ef91ed654358f4bccd80 Author: Jeff Law Date: Wed Jul 31 10:15:01 2024 -0600 [PR rtl-optimization/116136] Fix previously latent SUBREG simplification bug This fixes a testsuite regression seen on m68k after some of the recent ext-dce changes. Ultimately Richard S and I have concluded the bug was a latent issue in subreg simplification. Essentially when simplifying something like (set (target:M1) (subreg:M1 (subreg:M2 (reg:M1) 0) 0)) Where M1 > M2. We'd simplify to: (set (target:M1) (reg:M1)) The problem is on a big endian target that's wrong. Consider if M1 is DI and M2 is SI.The original should extract bits 32..63 from the source register and store them into bits 0..31 of the target register. In the simplified form it's just a copy, so bits 0..63 of the source end up bits 0..63 of the target. This shows up as the following regressions on the m68k: > Tests that now fail, but worked before (3 tests): > > gcc: gcc.c-torture/execute/960416-1.c -O2 execution test > gcc: gcc.c-torture/execute/960416-1.c -O2 -flto -fno-use-linker-plugin -flto-partition=none execution test > gcc: gcc.c-torture/execute/960416-1.c -Os execution test The fix is pretty trivial, instead of hardcoding "0" as the byte offset in the test for the simplification, instead we need to use the subreg_lowpart_offset. Anyway, bootstrapped and regression tested on m68k and x86_64 and tested on the other embedded targets as well without regressions. Naturally it fixes the regression noted above. I haven't see other testsuite improvements when I spot checked some of the big endian crosses. PR rtl-optimization/116136 gcc/ * simplify-rtx.cc (simplify_context::simplify_subreg): Check that we're working with the lowpart offset rather than byte 0. (cherry picked from commit 89ed5ab210b5e30c325b92e9e40c50e337be1b44) Diff: --- gcc/simplify-rtx.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc index 898ad8c2221..260c77584de 100644 --- a/gcc/simplify-rtx.cc +++ b/gcc/simplify-rtx.cc @@ -7672,8 +7672,9 @@ simplify_context::simplify_subreg (machine_mode outermode, rtx op, return NULL_RTX; if (outermode == innermostmode - && known_eq (byte, 0U) - && known_eq (SUBREG_BYTE (op), 0)) + && known_eq (byte, subreg_lowpart_offset (outermode, innermode)) + && known_eq (SUBREG_BYTE (op), + subreg_lowpart_offset (innermode, innermostmode))) return SUBREG_REG (op); /* Work out the memory offset of the final OUTERMODE value relative
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [target/116104] Fix more rtl-checking failures in ext-dce
https://gcc.gnu.org/g:9bdf6995bf4069c2e317b0490c9afa6302e8a037
commit 9bdf6995bf4069c2e317b0490c9afa6302e8a037
Author: Jeff Law
Date: Wed Jul 31 11:30:27 2024 -0600
[target/116104] Fix more rtl-checking failures in ext-dce
More enable-rtl-checking fixes for ext-dce. Very similar to the one
recently
posted, this time covering more of the shift ops.
I checked all instances of CONSTANT_P guarding [U]INTVAL and fixed all that
looked wrong. I also created a dummy assembler/linker so that I could run
the
GCC testsuite on gcn and verified that wasn't tripping any rtl-checking
bugs in
ext-dce anymore.
Obviously this has also gone through x86 bootstrap and regression tested.
Pushing to the trunk.
pr target/116104
gcc/
* ext-dce.cc (carry_backpropagate): Change more guards of [U]INTVAL
to
test CONST_INT_P rather than CONSTANT_P, fixing rtl-checking
failures.
(cherry picked from commit 69a9ee05c68bd1fe7f5b3be86baacc8f0a599915)
Diff:
---
gcc/ext-dce.cc | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/ext-dce.cc b/gcc/ext-dce.cc
index 86d7f950e35..fcbbf2da54d 100644
--- a/gcc/ext-dce.cc
+++ b/gcc/ext-dce.cc
@@ -501,7 +501,7 @@ carry_backpropagate (unsigned HOST_WIDE_INT mask, enum
rtx_code code, rtx x)
/* We propagate for the shifted operand, but not the shift
count. The count is handled specially. */
case LSHIFTRT:
- if (CONSTANT_P (XEXP (x, 1))
+ if (CONST_INT_P (XEXP (x, 1))
&& known_lt (UINTVAL (XEXP (x, 1)), GET_MODE_BITSIZE (mode)))
return mmask & (mask << INTVAL (XEXP (x, 1)));
return mmask;
@@ -509,7 +509,7 @@ carry_backpropagate (unsigned HOST_WIDE_INT mask, enum
rtx_code code, rtx x)
/* We propagate for the shifted operand, but not the shift
count. The count is handled specially. */
case ASHIFTRT:
- if (CONSTANT_P (XEXP (x, 1))
+ if (CONST_INT_P (XEXP (x, 1))
&& known_lt (UINTVAL (XEXP (x, 1)), GET_MODE_BITSIZE (mode)))
{
HOST_WIDE_INT sign = 0;
@@ -526,7 +526,7 @@ carry_backpropagate (unsigned HOST_WIDE_INT mask, enum
rtx_code code, rtx x)
return 0;
if (XEXP (x, 1) == const1_rtx)
return mmask;
- if (CONSTANT_P (XEXP (x, 1)))
+ if (CONST_INT_P (XEXP (x, 1)))
{
if (pow2p_hwi (INTVAL (XEXP (x, 1
return mmask & (mask << (GET_MODE_BITSIZE (mode).to_constant ()
@@ -549,7 +549,7 @@ carry_backpropagate (unsigned HOST_WIDE_INT mask, enum
rtx_code code, rtx x)
count. The count is handled specially. */
case SS_ASHIFT:
case US_ASHIFT:
- if (CONSTANT_P (XEXP (x, 1))
+ if (CONST_INT_P (XEXP (x, 1))
&& UINTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode).to_constant ())
{
return ((mmask & ~((unsigned HOST_WIDE_INT)mmask
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: NFC: Do not use zicond for pr105314 testcases
https://gcc.gnu.org/g:b6a1ecda25fc90724585f94eb618e7578722ea83
commit b6a1ecda25fc90724585f94eb618e7578722ea83
Author: Xiao Zeng
Date: Thu Jul 25 09:50:03 2024 +0800
RISC-V: NFC: Do not use zicond for pr105314 testcases
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr105314-rtl.c: Skip zicond.
* gcc.target/riscv/pr105314-rtl32.c: Ditto.
* gcc.target/riscv/pr105314.c: Ditto.
Signed-off-by: Xiao Zeng
(cherry picked from commit edad1b05010fedc7224515570592b2bd2153b21a)
Diff:
---
gcc/testsuite/gcc.target/riscv/pr105314-rtl.c | 2 +-
gcc/testsuite/gcc.target/riscv/pr105314-rtl32.c | 2 +-
gcc/testsuite/gcc.target/riscv/pr105314.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/pr105314-rtl.c
b/gcc/testsuite/gcc.target/riscv/pr105314-rtl.c
index 693291f4dbd..570918f9d9a 100644
--- a/gcc/testsuite/gcc.target/riscv/pr105314-rtl.c
+++ b/gcc/testsuite/gcc.target/riscv/pr105314-rtl.c
@@ -1,7 +1,7 @@
/* PR rtl-optimization/105314 */
/* { dg-do compile } */
/* { dg-require-effective-target rv64 } */
-/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" "-flto" } } */
+/* { dg-skip-if "" { *-*-* } { "-march=*zicond*" "-O0" "-Og" "-Os" "-Oz"
"-flto" } } */
/* { dg-options "-fdump-rtl-ce1" } */
long __RTL (startwith ("ce1"))
diff --git a/gcc/testsuite/gcc.target/riscv/pr105314-rtl32.c
b/gcc/testsuite/gcc.target/riscv/pr105314-rtl32.c
index 9f9600f7679..018b6c43095 100644
--- a/gcc/testsuite/gcc.target/riscv/pr105314-rtl32.c
+++ b/gcc/testsuite/gcc.target/riscv/pr105314-rtl32.c
@@ -1,7 +1,7 @@
/* PR rtl-optimization/105314 */
/* { dg-do compile } */
/* { dg-require-effective-target rv32 } */
-/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" "-flto" } } */
+/* { dg-skip-if "" { *-*-* } { "-march=*zicond*" "-O0" "-Og" "-Os" "-Oz"
"-flto" } } */
/* { dg-options "-fdump-rtl-ce1" } */
long __RTL (startwith ("ce1"))
diff --git a/gcc/testsuite/gcc.target/riscv/pr105314.c
b/gcc/testsuite/gcc.target/riscv/pr105314.c
index 1a7ea671791..75f6ecda2bb 100644
--- a/gcc/testsuite/gcc.target/riscv/pr105314.c
+++ b/gcc/testsuite/gcc.target/riscv/pr105314.c
@@ -1,6 +1,6 @@
/* PR rtl-optimization/105314 */
/* { dg-do compile } */
-/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-skip-if "" { *-*-* } { "-march=*zicond*" "-O0" "-Og" "-Os" "-Oz" } } */
/* { dg-options "-fdump-rtl-ce1" } */
long
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Correct mode_idx attribute for viwalu wx variants [PR116149].
https://gcc.gnu.org/g:b870cb81038f703c970ce4eb7c70991f544405b0
commit b870cb81038f703c970ce4eb7c70991f544405b0
Author: Robin Dapp
Date: Wed Jul 31 16:54:03 2024 +0200
RISC-V: Correct mode_idx attribute for viwalu wx variants [PR116149].
In PR116149 we choose a wrong vector length which causes wrong values in
a reduction. The problem happens in avlprop where we choose the
number of units in the instruction's mode as vector length. For the
non-scalar variants the respective operand has the correct non-widened
mode. For the scalar variants, however, the same operand has a scalar
mode which obviously only has one unit. This makes us choose VL = 1
leaving three elements undisturbed (so potentially -1). Those end up
in the reduction causing the wrong result.
This patch adjusts the mode_idx just for the scalar variants of the
affected instruction patterns.
gcc/ChangeLog:
PR target/116149
* config/riscv/vector.md: Fix mode_idx attribute of scalar
widen add/sub variants.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr116149.c: New test.
(cherry picked from commit f15cd1802129454029f7fcc8ee3ddd56a86cdad8)
Diff:
---
gcc/config/riscv/vector.md| 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/pr116149.c | 18 ++
2 files changed, 20 insertions(+)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index bcedf3d79e2..d4d9bd87e91 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -4016,6 +4016,7 @@
"TARGET_VECTOR"
"vwadd.wx\t%0,%3,%z4%p1"
[(set_attr "type" "viwalu")
+ (set_attr "mode_idx" "3")
(set_attr "mode" "")])
(define_insn "@pred_single_widen_sub_extended_scalar"
@@ -4038,6 +4039,7 @@
"TARGET_VECTOR"
"vwsub.wx\t%0,%3,%z4%p1"
[(set_attr "type" "viwalu")
+ (set_attr "mode_idx" "3")
(set_attr "mode" "")])
(define_insn "@pred_widen_mulsu"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr116149.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr116149.c
new file mode 100644
index 000..4f5927b96fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr116149.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=rv64gcv_zvl256b -mabi=lp64d -mrvv-vector-bits=zvl"
} */
+
+long a;
+short b[6];
+short c[20];
+int main() {
+ for (short d = 0; d < 20; d += 3) {
+c[d] = 0;
+for (int e = 0; e < 20; e += 2)
+ for (int f = 1; f < 20; f += 2)
+a += (unsigned)b[f + e];
+ }
+ if (a != 0)
+__builtin_abort ();
+}
+
+/* { dg-final { scan-assembler-times "vsetivli\tzero,1" 0 } } */
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Improve length attributes for atomic insn sequences
https://gcc.gnu.org/g:11967b054b91d58e8555886664ae91603032c14d commit 11967b054b91d58e8555886664ae91603032c14d Author: Patrick O'Neill Date: Thu Aug 1 20:27:52 2024 -0700 RISC-V: Improve length attributes for atomic insn sequences gcc/ChangeLog: * config/riscv/sync-rvwmo.md: Add conditional length attributes. * config/riscv/sync-ztso.md: Ditto. * config/riscv/sync.md: Fix incorrect insn length attributes and reformat existing conditional checks. Signed-off-by: Patrick O'Neill (cherry picked from commit 7ecd6610528a301e349df273b624513ef3827321) Diff: --- gcc/config/riscv/sync-rvwmo.md | 10 -- gcc/config/riscv/sync-ztso.md | 9 +++-- gcc/config/riscv/sync.md | 10 ++ 3 files changed, 21 insertions(+), 8 deletions(-) diff --git a/gcc/config/riscv/sync-rvwmo.md b/gcc/config/riscv/sync-rvwmo.md index 5db94c8c27f..e26f53ccd3e 100644 --- a/gcc/config/riscv/sync-rvwmo.md +++ b/gcc/config/riscv/sync-rvwmo.md @@ -68,7 +68,10 @@ return "\t%0,%1"; } [(set_attr "type" "multi") - (set (attr "length") (const_int 12))]) + (set (attr "length") + (symbol_ref "(is_mm_seq_cst (memmodel_from_int (INTVAL (operands[2]))) ? 12 + : is_mm_acquire (memmodel_from_int (INTVAL (operands[2]))) ? 8 + : 4)"))]) ;; Implement atomic stores with conservative fences. ;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7. @@ -94,4 +97,7 @@ return "\t%z1,%0"; } [(set_attr "type" "multi") - (set (attr "length") (const_int 12))]) + (set (attr "length") + (symbol_ref "(is_mm_seq_cst (memmodel_from_int (INTVAL (operands[2]))) ? 12 + : is_mm_release (memmodel_from_int (INTVAL (operands[2]))) ? 8 + : 4)"))]) diff --git a/gcc/config/riscv/sync-ztso.md b/gcc/config/riscv/sync-ztso.md index f99a21b45ca..7121b97083f 100644 --- a/gcc/config/riscv/sync-ztso.md +++ b/gcc/config/riscv/sync-ztso.md @@ -58,7 +58,10 @@ return "\t%0,%1"; } [(set_attr "type" "multi") - (set (attr "length") (const_int 12))]) + (set (attr "length") + (symbol_ref "(is_mm_seq_cst (memmodel_from_int (INTVAL (operands[2]))) ? 8 + : 4)"))]) + (define_insn "atomic_store_ztso" [(set (match_operand:ANYI 0 "memory_operand" "=A") @@ -78,4 +81,6 @@ return "\t%z1,%0"; } [(set_attr "type" "multi") - (set (attr "length") (const_int 8))]) + (set (attr "length") + (symbol_ref "(is_mm_seq_cst (memmodel_from_int (INTVAL (operands[2]))) ? 8 + : 4)"))]) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 0c493fea828..aa0c20446f4 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -199,7 +199,7 @@ "bnez\t%4, 1b"; } [(set_attr "type" "atomic") - (set (attr "length") (const_int 20))]) + (set (attr "length") (const_int 16))]) (define_insn "subword_atomic_fetch_strong_" [(set (match_operand:SI 0 "register_operand" "=&r") ;; old value at mem @@ -416,7 +416,7 @@ "mv\t%0, %4"; } [(set_attr "type" "atomic") - (set (attr "length") (const_int 20))]) + (set (attr "length") (const_int 16))]) (define_expand "atomic_exchange" [(match_operand:SHORT 0 "register_operand") ;; old value at mem @@ -560,7 +560,8 @@ } [(set_attr "type" "atomic") (set (attr "length") -(symbol_ref "is_mm_seq_cst(memmodel_from_int(INTVAL (operands[5]))) ? 8 : 4"))]) + (symbol_ref "(is_mm_seq_cst (memmodel_from_int (INTVAL (operands[5]))) ? 8 + : 4)"))]) (define_expand "atomic_compare_and_swap" [(match_operand:SI 0 "register_operand" "") ;; bool output @@ -646,7 +647,8 @@ } [(set_attr "type" "atomic") (set (attr "length") -(symbol_ref "is_mm_seq_cst(memmodel_from_int(INTVAL (operands[5]))) ? 8 : 4"))]) + (symbol_ref "(is_mm_seq_cst (memmodel_from_int (INTVAL (operands[5]))) ? 8 + : 4)"))]) (define_expand "atomic_compare_and_swap" [(match_operand:SI 0 "register_operand");; bool output
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] testsuite: Add RISC-V to targets not xfailing gcc.dg/attr-alloc_size-11.c:50, 51.
https://gcc.gnu.org/g:b9820a4a0d683a9b57ab72f7f4e60deb0976513e
commit b9820a4a0d683a9b57ab72f7f4e60deb0976513e
Author: Jiawei
Date: Mon Aug 5 20:15:59 2024 +0800
testsuite: Add RISC-V to targets not xfailing
gcc.dg/attr-alloc_size-11.c:50,51.
The test has been observed to pass on most architectures including RISC-V:
https://godbolt.org/z/8nYEvW6n1
Origin issue see:
https://gcc.gnu.org/PR79356#c11
Update RISC-V target to the pass list.
gcc/testsuite/ChangeLog:
* gcc.dg/attr-alloc_size-11.c: Add RISC-V to the list
of targets excluding xfail on lines 50 and 51.
(cherry picked from commit 70ffc57fd2fdb3c8fa67f11d2e8e6b6275dcc7c0)
Diff:
---
gcc/testsuite/gcc.dg/attr-alloc_size-11.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/attr-alloc_size-11.c
b/gcc/testsuite/gcc.dg/attr-alloc_size-11.c
index a2efe128915..6346d5e084b 100644
--- a/gcc/testsuite/gcc.dg/attr-alloc_size-11.c
+++ b/gcc/testsuite/gcc.dg/attr-alloc_size-11.c
@@ -47,8 +47,8 @@ typedef __SIZE_TYPE__size_t;
/* The following tests fail because of missing range information. The xfail
exclusions are PR79356. */
-TEST (signed char, SCHAR_MIN + 2, ALLOC_MAX); /* { dg-warning "argument 1
range \\\[13, \[0-9\]+\\\] exceeds maximum object size 12" "missing range info
for signed char" { xfail { ! { aarch64*-*-* arm*-*-* avr-*-* alpha*-*-*
cris-*-* ia64-*-* mips*-*-* or1k*-*-* pdp11*-*-* powerpc*-*-* sparc*-*-*
s390*-*-* visium-*-* msp430-*-* nvptx*-*-*} } } } */
-TEST (short, SHRT_MIN + 2, ALLOC_MAX); /* { dg-warning "argument 1 range
\\\[13, \[0-9\]+\\\] exceeds maximum object size 12" "missing range info for
short" { xfail { ! { aarch64*-*-* arm*-*-* alpha*-*-* avr-*-* cris-*-* ia64-*-*
mips*-*-* or1k*-*-* pdp11*-*-* powerpc*-*-* sparc*-*-* s390x-*-* visium-*-*
msp430-*-* nvptx*-*-* } } } } */
+TEST (signed char, SCHAR_MIN + 2, ALLOC_MAX); /* { dg-warning "argument 1
range \\\[13, \[0-9\]+\\\] exceeds maximum object size 12" "missing range info
for signed char" { xfail { ! { aarch64*-*-* arm*-*-* avr-*-* alpha*-*-*
cris-*-* ia64-*-* mips*-*-* or1k*-*-* pdp11*-*-* powerpc*-*-* riscv*-*-*
sparc*-*-* s390*-*-* visium-*-* msp430-*-* nvptx*-*-*} } } } */
+TEST (short, SHRT_MIN + 2, ALLOC_MAX); /* { dg-warning "argument 1 range
\\\[13, \[0-9\]+\\\] exceeds maximum object size 12" "missing range info for
short" { xfail { ! { aarch64*-*-* arm*-*-* alpha*-*-* avr-*-* cris-*-* ia64-*-*
mips*-*-* or1k*-*-* pdp11*-*-* powerpc*-*-* riscv*-*-* sparc*-*-* s390x-*-*
visium-*-* msp430-*-* nvptx*-*-* } } } } */
TEST (int, INT_MIN + 2, ALLOC_MAX);/* { dg-warning "argument 1 range
\\\[13, \[0-9\]+\\\] exceeds maximum object size 12" } */
TEST (int, -3, ALLOC_MAX); /* { dg-warning "argument 1 range
\\\[13, \[0-9\]+\\\] exceeds maximum object size 12" } */
TEST (int, -2, ALLOC_MAX); /* { dg-warning "argument 1 range
\\\[13, \[0-9\]+\\\] exceeds maximum object size 12" } */
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Reject 'd' extension with ILP32E ABI
https://gcc.gnu.org/g:5e106d5552f11a16a83f8e48852dc3803b010c11
commit 5e106d5552f11a16a83f8e48852dc3803b010c11
Author: Patrick O'Neill
Date: Tue Jul 30 14:28:23 2024 -0700
RISC-V: Reject 'd' extension with ILP32E ABI
Also add a testcase for -mabi=lp64d where 'd' is required.
gcc/ChangeLog:
PR target/116111
* config/riscv/riscv.cc (riscv_option_override): Add error.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-41.c: New test.
* gcc.target/riscv/pr116111.c: New test.
Signed-off-by: Patrick O'Neill
(cherry picked from commit 642e38983668807882e774524c88478f641f360f)
Diff:
---
gcc/config/riscv/riscv.cc | 5 +
gcc/testsuite/gcc.target/riscv/arch-41.c | 7 +++
gcc/testsuite/gcc.target/riscv/pr116111.c | 7 +++
3 files changed, 19 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index bf0e0b8a0e7..b1a3d0bdd36 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9818,6 +9818,11 @@ riscv_option_override (void)
error ("rv64e requires lp64e ABI");
}
+ /* ILP32E does not support the 'd' extension. */
+ if (riscv_abi == ABI_ILP32E && UNITS_PER_FP_REG > 4)
+error ("ILP32E ABI does not support the %qc extension",
+ UNITS_PER_FP_REG > 8 ? 'Q' : 'D');
+
/* Zfinx require abi ilp32, ilp32e, lp64 or lp64e. */
if (TARGET_ZFINX
&& riscv_abi != ABI_ILP32 && riscv_abi != ABI_LP64
diff --git a/gcc/testsuite/gcc.target/riscv/arch-41.c
b/gcc/testsuite/gcc.target/riscv/arch-41.c
new file mode 100644
index 000..699eeb20a58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-41.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i -mabi=lp64d" } */
+int
+foo ()
+{}
+
+/* { dg-error "requested ABI requires '-march' to subsume the 'D' extension"
"" { target *-*-* } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/pr116111.c
b/gcc/testsuite/gcc.target/riscv/pr116111.c
new file mode 100644
index 000..5c824be2e93
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr116111.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32ed -mabi=ilp32e" } */
+int
+foo ()
+{}
+
+/* { dg-error "ILP32E ABI does not support the 'D' extension" "" { target
*-*-* } 0 } */
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add deprecation warning to LP64E abi
https://gcc.gnu.org/g:6c244049d986b95658006b265b79ac014b325cbc
commit 6c244049d986b95658006b265b79ac014b325cbc
Author: Patrick O'Neill
Date: Tue Jul 30 17:32:09 2024 -0700
RISC-V: Add deprecation warning to LP64E abi
gcc/ChangeLog:
PR target/116152
* config/riscv/riscv.cc (riscv_option_override): Add deprecation
warning.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-9.c: Add check for warning.
Signed-off-by: Patrick O'Neill
(cherry picked from commit 51db1f307ba395ee322de5adadf56c316e82ae00)
Diff:
---
gcc/config/riscv/riscv.cc | 7 +++
gcc/testsuite/gcc.target/riscv/predef-9.c | 2 ++
2 files changed, 9 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index b1a3d0bdd36..f2aad93526c 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9823,6 +9823,13 @@ riscv_option_override (void)
error ("ILP32E ABI does not support the %qc extension",
UNITS_PER_FP_REG > 8 ? 'Q' : 'D');
+ if (riscv_abi == ABI_LP64E)
+{
+ if (warning (OPT_Wdeprecated, "LP64E ABI is marked for deprecation in
GCC"))
+ inform (UNKNOWN_LOCATION, "If you need LP64E please notify the GCC "
+ "project via https://gcc.gnu.org/PR116152";);
+}
+
/* Zfinx require abi ilp32, ilp32e, lp64 or lp64e. */
if (TARGET_ZFINX
&& riscv_abi != ABI_ILP32 && riscv_abi != ABI_LP64
diff --git a/gcc/testsuite/gcc.target/riscv/predef-9.c
b/gcc/testsuite/gcc.target/riscv/predef-9.c
index cc3abc9a741..0d9488529ea 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-9.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-9.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64em -mabi=lp64e -mno-div -mcmodel=medlow" } */
+/* { dg-warning "LP64E ABI is marked for deprecation in GCC" "" { target *-*-*
} 0 } */
+/* { dg-note "If you need LP64E please notify the GCC project via
https://gcc.gnu.org/PR116152"; "" { target *-*-* } 0 } */
int main () {
#if !defined(__riscv)
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix format-diag warning from improperly formatted url
https://gcc.gnu.org/g:a20c435f8158401e56339bbdfe4c2b5d60ebed96
commit a20c435f8158401e56339bbdfe4c2b5d60ebed96
Author: Patrick O'Neill
Date: Tue Aug 6 08:16:26 2024 -0700
RISC-V: Fix format-diag warning from improperly formatted url
gcc/ChangeLog:
PR target/116152
* config/riscv/riscv.cc (riscv_option_override): Fix url
formatting.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-9.c: Update testcase.
Co-authored-by: Jakub Jelinek
Signed-off-by: Patrick O'Neill
(cherry picked from commit 4c3f476e55149f542de538e97dd9800ec9bd1011)
Diff:
---
gcc/config/riscv/riscv.cc | 4 ++--
gcc/testsuite/gcc.target/riscv/predef-9.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index f2aad93526c..7b1a76b3741 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9826,8 +9826,8 @@ riscv_option_override (void)
if (riscv_abi == ABI_LP64E)
{
if (warning (OPT_Wdeprecated, "LP64E ABI is marked for deprecation in
GCC"))
- inform (UNKNOWN_LOCATION, "If you need LP64E please notify the GCC "
- "project via https://gcc.gnu.org/PR116152";);
+ inform (UNKNOWN_LOCATION, "if you need LP64E please notify the GCC "
+ "project via %{PR116152%}", "https://gcc.gnu.org/PR116152";);
}
/* Zfinx require abi ilp32, ilp32e, lp64 or lp64e. */
diff --git a/gcc/testsuite/gcc.target/riscv/predef-9.c
b/gcc/testsuite/gcc.target/riscv/predef-9.c
index 0d9488529ea..b173d5df57f 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-9.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-9.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64em -mabi=lp64e -mno-div -mcmodel=medlow" } */
/* { dg-warning "LP64E ABI is marked for deprecation in GCC" "" { target *-*-*
} 0 } */
-/* { dg-note "If you need LP64E please notify the GCC project via
https://gcc.gnu.org/PR116152"; "" { target *-*-* } 0 } */
+/* { dg-note "if you need LP64E please notify the GCC project via PR116152" ""
{ target *-*-* } 0 } */
int main () {
#if !defined(__riscv)
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix comment typos
https://gcc.gnu.org/g:69ce456669e1f1549705197cca46e4fd47f509fa commit 69ce456669e1f1549705197cca46e4fd47f509fa Author: Patrick O'Neill Date: Mon Aug 5 14:13:12 2024 -0700 RISC-V: Fix comment typos This fixes most of the typos I found when reading various parts of the RISC-V backend. gcc/ChangeLog: * config/riscv/arch-canonicalize: Fix typos in comments. * config/riscv/autovec.md: Ditto. * config/riscv/riscv-avlprop.cc (avl_can_be_propagated_p): Ditto. (pass_avlprop::get_vlmax_ta_preferred_avl): Ditto. * config/riscv/riscv-modes.def (ADJUST_FLOAT_FORMAT): Ditto. (VLS_MODES): Ditto. * config/riscv/riscv-opts.h (TARGET_ZICOND_LIKE): Ditto. (enum rvv_vector_bits_enum): Ditto. * config/riscv/riscv-protos.h (enum insn_flags): Ditto. (enum insn_type): Ditto. * config/riscv/riscv-sr.cc (riscv_sr_match_epilogue): Ditto. * config/riscv/riscv-string.cc (expand_block_move): Ditto. * config/riscv/riscv-v.cc (rvv_builder::is_repeating_sequence): Ditto. (rvv_builder::single_step_npatterns_p): Ditto. (calculate_ratio): Ditto. (expand_const_vector): Ditto. (shuffle_merge_patterns): Ditto. (shuffle_compress_patterns): Ditto. (expand_select_vl): Ditto. * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS): Ditto. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. * config/riscv/riscv-vector-builtins.cc (function_builder::add_function): Ditto. (resolve_overloaded_builtin): Ditto. * config/riscv/riscv-vector-builtins.def (vbool1_t): Ditto. (vuint8m8_t): Ditto. (vuint16m8_t): Ditto. (vfloat16m8_t): Ditto. (unsigned_vector): Ditto. * config/riscv/riscv-vector-builtins.h (enum required_ext): Ditto. * config/riscv/riscv-vector-costs.cc (get_store_value): Ditto. (costs::analyze_loop_vinfo): Ditto. (costs::add_stmt_cost): Ditto. * config/riscv/riscv.cc (riscv_build_integer): Ditto. (riscv_vector_type_p): Ditto. * config/riscv/thead.cc (th_mempair_output_move): Ditto. * config/riscv/thead.md: Ditto. * config/riscv/vector-iterators.md: Ditto. * config/riscv/vector.md: Ditto. * config/riscv/zc.md: Ditto. Signed-off-by: Patrick O'Neill (cherry picked from commit 8089cb8540e780c10bb1279dfae39a4a7c25c83a) Diff: --- gcc/config/riscv/arch-canonicalize | 2 +- gcc/config/riscv/autovec.md| 2 +- gcc/config/riscv/riscv-avlprop.cc | 8 +++--- gcc/config/riscv/riscv-modes.def | 4 +-- gcc/config/riscv/riscv-opts.h | 6 ++--- gcc/config/riscv/riscv-protos.h| 4 +-- gcc/config/riscv/riscv-sr.cc | 4 +-- gcc/config/riscv/riscv-string.cc | 6 ++--- gcc/config/riscv/riscv-v.cc| 24 - .../riscv/riscv-vector-builtins-functions.def | 2 +- gcc/config/riscv/riscv-vector-builtins-shapes.h| 2 +- gcc/config/riscv/riscv-vector-builtins.cc | 8 +++--- gcc/config/riscv/riscv-vector-builtins.def | 10 gcc/config/riscv/riscv-vector-builtins.h | 6 ++--- gcc/config/riscv/riscv-vector-costs.cc | 8 +++--- gcc/config/riscv/riscv.cc | 6 ++--- gcc/config/riscv/thead.cc | 2 +- gcc/config/riscv/thead.md | 2 +- gcc/config/riscv/vector-iterators.md | 2 +- gcc/config/riscv/vector.md | 30 +++--- gcc/config/riscv/zc.md | 2 +- 21 files changed, 70 insertions(+), 70 deletions(-) diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize index 35e0f46b6bd..95cfe17f912 100755 --- a/gcc/config/riscv/arch-canonicalize +++ b/gcc/config/riscv/arch-canonicalize @@ -140,7 +140,7 @@ def arch_canonicalize(arch, isa_spec): any_change = True # Single letter extension might appear in the long_exts list, - # becasue we just append extensions list to the arch string. + # because we just append extensions list to the arch string. std_exts += list(filter(lambda x:len(x) == 1, long_exts)) def longext_sort (exts): diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index d5793acc999..0423d7bee13 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -794,7 +794,7 @@ }) ;; - -;; Truncation to a mode whose inner mode size is an eigth of mode's. +;; Truncation to a
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix typos in code
https://gcc.gnu.org/g:f8512afeda441a4469002db034bbe6dfaf25a5ce
commit f8512afeda441a4469002db034bbe6dfaf25a5ce
Author: Patrick O'Neill
Date: Mon Aug 5 14:19:58 2024 -0700
RISC-V: Fix typos in code
This fixes typos in function names and executed code.
gcc/ChangeLog:
* config/riscv/riscv-target-attr.cc (num_occurences_in_str):
Rename...
(num_occurrences_in_str): here.
(riscv_process_target_attr): Update num_occurences_in_str callsite.
* config/riscv/riscv-v.cc (emit_vec_widden_cvt_x_f): widden ->
widen.
(emit_vec_widen_cvt_x_f): Ditto.
(emit_vec_widden_cvt_f_f): Ditto.
(emit_vec_widen_cvt_f_f): Ditto.
(emit_vec_rounding_to_integer): Update *widden* callsites.
* config/riscv/riscv-vector-builtins.cc (expand_builtin): Update
required_ext_to_isa_name callsite and fix xtheadvector typo.
* config/riscv/riscv-vector-builtins.h (reqired_ext_to_isa_name):
Rename...
(required_ext_to_isa_name): here.
* config/riscv/riscv_th_vector.h: Fix endif label.
* config/riscv/vector-crypto.md: boardcast_scalar ->
broadcast_scalar.
* config/riscv/vector.md: Ditto.
Signed-off-by: Patrick O'Neill
(cherry picked from commit 6b8e46d93a76055087071204fe5ae1dfbf5ef613)
Diff:
---
gcc/config/riscv/riscv-target-attr.cc | 4 +-
gcc/config/riscv/riscv-v.cc | 10 ++---
gcc/config/riscv/riscv-vector-builtins.cc | 2 +-
gcc/config/riscv/riscv-vector-builtins.h | 4 +-
gcc/config/riscv/riscv_th_vector.h| 2 +-
gcc/config/riscv/vector-crypto.md | 8 ++--
gcc/config/riscv/vector.md| 74 +++
7 files changed, 52 insertions(+), 52 deletions(-)
diff --git a/gcc/config/riscv/riscv-target-attr.cc
b/gcc/config/riscv/riscv-target-attr.cc
index 1645a669217..bf14ade5ce0 100644
--- a/gcc/config/riscv/riscv-target-attr.cc
+++ b/gcc/config/riscv/riscv-target-attr.cc
@@ -290,7 +290,7 @@ riscv_process_one_target_attr (char *arg_str,
NULL-terminated string STR. */
static unsigned int
-num_occurences_in_str (char c, char *str)
+num_occurrences_in_str (char c, char *str)
{
unsigned int res = 0;
while (*str != '\0')
@@ -347,7 +347,7 @@ riscv_process_target_attr (tree args, location_t loc)
/* Used to catch empty spaces between semi-colons i.e.
attribute ((target ("attr1;;attr2"))). */
- unsigned int num_semicolons = num_occurences_in_str (';', str_to_check);
+ unsigned int num_semicolons = num_occurrences_in_str (';', str_to_check);
/* Handle multiple target attributes separated by ';'. */
char *token = strtok_r (str_to_check, ";", &str_to_check);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 577e8c8315c..1370ac489fe 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -4599,7 +4599,7 @@ emit_vec_narrow_cvt_x_f (rtx op_dest, rtx op_src,
insn_type type,
}
static void
-emit_vec_widden_cvt_x_f (rtx op_dest, rtx op_src, insn_type type,
+emit_vec_widen_cvt_x_f (rtx op_dest, rtx op_src, insn_type type,
machine_mode vec_mode)
{
rtx ops[] = {op_dest, op_src};
@@ -4609,7 +4609,7 @@ emit_vec_widden_cvt_x_f (rtx op_dest, rtx op_src,
insn_type type,
}
static void
-emit_vec_widden_cvt_f_f (rtx op_dest, rtx op_src, insn_type type,
+emit_vec_widen_cvt_f_f (rtx op_dest, rtx op_src, insn_type type,
machine_mode vec_mode)
{
rtx ops[] = {op_dest, op_src};
@@ -4835,7 +4835,7 @@ emit_vec_rounding_to_integer (rtx op_0, rtx op_1,
insn_type type,
else if (maybe_eq (vec_fp_size, vec_int_size * 2)) /* DF => SI. */
emit_vec_narrow_cvt_x_f (op_0, op_1, type, vec_fp_mode);
else if (maybe_eq (vec_fp_size * 2, vec_int_size)) /* SF => DI, HF => SI. */
-emit_vec_widden_cvt_x_f (op_0, op_1, type, vec_int_mode);
+emit_vec_widen_cvt_x_f (op_0, op_1, type, vec_int_mode);
else if (maybe_eq (vec_fp_size * 4, vec_int_size)) /* HF => DI. */
{
gcc_assert (vec_bridge_mode != E_VOIDmode);
@@ -4843,9 +4843,9 @@ emit_vec_rounding_to_integer (rtx op_0, rtx op_1,
insn_type type,
rtx op_sf = gen_reg_rtx (vec_bridge_mode);
/* Step-1: HF => SF, no rounding here. */
- emit_vec_widden_cvt_f_f (op_sf, op_1, UNARY_OP, vec_bridge_mode);
+ emit_vec_widen_cvt_f_f (op_sf, op_1, UNARY_OP, vec_bridge_mode);
/* Step-2: SF => DI. */
- emit_vec_widden_cvt_x_f (op_0, op_sf, type, vec_int_mode);
+ emit_vec_widen_cvt_x_f (op_0, op_sf, type, vec_int_mode);
}
else
gcc_unreachable ();
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index 7d8a289c80b..49a1cb1708f 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -4765,7 +4765,7 @@ expand_builtin (unsigned int code,
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Update .SAT_TRUNC dump check due to middle-end change
https://gcc.gnu.org/g:7982b3fb96a0187466024f4ae22f5eb60106b2ee
commit 7982b3fb96a0187466024f4ae22f5eb60106b2ee
Author: Pan Li
Date: Mon Aug 5 16:01:11 2024 +0800
RISC-V: Update .SAT_TRUNC dump check due to middle-end change
Due to recent middle-end change, update the .SAT_TRUNC expand dump
check from 2 to 4.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c: Adjust
asm check times from 2 to 4.
Signed-off-by: Pan Li
Signed-off-by: Pan Li
(cherry picked from commit 1b5c57e53e7ee4087e10f51fcf74968d950d3d83)
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
index 7f047f3f6a2..ae3e44cd57e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
@@ -16,4 +16,4 @@
*/
DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint16_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Minimal support for Zimop extension.
https://gcc.gnu.org/g:16a39f8b7f4192ddeff4efd2b9131adb6352b071
commit 16a39f8b7f4192ddeff4efd2b9131adb6352b071
Author: Jiawei
Date: Fri Aug 2 23:23:14 2024 +0800
RISC-V: Minimal support for Zimop extension.
This patch support Zimop and Zcmop extension[1].To enable GCC to recognize
and process Zimop and Zcmop extension correctly at compile time.
https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: New extension.
* config/riscv/riscv.opt: New mask.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-42.c: New test.
* gcc.target/riscv/arch-43.c: New test.
(cherry picked from commit c8f3fdd53871a20838be532b58ef610bf1dd75e1)
Diff:
---
gcc/common/config/riscv/riscv-common.cc | 8
gcc/config/riscv/riscv.opt | 7 +++
gcc/testsuite/gcc.target/riscv/arch-42.c | 5 +
gcc/testsuite/gcc.target/riscv/arch-43.c | 5 +
4 files changed, 25 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 1944c7785c4..62c6e1dab1f 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -97,6 +97,8 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zabha", "zaamo"},
{"zacas", "zaamo"},
+ {"zcmop", "zca"},
+
{"b", "zba"},
{"b", "zbb"},
{"b", "zbs"},
@@ -319,6 +321,9 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
{"zicclsm", ISA_SPEC_CLASS_NONE, 1, 0},
{"ziccrse", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zimop", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zcmop", ISA_SPEC_CLASS_NONE, 1, 0},
+
{"zicntr", ISA_SPEC_CLASS_NONE, 2, 0},
{"zihpm", ISA_SPEC_CLASS_NONE, 2, 0},
@@ -1629,6 +1634,9 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
{"zicbop", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOP},
{"zic64b", &gcc_options::x_riscv_zicmo_subext, MASK_ZIC64B},
+ {"zimop",&gcc_options::x_riscv_mop_subext, MASK_ZIMOP},
+ {"zcmop",&gcc_options::x_riscv_mop_subext, MASK_ZCMOP},
+
{"zve32x", &gcc_options::x_target_flags, MASK_VECTOR},
{"zve32f", &gcc_options::x_target_flags, MASK_VECTOR},
{"zve64x", &gcc_options::x_target_flags, MASK_VECTOR},
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 2e340e5324f..a8758abc918 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -406,6 +406,13 @@ Mask(ZICBOP) Var(riscv_zicmo_subext)
Mask(ZIC64B) Var(riscv_zicmo_subext)
+TargetVariable
+int riscv_mop_subext
+
+Mask(ZIMOP) Var(riscv_mop_subext)
+
+Mask(ZCMOP) Var(riscv_mop_subext)
+
TargetVariable
int riscv_zf_subext
diff --git a/gcc/testsuite/gcc.target/riscv/arch-42.c
b/gcc/testsuite/gcc.target/riscv/arch-42.c
new file mode 100644
index 000..83f78d28dbe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-42.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zimop -mabi=lp64" } */
+int foo()
+{
+}
diff --git a/gcc/testsuite/gcc.target/riscv/arch-43.c
b/gcc/testsuite/gcc.target/riscv/arch-43.c
new file mode 100644
index 000..4a300a165fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-43.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zcmop -mabi=lp64" } */
+int foo()
+{
+}
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Fix Wstringop-overflow-47.c warning in RISC-V target.
https://gcc.gnu.org/g:d18d1a744832cb6deda2271c6ea9ce39d7b7f672
commit d18d1a744832cb6deda2271c6ea9ce39d7b7f672
Author: Jiawei
Date: Tue Jul 16 08:06:25 2024 +0800
Fix Wstringop-overflow-47.c warning in RISC-V target.
Update warning test info for RISC-V target, compared on godbolt:
https://godbolt.org/z/Mexd3dfcc
gcc/testsuite/ChangeLog:
* gcc.dg/Wstringop-overflow-47.c: Remove xfail target.
(cherry picked from commit b4d91abddc2359a5457b1c77f038b86567da52b6)
Diff:
---
gcc/testsuite/gcc.dg/Wstringop-overflow-47.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/Wstringop-overflow-47.c
b/gcc/testsuite/gcc.dg/Wstringop-overflow-47.c
index 883921b097f..9fb78e55046 100644
--- a/gcc/testsuite/gcc.dg/Wstringop-overflow-47.c
+++ b/gcc/testsuite/gcc.dg/Wstringop-overflow-47.c
@@ -65,15 +65,15 @@ void warn_i16_64 (int16_t i)
like x86_64 it's a series of BIT_FIELD_REFs. The overflow by
the former is detected but the latter is not yet. */
- extern char warn_a64[64]; // { dg-message "at offset (1|128) into
destination object 'warn_a64' of size (63|64)" "pr97027 note" { xfail { ! {
aarch64-*-* riscv*-*-* } } } }
+ extern char warn_a64[64]; // { dg-message "at offset (1|128) into
destination object 'warn_a64' of size (63|64)" "pr97027 note" { xfail { ! {
aarch64-*-* } } } }
void *p = warn_a64 + 1;
I16_64 *q = (I16_64*)p;
- *q = (I16_64){ i }; // { dg-warning "writing (1 byte|64 bytes) into
a region of size (0|63)" "pr97027" { xfail { ! { aarch64-*-* riscv*-*-* } } } }
+ *q = (I16_64){ i }; // { dg-warning "writing (1 byte|64 bytes) into
a region of size (0|63)" "pr97027" { xfail { ! { aarch64-*-* } } } }
char a64[64];
p = a64 + 1;
q = (I16_64*)p;
- *q = (I16_64){ i }; // { dg-warning "writing (1 byte|64 bytes) into
a region of size (0|63)" "pr97027" { xfail { ! { aarch64-*-* riscv*-*-* } } } }
+ *q = (I16_64){ i }; // { dg-warning "writing (1 byte|64 bytes) into
a region of size (0|63)" "pr97027" { xfail { ! { aarch64-*-* } } } }
sink (p);
}
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Rearrange SLP nodes with duplicate statements [PR98138]
https://gcc.gnu.org/g:184712c1c6bd5d46c37bba76996e1f3f6b343389
commit 184712c1c6bd5d46c37bba76996e1f3f6b343389
Author: Manolis Tsamis
Date: Tue Jun 25 08:00:04 2024 -0700
Rearrange SLP nodes with duplicate statements [PR98138]
This change checks when a two_operators SLP node has multiple occurrences of
the same statement (e.g. {A, B, A, B, ...}) and tries to rearrange the
operands
so that there are no duplicates. Two vec_perm expressions are then
introduced
to recreate the original ordering. These duplicates can appear due to how
two_operators nodes are handled, and they prevent vectorization in some
cases.
This targets the vectorization of the SPEC2017 x264 pixel_satd functions.
In some processors a larger than 10% improvement on x264 has been observed.
PR tree-optimization/98138
gcc/ChangeLog:
* tree-vect-slp.cc: Avoid duplicates in two_operators nodes.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/vect-slp-two-operator.c: New test.
(cherry picked from commit ab18785840d7b8afd9f716bab9d1eab415bc4fe9)
Diff:
---
.../gcc.target/aarch64/vect-slp-two-operator.c | 36 +++
gcc/tree-vect-slp.cc | 114 +
2 files changed, 150 insertions(+)
diff --git a/gcc/testsuite/gcc.target/aarch64/vect-slp-two-operator.c
b/gcc/testsuite/gcc.target/aarch64/vect-slp-two-operator.c
new file mode 100644
index 000..b6b093ffc34
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/vect-slp-two-operator.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect
-fdump-tree-vect-details" } */
+
+typedef unsigned char uint8_t;
+typedef unsigned int uint32_t;
+
+#define HADAMARD4(d0, d1, d2, d3, s0, s1, s2, s3) {\
+int t0 = s0 + s1;\
+int t1 = s0 - s1;\
+int t2 = s2 + s3;\
+int t3 = s2 - s3;\
+d0 = t0 + t2;\
+d1 = t1 + t3;\
+d2 = t0 - t2;\
+d3 = t1 - t3;\
+}
+
+void sink(uint32_t tmp[4][4]);
+
+int x264_pixel_satd_8x4( uint8_t *pix1, int i_pix1, uint8_t *pix2, int i_pix2 )
+{
+uint32_t tmp[4][4];
+int sum = 0;
+for( int i = 0; i < 4; i++, pix1 += i_pix1, pix2 += i_pix2 )
+{
+uint32_t a0 = (pix1[0] - pix2[0]) + ((pix1[4] - pix2[4]) << 16);
+uint32_t a1 = (pix1[1] - pix2[1]) + ((pix1[5] - pix2[5]) << 16);
+uint32_t a2 = (pix1[2] - pix2[2]) + ((pix1[6] - pix2[6]) << 16);
+uint32_t a3 = (pix1[3] - pix2[3]) + ((pix1[7] - pix2[7]) << 16);
+HADAMARD4( tmp[i][0], tmp[i][1], tmp[i][2], tmp[i][3], a0,a1,a2,a3 );
+}
+sink(tmp);
+}
+
+/* { dg-final { scan-tree-dump "vectorizing stmts using SLP" "vect" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc
index 0795605ec52..f23a04560ff 100644
--- a/gcc/tree-vect-slp.cc
+++ b/gcc/tree-vect-slp.cc
@@ -2404,6 +2404,95 @@ out:
}
swap = NULL;
+ bool has_two_operators_perm = false;
+ auto_vec two_op_perm_indices[2];
+ vec two_op_scalar_stmts[2] = {vNULL, vNULL};
+
+ if (two_operators && oprnds_info.length () == 2 && group_size > 2)
+{
+ unsigned idx = 0;
+ hash_map seen;
+ vec new_oprnds_info
+ = vect_create_oprnd_info (1, group_size);
+ bool success = true;
+
+ enum tree_code code = ERROR_MARK;
+ if (oprnds_info[0]->def_stmts[0]
+ && is_a (oprnds_info[0]->def_stmts[0]->stmt))
+ code = gimple_assign_rhs_code (oprnds_info[0]->def_stmts[0]->stmt);
+
+ for (unsigned j = 0; j < group_size; ++j)
+ {
+ FOR_EACH_VEC_ELT (oprnds_info, i, oprnd_info)
+ {
+ stmt_vec_info stmt_info = oprnd_info->def_stmts[j];
+ if (!stmt_info || !stmt_info->stmt
+ || !is_a (stmt_info->stmt)
+ || gimple_assign_rhs_code (stmt_info->stmt) != code
+ || skip_args[i])
+ {
+ success = false;
+ break;
+ }
+
+ bool exists;
+ unsigned &stmt_idx
+ = seen.get_or_insert (stmt_info->stmt, &exists);
+
+ if (!exists)
+ {
+ new_oprnds_info[0]->def_stmts.safe_push (stmt_info);
+ new_oprnds_info[0]->ops.safe_push (oprnd_info->ops[j]);
+ stmt_idx = idx;
+ idx++;
+ }
+
+ two_op_perm_indices[i].safe_push (stmt_idx);
+ }
+
+ if (!success)
+ break;
+ }
+
+ if (success && idx == group_size)
+ {
+ if (dump_enabled_p ())
+ {
+ dump_printf_loc (MSG_NOTE, vect_location,
+ "Replace two_operators operands:\n");
+
+ FOR_EACH_VEC_ELT (oprnds_info, i, oprnd_info)
+ {
+ dump_printf_loc (MSG_NOTE, vect_location,
+
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Delete duplicate '#define RISCV_DWARF_VLENB'
https://gcc.gnu.org/g:05611fbd80acad68fca9ce7f951977699b27d20b commit 05611fbd80acad68fca9ce7f951977699b27d20b Author: Jin Ma Date: Thu Aug 8 07:49:51 2024 -0600 RISC-V: Delete duplicate '#define RISCV_DWARF_VLENB' gcc/ChangeLog: * config/riscv/riscv.h (RISCV_DWARF_VLENB): Delete. (cherry picked from commit ecdf7a4ed82bd95f8058914c9f92ad2c2f924033) Diff: --- gcc/config/riscv/riscv.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 57910eecd3e..f6c5a11b2f9 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -1238,8 +1238,6 @@ extern void riscv_remove_unneeded_save_restore_calls (void); #define REGMODE_NATURAL_SIZE(MODE) riscv_regmode_natural_size (MODE) -#define RISCV_DWARF_VLENB (4096 + 0xc22) - #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER + 1 /* VLENB */) #define DWARF_REG_TO_UNWIND_COLUMN(REGNO) \
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V][PR target/116240] Ensure object is a comparison before extracting arguments
https://gcc.gnu.org/g:616f63ee647e61d3cfb25ecf68c50ecbef364828
commit 616f63ee647e61d3cfb25ecf68c50ecbef364828
Author: Jeff Law
Date: Thu Aug 8 07:42:26 2024 -0600
[RISC-V][PR target/116240] Ensure object is a comparison before extracting
arguments
This was supposed to go out the door yesterday, but I kept getting
interrupted.
The target bits for rtx costing can't assume the rtl they're given actually
matches a target pattern. It's just kind of inherent in how the costing
routines get called in various places.
In this particular case we're trying to cost a conditional move:
(set (dest) (if_then_else (cond) (true) (false))
On the RISC-V port the backend only allows actual conditionals for COND. So
something like (eq (reg) (const_int 0)). In the costing code for
if-then-else
we did something like
(XEXP (XEXP (cond, 0), 0)))
Which fails miserably if COND is a terminal node like (reg) rather than (ne
(reg) (const_int 0)
So this patch tightens up the RTL scanning to ensure that we have a
comparison
before we start looking at the comparison's arguments.
Run through my tester without incident, but I'll wait for the pre-commit
tester
to run through a cycle before pushing to the trunk.
Jeff
ps. We probably could support a naked REG for the condition and
internally convert it to (ne (reg) (const_int 0)), but I don't think it likely
happens with any regularity.
PR target/116240
gcc/
* config/riscv/riscv.cc (riscv_rtx_costs): Ensure object is a
comparison before looking at its arguments.
gcc/testsuite
* gcc.target/riscv/pr116240.c: New test.
(cherry picked from commit 190ad81282057b0e5884fd30a7270356b9b1)
Diff:
---
gcc/config/riscv/riscv.cc | 6 --
gcc/testsuite/gcc.target/riscv/pr116240.c | 12
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 20f4f014a6e..48258e1e713 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3646,9 +3646,11 @@ riscv_rtx_costs (rtx x, machine_mode mode, int
outer_code, int opno ATTRIBUTE_UN
&& XEXP (x, 2) == CONST0_RTX (GET_MODE (XEXP (x, 1
|| (GET_CODE (XEXP (x, 2)) == REG
&& XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 2
- || (GET_CODE (XEXP (x, 1)) == REG
+ || (COMPARISON_P (XEXP (x, 0))
+ && GET_CODE (XEXP (x, 1)) == REG
&& rtx_equal_p (XEXP (x, 1), XEXP (XEXP (x, 0), 0)))
- || (GET_CODE (XEXP (x, 1)) == REG
+ || (COMPARISON_P (XEXP (x, 0))
+ && GET_CODE (XEXP (x, 1)) == REG
&& rtx_equal_p (XEXP (x, 2), XEXP (XEXP (x, 0), 0)
{
*total = COSTS_N_INSNS (1);
diff --git a/gcc/testsuite/gcc.target/riscv/pr116240.c
b/gcc/testsuite/gcc.target/riscv/pr116240.c
new file mode 100644
index 000..7e3eaa2f544
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr116240.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-fwrapv
-march=rv64imvxtheadcondmov_xventanacondops -mabi=lp64d" } */
+
+int a, b;
+void c() {
+ int e = a >= 2 ? b : a;
+ short d = e * 2;
+ if (d)
+for (;;)
+ ;
+}
+
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: testsuite: xtheadfmemidx: Rename test and add similar Zfa test
https://gcc.gnu.org/g:fef123664d31ed2ccb29693a8345a72e209da6c4
commit fef123664d31ed2ccb29693a8345a72e209da6c4
Author: Christoph Müllner
Date: Tue Aug 6 07:24:07 2024 +0200
RISC-V: testsuite: xtheadfmemidx: Rename test and add similar Zfa test
Test file xtheadfmemidx-medany.c has been added in b79cd204c780 as a
test case that provoked an ICE when loading DFmode registers via two
SImode register loads followed by a SI->DF[63:32] move from XTheadFmv.
Since Zfa is affected in the same way as XTheadFmv, even if both
have slightly different instructions, let's add a test for Zfa as well
and give the tests proper names.
Let's also add a test into the test files that counts the SI->DF moves
from XTheadFmv/Zfa.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xtheadfmemidx-medany.c: Move to...
* gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c: ...here.
* gcc.target/riscv/xtheadfmemidx-zfa-medany.c: New test.
Signed-off-by: Christoph Müllner
(cherry picked from commit 8e6bc6dd2bb476fa97586b477bc98c670a3fcaf0)
Diff:
---
...x-medany.c => xtheadfmemidx-xtheadfmv-medany.c} | 5 +--
.../gcc.target/riscv/xtheadfmemidx-zfa-medany.c| 39 ++
2 files changed, 42 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-medany.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
similarity index 71%
rename from gcc/testsuite/gcc.target/riscv/xtheadfmemidx-medany.c
rename to gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
index 0c8060d0632..7c70b775824 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-Og" "-Os" "-Oz"} } */
-/* { dg-options "-march=rv32gc_xtheadfmemidx_xtheadfmv_xtheadmemidx
-mabi=ilp32d -mcmodel=medany -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" "-O0" "-O1" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc_xtheadfmemidx_xtheadfmv_xtheadmemidx
-mabi=ilp32d -mcmodel=medany" } */
typedef union {
double v;
@@ -36,3 +36,4 @@ double foo (int i, int j)
}
/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mth\.fmv\.hw\.x\M} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
new file mode 100644
index 000..4215eab1195
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-flto" "-O0" "-O1" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc_zfa_xtheadfmemidx_xtheadmemidx -mabi=ilp32d
-mcmodel=medany" } */
+
+typedef union {
+ double v;
+ unsigned w;
+} my_t;
+
+double z;
+
+double foo (int i, int j)
+{
+
+ if (j)
+{
+ switch (i)
+ {
+ case 0:
+ return 1;
+ case 1:
+ return 0;
+ case 2:
+ return 3.0;
+ }
+}
+
+ if (i == 1)
+{
+ my_t u;
+ u.v = z;
+ u.w = 1;
+ z = u.v;
+}
+ return z;
+}
+
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mfmvp\.d\.x\M} 3 } } */
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: xthead(f)memidx: Eliminate optimization patterns
https://gcc.gnu.org/g:c2fbe69dbc0c7ef43ad3d99122f0998be89fcb33
commit c2fbe69dbc0c7ef43ad3d99122f0998be89fcb33
Author: Christoph Müllner
Date: Tue Jul 30 13:10:59 2024 +0200
RISC-V: xthead(f)memidx: Eliminate optimization patterns
We have a huge amount of optimization patterns (insn_and_split) for
XTheadMemIdx and XTheadFMemIdx that attempt to do something, that can be
done more efficient by generic GCC passes, if we have proper support code.
A key function in eliminating the optimization patterns is
th_memidx_classify_address_index(), which needs to identify each possible
memory expression that can be lowered into a XTheadMemIdx/XTheadFMemIdx
instruction. This patch adds all memory expressions that were
previously only recognized by the optimization patterns.
Now, that the address classification is complete, we can finally remove
all optimization patterns with the side-effect or getting rid of the
non-canonical memory expression they produced: (plus (reg) (ashift (reg)
(imm))).
A positive side-effect of this change is, that we address an RV32 ICE,
that was caused by the th_memidx_I_c pattern, which did not properly
handle SUBREGs (more details are in PR116131).
A temporary negative side-effect of this change is, that we cause a
regression of the xtheadfmemidx + xtheadfmv/zfa tests (initially
introduced as part of b79cd204c780 to address an ICE).
As this issue cannot be addressed in the code parts that are
adjusted in this patch, we just accept the regression for now.
PR target/116131
gcc/ChangeLog:
* config/riscv/thead.cc (th_memidx_classify_address_index):
Recognize all possible XTheadMemIdx memory operand structures.
(th_fmemidx_output_index): Do strict classification.
* config/riscv/thead.md (*th_memidx_operand): Remove.
(TARGET_XTHEADMEMIDX): Likewise.
(TARGET_HARD_FLOAT && TARGET_XTHEADFMEMIDX): Likewise.
(!TARGET_64BIT && TARGET_XTHEADMEMIDX): Likewise.
(*th_memidx_I_a): Likewise.
(*th_memidx_I_b): Likewise.
(*th_memidx_I_c): Likewise.
(*th_memidx_US_a): Likewise.
(*th_memidx_US_b): Likewise.
(*th_memidx_US_c): Likewise.
(*th_memidx_UZ_a): Likewise.
(*th_memidx_UZ_b): Likewise.
(*th_memidx_UZ_c): Likewise.
(*th_fmemidx_movsf_hardfloat): Likewise.
(*th_fmemidx_movdf_hardfloat_rv64): Likewise.
(*th_fmemidx_I_a): Likewise.
(*th_fmemidx_I_c): Likewise.
(*th_fmemidx_US_a): Likewise.
(*th_fmemidx_US_c): Likewise.
(*th_fmemidx_UZ_a): Likewise.
(*th_fmemidx_UZ_c): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr116131.c: New test.
Reported-by: Patrick O'Neill
Signed-off-by: Christoph Müllner
(cherry picked from commit 31c3c5d1cad7f08c2eb7d264f4a208c2c91d20d1)
Diff:
---
gcc/config/riscv/thead.cc | 88 ++-
gcc/config/riscv/thead.md | 417 --
gcc/testsuite/gcc.target/riscv/pr116131.c | 15 ++
3 files changed, 90 insertions(+), 430 deletions(-)
diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc
index 13ca8f674b0..2f1d83fbbc7 100644
--- a/gcc/config/riscv/thead.cc
+++ b/gcc/config/riscv/thead.cc
@@ -609,31 +609,70 @@ th_memidx_classify_address_index (struct
riscv_address_info *info, rtx x,
if (GET_CODE (x) != PLUS)
return false;
- rtx reg = XEXP (x, 0);
+ rtx op0 = XEXP (x, 0);
+ rtx op1 = XEXP (x, 1);
enum riscv_address_type type;
- rtx offset = XEXP (x, 1);
int shift;
+ rtx reg = op0;
+ rtx offset = op1;
if (!riscv_valid_base_register_p (reg, mode, strict_p))
-return false;
+{
+ reg = op1;
+ offset = op0;
+ if (!riscv_valid_base_register_p (reg, mode, strict_p))
+ return false;
+}
/* (reg:X) */
- if (REG_P (offset)
+ if ((REG_P (offset) || SUBREG_P (offset))
&& GET_MODE (offset) == Xmode)
{
type = ADDRESS_REG_REG;
shift = 0;
offset = offset;
}
- /* (zero_extend:DI (reg:SI)) */
- else if (GET_CODE (offset) == ZERO_EXTEND
+ /* (any_extend:DI (reg:SI)) */
+ else if (TARGET_64BIT
+ && (GET_CODE (offset) == SIGN_EXTEND
+ || GET_CODE (offset) == ZERO_EXTEND)
&& GET_MODE (offset) == DImode
&& GET_MODE (XEXP (offset, 0)) == SImode)
{
- type = ADDRESS_REG_UREG;
+ type = (GET_CODE (offset) == SIGN_EXTEND)
+? ADDRESS_REG_REG : ADDRESS_REG_UREG;
shift = 0;
offset = XEXP (offset, 0);
}
+ /* (mult:X (reg:X) (const_int scale)) */
+ else if (GET_CODE (offset) == MULT
+ && GET_MODE (offset) == Xmode
+ && REG_P (XEXP (offset, 0))
+ && GET_MODE (
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: rv32/DF: Prevent 2 SImode loads using XTheadMemIdx
https://gcc.gnu.org/g:a9e84ce68bf3779e5bbc643cfab457803f7b5ad7 commit a9e84ce68bf3779e5bbc643cfab457803f7b5ad7 Author: Christoph Müllner Date: Tue Aug 6 06:48:59 2024 +0200 RISC-V: rv32/DF: Prevent 2 SImode loads using XTheadMemIdx When enabling XTheadFmv/Zfa and XThead(F)MemIdx, we might end up with the following insn (registers are examples, but of correct class): (set (reg:DF a4) (mem:DF (plus:SI (mult:SI (reg:SI a0) (const_int 8)) (reg:SI a5 This is a result of an attempt to load the DF register via two SI register loads followed by XTheadFmv/Zfa instructions to move the contents of the two SI registers into the DF register. The two loads are generated in riscv_split_doubleword_move(), where the second load adds an offset of 4 to load address. While this works fine for RVI loads, this can't be handled for XTheadMemIdx addresses. Coming back to the example above, we would end up with the following insn, which can't be simplified or matched: (set (reg:SI a4) (mem:SI (plus:SI (plus:SI (mult:SI (reg:SI a0) (const_int 8)) (reg:SI a5)) (const_int 4 This triggered an ICE in the past, which was resolved in b79cd204c780, which also added the test xtheadfmemidx-medany.c, where the examples are from. The patch postponed the optimization insn_and_split pattern for XThead(F)MemIdx, so that the situation could effectively be avoided. Since we don't want to rely on these optimization pattern in the future, we need a different solution. Therefore, this patch restricts the movdf_hardfloat_rv32 insn to not match for split-double-word-moves with XThead(F)MemIdx operands. This ensures we don't need to split them up later. When looking at the code generation of the test file, we can see that we have less GP<->FP conversions, but cannot use the indexed loads. The new sequence is identical to rv32gc_xtheadfmv (similar to rv32gc_zfa). Old: [...] lla a5,.LANCHOR0 th.flrd fa5,a5,a0,3 fmv.x.w a4,fa5 th.fmv.x.hw a5,fa5 .L1: fmv.w.x fa0,a4 th.fmv.hw.x fa0,a5 ret [...] New: [...] lla a5,.LANCHOR0 sllia4,a0,3 add a4,a4,a5 lw a5,4(a4) lw a4,0(a4) .L1: fmv.w.x fa0,a4 th.fmv.hw.x fa0,a5 ret [...] This was tested (together with the patch that eliminates the XTheadMemIdx optimization patterns) with SPEC CPU 2017 intrate on QEMU (RV64/lp64d). gcc/ChangeLog: * config/riscv/constraints.md (th_m_noi): New constraint. * config/riscv/riscv.md: Adjust movdf_hardfloat_rv32 for XTheadMemIdx. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c: Adjust. * gcc.target/riscv/xtheadfmemidx-zfa-medany.c: Likewise. Signed-off-by: Christoph Müllner (cherry picked from commit 33aca37ebc0c06e9c9240a8a0c13e31a0bcd4efb) Diff: --- gcc/config/riscv/constraints.md | 9 + gcc/config/riscv/riscv.md | 4 ++-- gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c | 3 ++- gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c | 3 ++- 4 files changed, 15 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index a9ee346af6f..3ab6d542622 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -243,6 +243,15 @@ (and (match_code "mem") (match_test "th_memidx_legitimate_index_p (op, true)"))) +(define_memory_constraint "th_m_noi" + "@internal + A MEM with does not match XTheadMemIdx operands." + (and (match_code "mem") + (and (match_test "!th_memidx_legitimate_modify_p (op, true)") + (and (match_test "!th_memidx_legitimate_modify_p (op, false)") +(and (match_test "!th_memidx_legitimate_index_p (op, false)") + (match_test "!th_memidx_legitimate_index_p (op, true)")) + ;; CORE-V Constraints (define_constraint "CV_alu_pow2" "@internal diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index d9f6c1765d0..f46851dd471 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2592,8 +2592,8 @@ ;; In RV32, we lack fmv.x.d and fmv.d.x. Go through memory instead. ;; (However, we can still use fcvt.d.w to zero a floating-point register.) (define_insn "*movdf_hardfloat_rv32" - [(set (match_operand:DF 0 "nonimmediate_operand" "=f, f,f,f,m,m,*zmvf,*
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Small stack tie changes
https://gcc.gnu.org/g:49000f578de1ac20872083e19f709cf41b4a81a7
commit 49000f578de1ac20872083e19f709cf41b4a81a7
Author: Raphael Moreira Zinsly
Date: Mon Jul 22 11:23:12 2024 -0300
RISC-V: Small stack tie changes
Enable the register used by riscv_emit_stack_tie () to be passed as
an argument so we can tie the stack with other registers besides
hard_frame_pointer_rtx.
Also don't allow operand 1 of stack_tie to be optimized to sp
in preparation for the stack clash protection support.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_emit_stack_tie): Pass the
register to be tied to the stack pointer as argument.
* config/riscv/riscv.md (stack_tie): Don't match equal
operands.
(cherry picked from commit 0e604d0ef6dcac8ee4cdc62902f2a2708ef7b040)
Diff:
---
gcc/config/riscv/riscv.cc | 18 +-
gcc/config/riscv/riscv.md | 2 +-
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 48258e1e713..eba04d27f9c 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7894,12 +7894,12 @@ riscv_adjust_multi_push_cfi_prologue (int saved_size)
}
static void
-riscv_emit_stack_tie (void)
+riscv_emit_stack_tie (rtx reg)
{
if (Pmode == SImode)
-emit_insn (gen_stack_tiesi (stack_pointer_rtx, hard_frame_pointer_rtx));
+emit_insn (gen_stack_tiesi (stack_pointer_rtx, reg));
else
-emit_insn (gen_stack_tiedi (stack_pointer_rtx, hard_frame_pointer_rtx));
+emit_insn (gen_stack_tiedi (stack_pointer_rtx, reg));
}
/*zcmp multi push and pop code_for_push_pop function ptr array */
@@ -8080,7 +8080,7 @@ riscv_expand_prologue (void)
GEN_INT ((frame->hard_frame_pointer_offset -
remaining_size).to_constant ()));
RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
- riscv_emit_stack_tie ();
+ riscv_emit_stack_tie (hard_frame_pointer_rtx);
}
/* Save the V registers. */
@@ -8111,7 +8111,7 @@ riscv_expand_prologue (void)
allocation is ordered WRT fp setup and subsequent writes
into the frame. */
if (frame_pointer_needed)
- riscv_emit_stack_tie ();
+ riscv_emit_stack_tie (hard_frame_pointer_rtx);
return;
}
@@ -8150,7 +8150,7 @@ riscv_expand_prologue (void)
allocation is ordered WRT fp setup and subsequent writes
into the frame. */
if (frame_pointer_needed)
- riscv_emit_stack_tie ();
+ riscv_emit_stack_tie (hard_frame_pointer_rtx);
}
}
@@ -8285,7 +8285,7 @@ riscv_expand_epilogue (int style)
if (cfun->calls_alloca)
{
/* Emit a barrier to prevent loads from a deallocated stack. */
- riscv_emit_stack_tie ();
+ riscv_emit_stack_tie (hard_frame_pointer_rtx);
need_barrier_p = false;
poly_int64 adjust_offset = -frame->hard_frame_pointer_offset;
@@ -8379,7 +8379,7 @@ riscv_expand_epilogue (int style)
if (known_gt (step1, 0))
{
/* Emit a barrier to prevent loads from a deallocated stack. */
- riscv_emit_stack_tie ();
+ riscv_emit_stack_tie (hard_frame_pointer_rtx);
need_barrier_p = false;
/* Restore the scalable frame which is assigned in prologue. */
@@ -8479,7 +8479,7 @@ riscv_expand_epilogue (int style)
frame->mask = mask; /* Undo the above fib. */
if (need_barrier_p)
-riscv_emit_stack_tie ();
+riscv_emit_stack_tie (hard_frame_pointer_rtx);
/* Deallocate the final bit of the frame. */
if (step2.to_constant () > 0)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index f46851dd471..5e3ef789e42 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3969,7 +3969,7 @@
(unspec:BLK [(match_operand:X 0 "register_operand" "r")
(match_operand:X 1 "register_operand" "r")]
UNSPEC_TIE))]
- ""
+ "!rtx_equal_p (operands[0], operands[1])"
""
[(set_attr "type" "ghost")
(set_attr "length" "0")]
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Move riscv_v_adjust_scalable_frame
https://gcc.gnu.org/g:fec211cf435acc4f3ebc32c59314c2816291ea96
commit fec211cf435acc4f3ebc32c59314c2816291ea96
Author: Raphael Moreira Zinsly
Date: Mon Jul 22 11:23:17 2024 -0300
RISC-V: Move riscv_v_adjust_scalable_frame
Move riscv_v_adjust_scalable_frame () in preparation for the stack clash
protection support.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_v_adjust_scalable_frame): Move
closer to riscv_expand_prologue.
(cherry picked from commit 5694fcf75b65bea5d3eb42e5d28d7f3e5ee7cfd7)
Diff:
---
gcc/config/riscv/riscv.cc | 62 +++
1 file changed, 31 insertions(+), 31 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index eba04d27f9c..b1582e45aec 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3122,37 +3122,6 @@ riscv_legitimize_poly_move (machine_mode mode, rtx dest,
rtx tmp, rtx src)
}
}
-/* Adjust scalable frame of vector for prologue && epilogue. */
-
-static void
-riscv_v_adjust_scalable_frame (rtx target, poly_int64 offset, bool epilogue)
-{
- rtx tmp = RISCV_PROLOGUE_TEMP (Pmode);
- rtx adjust_size = RISCV_PROLOGUE_TEMP2 (Pmode);
- rtx insn, dwarf, adjust_frame_rtx;
-
- riscv_legitimize_poly_move (Pmode, adjust_size, tmp,
- gen_int_mode (offset, Pmode));
-
- if (epilogue)
-insn = gen_add3_insn (target, target, adjust_size);
- else
-insn = gen_sub3_insn (target, target, adjust_size);
-
- insn = emit_insn (insn);
-
- RTX_FRAME_RELATED_P (insn) = 1;
-
- adjust_frame_rtx
-= gen_rtx_SET (target,
- plus_constant (Pmode, target, epilogue ? offset : -offset));
-
- dwarf = alloc_reg_note (REG_FRAME_RELATED_EXPR, copy_rtx (adjust_frame_rtx),
- NULL_RTX);
-
- REG_NOTES (insn) = dwarf;
-}
-
/* Take care below subreg const_poly_int move:
1. (set (subreg:DI (reg:TI 237) 8)
@@ -7931,6 +7900,37 @@ static const code_for_push_pop_t
code_for_push_pop[ZCMP_MAX_GRP_SLOTS][ZCMP_OP_N
code_for_gpr_multi_popret_up_to_s11,
code_for_gpr_multi_popretz_up_to_s11}};
+/* Adjust scalable frame of vector for prologue && epilogue. */
+
+static void
+riscv_v_adjust_scalable_frame (rtx target, poly_int64 offset, bool epilogue)
+{
+ rtx tmp = RISCV_PROLOGUE_TEMP (Pmode);
+ rtx adjust_size = RISCV_PROLOGUE_TEMP2 (Pmode);
+ rtx insn, dwarf, adjust_frame_rtx;
+
+ riscv_legitimize_poly_move (Pmode, adjust_size, tmp,
+ gen_int_mode (offset, Pmode));
+
+ if (epilogue)
+insn = gen_add3_insn (target, target, adjust_size);
+ else
+insn = gen_sub3_insn (target, target, adjust_size);
+
+ insn = emit_insn (insn);
+
+ RTX_FRAME_RELATED_P (insn) = 1;
+
+ adjust_frame_rtx
+= gen_rtx_SET (target,
+ plus_constant (Pmode, target, epilogue ? offset : -offset));
+
+ dwarf = alloc_reg_note (REG_FRAME_RELATED_EXPR, copy_rtx (adjust_frame_rtx),
+ NULL_RTX);
+
+ REG_NOTES (insn) = dwarf;
+}
+
static rtx
riscv_gen_multi_push_pop_insn (riscv_zcmp_op_t op, HOST_WIDE_INT adj_size,
unsigned int regs_num)
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Stack-clash protection implemention
https://gcc.gnu.org/g:7f6b6a5710258a720d2d35d14c30877b729b4833 commit 7f6b6a5710258a720d2d35d14c30877b729b4833 Author: Raphael Moreira Zinsly Date: Mon Jul 22 11:23:20 2024 -0300 RISC-V: Stack-clash protection implemention This implements stack-clash protection for riscv, with riscv_allocate_and_probe_stack_space being based of aarch64_allocate_and_probe_stack_space from aarch64's implementation. We enforce the probing interval and the guard size to always be equal, their default value is 4Kb which is riscv page size. We also probe up by 1024 bytes in the general case when a probe is required. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_option_override): Enforce that interval is the same size as guard size. (riscv_allocate_and_probe_stack_space): New function. (riscv_expand_prologue): Call riscv_allocate_and_probe_stack_space to the final allocation of the stack and add stack-clash dump information. * config/riscv/riscv.h: Define STACK_CLASH_CALLER_GUARD and STACK_CLASH_MAX_UNROLL_PAGES. gcc/testsuite/ChangeLog: * gcc.dg/params/blocksort-part.c: Skip riscv for stack-clash protection intervals. * gcc.dg/pr82788.c: Skip riscv. * gcc.dg/stack-check-6.c: Skip residual check for riscv. * gcc.dg/stack-check-6a.c: Skip riscv. * gcc.target/riscv/stack-check-12.c: New test. * gcc.target/riscv/stack-check-13.c: New test. * gcc.target/riscv/stack-check-cfa-1.c: New test. * gcc.target/riscv/stack-check-cfa-2.c: New test. * gcc.target/riscv/stack-check-prologue-1.c: New test. * gcc.target/riscv/stack-check-prologue-10.c: New test. * gcc.target/riscv/stack-check-prologue-11.c: New test. * gcc.target/riscv/stack-check-prologue-12.c: New test. * gcc.target/riscv/stack-check-prologue-13.c: New test. * gcc.target/riscv/stack-check-prologue-14.c: New test. * gcc.target/riscv/stack-check-prologue-15.c: New test. * gcc.target/riscv/stack-check-prologue-2.c: New test. * gcc.target/riscv/stack-check-prologue-3.c: New test. * gcc.target/riscv/stack-check-prologue-4.c: New test. * gcc.target/riscv/stack-check-prologue-5.c: New test. * gcc.target/riscv/stack-check-prologue-6.c: New test. * gcc.target/riscv/stack-check-prologue-7.c: New test. * gcc.target/riscv/stack-check-prologue-8.c: New test. * gcc.target/riscv/stack-check-prologue-9.c: New test. * gcc.target/riscv/stack-check-prologue.h: New file. * lib/target-supports.exp (check_effective_target_supports_stack_clash_protection): Add riscv. (check_effective_target_caller_implicit_probes): Likewise. (cherry picked from commit b82d173dac33d9e2f7d31bf84eb0d9f0c21d0240) Diff: --- gcc/config/riscv/riscv.cc | 244 ++--- gcc/config/riscv/riscv.h | 8 + gcc/testsuite/gcc.dg/params/blocksort-part.c | 2 +- gcc/testsuite/gcc.dg/pr82788.c | 2 +- gcc/testsuite/gcc.dg/stack-check-6.c | 2 +- gcc/testsuite/gcc.dg/stack-check-6a.c | 2 +- gcc/testsuite/gcc.target/riscv/stack-check-12.c| 23 ++ gcc/testsuite/gcc.target/riscv/stack-check-13.c| 26 +++ gcc/testsuite/gcc.target/riscv/stack-check-cfa-1.c | 12 + gcc/testsuite/gcc.target/riscv/stack-check-cfa-2.c | 13 ++ .../gcc.target/riscv/stack-check-prologue-1.c | 9 + .../gcc.target/riscv/stack-check-prologue-10.c | 11 + .../gcc.target/riscv/stack-check-prologue-11.c | 11 + .../gcc.target/riscv/stack-check-prologue-12.c | 15 ++ .../gcc.target/riscv/stack-check-prologue-13.c | 20 ++ .../gcc.target/riscv/stack-check-prologue-14.c | 24 ++ .../gcc.target/riscv/stack-check-prologue-15.c | 23 ++ .../gcc.target/riscv/stack-check-prologue-2.c | 10 + .../gcc.target/riscv/stack-check-prologue-3.c | 11 + .../gcc.target/riscv/stack-check-prologue-4.c | 11 + .../gcc.target/riscv/stack-check-prologue-5.c | 11 + .../gcc.target/riscv/stack-check-prologue-6.c | 11 + .../gcc.target/riscv/stack-check-prologue-7.c | 11 + .../gcc.target/riscv/stack-check-prologue-8.c | 10 + .../gcc.target/riscv/stack-check-prologue-9.c | 11 + .../gcc.target/riscv/stack-check-prologue.h| 5 + gcc/testsuite/lib/target-supports.exp | 6 +- 27 files changed, 504 insertions(+), 40 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index b1582e45aec..05dce3ccea4 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7953,6 +7953,191 @@ get_multi_push_fpr_
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add support to vector stack-clash protection
https://gcc.gnu.org/g:9673f136d09980bbc7be4e3e82fec1ef37652ea0
commit 9673f136d09980bbc7be4e3e82fec1ef37652ea0
Author: Raphael Moreira Zinsly
Date: Mon Jul 22 11:23:23 2024 -0300
RISC-V: Add support to vector stack-clash protection
Adds basic support to vector stack-clash protection using a loop to do
the probing and stack adjustments.
gcc/ChangeLog:
* config/riscv/riscv.cc
(riscv_allocate_and_probe_stack_loop): New function.
(riscv_v_adjust_scalable_frame): Add stack-clash protection
support.
(riscv_allocate_and_probe_stack_space): Move the probe loop
implementation to riscv_allocate_and_probe_stack_loop.
* config/riscv/riscv.h: Define RISCV_STACK_CLASH_VECTOR_CFA_REGNUM.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/stack-check-cfa-3.c: New test.
* gcc.target/riscv/stack-check-prologue-16.c: New test.
* gcc.target/riscv/struct_vect_24.c: New test.
(cherry picked from commit 2862d99bfdae96a1d4b275fa3f3daad6206ff761)
Diff:
---
gcc/config/riscv/riscv.cc | 99 +-
gcc/config/riscv/riscv.h | 5 ++
gcc/testsuite/gcc.target/riscv/stack-check-cfa-3.c | 13 +++
.../gcc.target/riscv/stack-check-prologue-16.c | 30 +++
gcc/testsuite/gcc.target/riscv/struct_vect_24.c| 47 ++
5 files changed, 173 insertions(+), 21 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 05dce3ccea4..2210f56ae46 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7900,6 +7900,35 @@ static const code_for_push_pop_t
code_for_push_pop[ZCMP_MAX_GRP_SLOTS][ZCMP_OP_N
code_for_gpr_multi_popret_up_to_s11,
code_for_gpr_multi_popretz_up_to_s11}};
+/* Set a probe loop for stack clash protection. */
+static void
+riscv_allocate_and_probe_stack_loop (rtx tmp, enum rtx_code code,
+rtx op0, rtx op1, bool vector,
+HOST_WIDE_INT offset)
+{
+ tmp = riscv_force_temporary (tmp, gen_int_mode (offset, Pmode));
+
+ /* Loop. */
+ rtx label = gen_label_rtx ();
+ emit_label (label);
+
+ /* Allocate and probe stack. */
+ emit_insn (gen_sub3_insn (stack_pointer_rtx, stack_pointer_rtx, tmp));
+ emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
+ STACK_CLASH_CALLER_GUARD));
+ emit_insn (gen_blockage ());
+
+ /* Adjust the remaining vector length. */
+ if (vector)
+emit_insn (gen_sub3_insn (op0, op0, tmp));
+
+ /* Branch if there's still more bytes to probe. */
+ riscv_expand_conditional_branch (label, code, op0, op1);
+ JUMP_LABEL (get_last_insn ()) = label;
+
+ emit_insn (gen_blockage ());
+}
+
/* Adjust scalable frame of vector for prologue && epilogue. */
static void
@@ -7912,6 +7941,49 @@ riscv_v_adjust_scalable_frame (rtx target, poly_int64
offset, bool epilogue)
riscv_legitimize_poly_move (Pmode, adjust_size, tmp,
gen_int_mode (offset, Pmode));
+ /* If doing stack clash protection then we use a loop to allocate and probe
+ the stack. */
+ if (flag_stack_clash_protection && !epilogue)
+{
+ HOST_WIDE_INT min_probe_threshold
+ = (1 << param_stack_clash_protection_guard_size) -
STACK_CLASH_CALLER_GUARD;
+
+ if (!frame_pointer_needed)
+ {
+ /* This is done to provide unwinding information for the stack
+adjustments we're about to do, however to prevent the optimizers
+from removing the T3 move and leaving the CFA note (which would be
+very wrong) we tie the old and new stack pointer together.
+The tie will expand to nothing but the optimizers will not touch
+the instruction. */
+ insn = get_last_insn ();
+ rtx stack_ptr_copy = gen_rtx_REG (Pmode,
RISCV_STACK_CLASH_VECTOR_CFA_REGNUM);
+ emit_move_insn (stack_ptr_copy, stack_pointer_rtx);
+ riscv_emit_stack_tie (stack_ptr_copy);
+
+ /* We want the CFA independent of the stack pointer for the
+duration of the loop. */
+ add_reg_note (insn, REG_CFA_DEF_CFA, stack_ptr_copy);
+ RTX_FRAME_RELATED_P (insn) = 1;
+ }
+
+ riscv_allocate_and_probe_stack_loop (tmp, GE, adjust_size, tmp, true,
+ min_probe_threshold);
+
+ /* Allocate the residual. */
+ insn = emit_insn (gen_sub3_insn (target, target, adjust_size));
+
+ /* Now reset the CFA register if needed. */
+ if (!frame_pointer_needed)
+ {
+ add_reg_note (insn, REG_CFA_DEF_CFA,
+ plus_constant (Pmode, stack_pointer_rtx, -offset));
+ RTX_FRAME_RELATED_P (insn) = 1;
+ }
+
+ return;
+}
+
if (epilogue)
insn = gen_add3_insn (target, target, adjust_size);
else
@@ -8059,8 +8131,9 @@ ri
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Enable stack clash in alloca
https://gcc.gnu.org/g:8eced564ddf62282cd2737a7b3487088fc32eff4
commit 8eced564ddf62282cd2737a7b3487088fc32eff4
Author: Raphael Moreira Zinsly
Date: Mon Jul 22 11:23:27 2024 -0300
RISC-V: Enable stack clash in alloca
Add the TARGET_STACK_CLASH_PROTECTION_ALLOCA_PROBE_RANGE to riscv in
order to enable stack clash protection when using alloca.
The code and tests are the same used by aarch64.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_compute_frame_info): Update
outgoing args size.
(riscv_stack_clash_protection_alloca_probe_range): New.
(TARGET_STACK_CLASH_PROTECTION_ALLOCA_PROBE_RANGE): New.
* config/riscv/riscv.h
(STACK_CLASH_MIN_BYTES_OUTGOING_ARGS): New.
(STACK_DYNAMIC_OFFSET): New.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/stack-check-14.c: New test.
* gcc.target/riscv/stack-check-15.c: New test.
* gcc.target/riscv/stack-check-alloca-1.c: New test.
* gcc.target/riscv/stack-check-alloca-2.c: New test.
* gcc.target/riscv/stack-check-alloca-3.c: New test.
* gcc.target/riscv/stack-check-alloca-4.c: New test.
* gcc.target/riscv/stack-check-alloca-5.c: New test.
* gcc.target/riscv/stack-check-alloca-6.c: New test.
* gcc.target/riscv/stack-check-alloca-7.c: New test.
* gcc.target/riscv/stack-check-alloca-8.c: New test.
* gcc.target/riscv/stack-check-alloca-9.c: New test.
* gcc.target/riscv/stack-check-alloca-10.c: New test.
* gcc.target/riscv/stack-check-alloca.h: New.
(cherry picked from commit 180ede3543e98ade8f809afe8be5af0eeaeff7bb)
Diff:
---
gcc/config/riscv/riscv.cc | 17 +++
gcc/config/riscv/riscv.h | 17 +++
gcc/testsuite/gcc.target/riscv/stack-check-14.c| 24 ++
gcc/testsuite/gcc.target/riscv/stack-check-15.c| 21 +++
.../gcc.target/riscv/stack-check-alloca-1.c| 15 ++
.../gcc.target/riscv/stack-check-alloca-10.c | 13
.../gcc.target/riscv/stack-check-alloca-2.c| 11 ++
.../gcc.target/riscv/stack-check-alloca-3.c| 11 ++
.../gcc.target/riscv/stack-check-alloca-4.c| 12 +++
.../gcc.target/riscv/stack-check-alloca-5.c| 12 +++
.../gcc.target/riscv/stack-check-alloca-6.c| 12 +++
.../gcc.target/riscv/stack-check-alloca-7.c| 12 +++
.../gcc.target/riscv/stack-check-alloca-8.c| 14 +
.../gcc.target/riscv/stack-check-alloca-9.c| 13
.../gcc.target/riscv/stack-check-alloca.h | 15 ++
15 files changed, 219 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 2210f56ae46..70448772093 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7248,6 +7248,10 @@ riscv_compute_frame_info (void)
frame = &cfun->machine->frame;
+ /* Adjust the outgoing arguments size if required. Keep it in sync with what
+ the mid-end is doing. */
+ crtl->outgoing_args_size = STACK_DYNAMIC_OFFSET (cfun);
+
/* In an interrupt function, there are two cases in which t0 needs to be
used:
1, If we have a large frame, then we need to save/restore t0. We check
for
this before clearing the frame struct.
@@ -11927,6 +11931,15 @@ riscv_expand_ustrunc (rtx dest, rtx src)
emit_move_insn (dest, gen_lowpart (mode, xmode_dest));
}
+/* On riscv we have an ABI defined safe buffer. This constant is used to
+ determining the probe offset for alloca. */
+
+static HOST_WIDE_INT
+riscv_stack_clash_protection_alloca_probe_range (void)
+{
+ return STACK_CLASH_CALLER_GUARD;
+}
+
/* Initialize the GCC target structure. */
#undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
@@ -12235,6 +12248,10 @@ riscv_expand_ustrunc (rtx dest, rtx src)
#define TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT \
riscv_vectorize_preferred_vector_alignment
+#undef TARGET_STACK_CLASH_PROTECTION_ALLOCA_PROBE_RANGE
+#define TARGET_STACK_CLASH_PROTECTION_ALLOCA_PROBE_RANGE \
+ riscv_stack_clash_protection_alloca_probe_range
+
/* Mode switching hooks. */
#undef TARGET_MODE_EMIT
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 2d6c30af8d8..2af2cd78f68 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -1275,4 +1275,21 @@ extern void riscv_remove_unneeded_save_restore_calls
(void);
generating stack clash probes. */
#define STACK_CLASH_MAX_UNROLL_PAGES 4
+/* This value represents the minimum amount of bytes we expect the function's
+ outgoing arguments to be when stack-clash is enabled. */
+#define STACK_CLASH_MIN_BYTES_OUTGOING_ARGS 8
+
+/* Allocate a minimum of STACK_CLASH_MIN_BYTES_OUTGOING_ARGS
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V][PR target/116283] Fix split code for recent Zbs improvements with masked bit positions
https://gcc.gnu.org/g:d0d826c509e0cccadba399eaa57f8d63a51178c5
commit d0d826c509e0cccadba399eaa57f8d63a51178c5
Author: Jeff Law
Date: Fri Aug 9 17:46:01 2024 -0600
[RISC-V][PR target/116283] Fix split code for recent Zbs improvements with
masked bit positions
So Patrick's fuzzer found an interesting little buglet in the Zbs
improvements
I added a couple months back.
Specifically when we have masked bit position for a Zbs instruction. If the
mask has extraneous bits set we'll generate an unrecognizable insn due to an
invalid constant.
More concretely, let's take this pattern:
> (define_insn_and_split ""
> [(set (match_operand:DI 0 "register_operand" "=r")
> (any_extend:DI
> (ashift:SI (const_int 1)
> (subreg:QI(and:DI
(match_operand:DI 1 "register_operand" "r")
> (match_operand 2 "const_int_operand"))
0]
What we need to know to transform this into bset for rv64.
After masking the shift count we want to know the low 5 bits aren't 0x1f.
If
they were 0x1f, then the constant generated would be 0x8000 which would
then need sign extension out to 64bits, which the bset instruction will not
do
for us.
We can ignore anything outside the low 5 bits. The mode of the shift is
SI, so
shifting by 32+ bits is undefined behavior.
It's also worth explicitly mentioning that the hardware is going to mask the
count against 0x3f.
The net is if (operands[2] & 0x1f) != 0x1f, then this transformation is
safe.
So onto the generated split code...
> [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 2)))
>(set (match_dup 0) (zero_extend:DI (ashift:SI
> (const_int 1)
> (subreg:QI (match_dup 0) 0]
Which would seemingly do exactly what we want. The problem is the first
split
insn. If the constant does not fit into a simm12, that insn won't be
recognized resulting in the ICE.
The fix is simple, we just need to mask the constant before generating RTL.
We
can just mask it against 0x1f since we only care about the low 5 bits.
This affects multiple patterns. I've added the appropriate fix to all of
them.
Tested in my tester. Waiting for the pre-commit bits to run before pushing.
PR target/116283
gcc/
* config/riscv/bitmanip.md (Zbs combiner patterns/splitters): Mask
the
bit position in the split code appropriately.
gcc/testsuite/
* gcc.target/riscv/pr116283.c: New test
(cherry picked from commit d4e1290e5d603984e9b410c7d4cf21a9ffbd68fd)
Diff:
---
gcc/config/riscv/bitmanip.md | 24 ++--
gcc/testsuite/gcc.target/riscv/pr116283.c | 15 +++
2 files changed, 33 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index b19295cd942..6872ee56022 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -643,7 +643,10 @@
(set (match_dup 3) (and:DI (not:DI (match_dup 1)) (match_dup 3)))
(set (match_dup 0) (zero_extend:DI
(ashift:SI (const_int 1) (match_dup 4]
- { operands[4] = gen_lowpart (QImode, operands[3]); }
+{
+ operands[4] = gen_lowpart (QImode, operands[3]);
+ operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+}
[(set_attr "type" "bitmanip")])
(define_insn_and_split ""
@@ -662,7 +665,7 @@
(set (match_dup 0) (zero_extend:DI (ashift:SI
(const_int 1)
(subreg:QI (match_dup 0) 0]
- { }
+ { operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); }
[(set_attr "type" "bitmanip")])
;; Similarly two patterns for IOR/XOR generating bset/binv to
@@ -687,7 +690,10 @@
[(set (match_dup 4) (match_dup 2))
(set (match_dup 4) (and:DI (not:DI (match_dup 1)) (match_dup 4)))
(set (match_dup 0) (any_or:DI (ashift:DI (const_int 1) (match_dup 5))
(match_dup 3)))]
- { operands[5] = gen_lowpart (QImode, operands[4]); }
+{
+ operands[5] = gen_lowpart (QImode, operands[4]);
+ operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+}
[(set_attr "type" "bitmanip")])
(define_insn_and_split ""
@@ -708,7 +714,7 @@
"&& reload_completed"
[(set (match_dup 4) (and:DI (match_dup 1) (match_dup 2)))
(set (match_dup 0) (any_or:DI (ashift:DI (const_int 1) (subreg:QI
(match_dup 4) 0)) (match_dup 3)))]
- { }
+ { operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); }
[(set_attr "type" "bitmanip")])
;; Similarly two patterns for AND generating bclr to
@@ -734,7 +740,10 @@
[(set (match_dup 4) (match_dup 2))
(set (match_dup 4) (and:DI (not:DI (match_dup 1)) (match_dup 4)))
(set (match_dup 0) (
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix non-obvious comment typos
https://gcc.gnu.org/g:983da7ad96ff0920ceb3c439a29fdbcf4512fbae
commit 983da7ad96ff0920ceb3c439a29fdbcf4512fbae
Author: Patrick O'Neill
Date: Mon Aug 5 15:29:33 2024 -0700
RISC-V: Fix non-obvious comment typos
This fixes the remainder of the typos I found when reading various parts of
the
RISC-V backend.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (legitimize_move): extrac -> extract.
(expand_vec_cmp_float): Remove duplicate vmnor.mm.
* config/riscv/riscv-vector-builtins.cc: ins -> insns.
* config/riscv/riscv.cc (riscv_init_machine_status): mwrvv -> mrvv.
* config/riscv/vector-iterators.md: RVVM8QImde -> RVVM8QImode
* config/riscv/vector.md: Replaced non-existant vsetivl with
vsetivli.
Signed-off-by: Patrick O'Neill
(cherry picked from commit ccd7068d462b271d5bd9bbfac968204ee96500f1)
Diff:
---
gcc/config/riscv/riscv-v.cc | 6 +++---
gcc/config/riscv/riscv-vector-builtins.cc | 4 ++--
gcc/config/riscv/riscv.cc | 2 +-
gcc/config/riscv/vector-iterators.md | 2 +-
gcc/config/riscv/vector.md| 2 +-
5 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 1370ac489fe..0db5c7591ef 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1552,8 +1552,8 @@ legitimize_move (rtx dest, rtx *srcp)
{
if (GET_MODE_NUNITS (mode).to_constant () <= 31)
{
- /* For NUNITS <= 31 VLS modes, we don't need extrac
-scalar regisers so we apply the naive (set (op0) (op1)) pattern. */
+ /* For NUNITS <= 31 VLS modes, we don't need extract
+scalar registers so we apply the naive (set (op0) (op1)) pattern.
*/
if (can_create_pseudo_p ())
{
/* Need to force register if mem <- !reg. */
@@ -2900,7 +2900,7 @@ expand_vec_cmp_float (rtx target, rtx_code code, rtx op0,
rtx op1,
}
/* We use one_cmpl2 to make Combine PASS to combine mask instructions
- into: vmand.mm/vmnor.mm/vmnand.mm/vmnor.mm/vmxnor.mm. */
+ into: vmand.mm/vmnor.mm/vmnand.mm/vmxnor.mm. */
emit_insn (gen_rtx_SET (target, gen_rtx_NOT (mask_mode, eq0)));
return false;
}
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index 49a1cb1708f..9f707efa533 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -2765,7 +2765,7 @@ static CONSTEXPR const rvv_op_info
all_v_scalar_ptr_index_ops
scalar_ptr_index_args /* Args */};
/* A static operand information for vector_type func (vector_type).
- Some ins just supports SEW=32, such as crypto vectol Zvkg extension.
+ Some insns just supports SEW=32, such as the crypto vector Zvkg extension.
* function registration. */
static CONSTEXPR const rvv_arg_type_info vs_lmul_x2_args[]
= {rvv_arg_type_info (RVV_BASE_vlmul_ext_x2),
@@ -2838,7 +2838,7 @@ static CONSTEXPR const rvv_op_info
u_vvs_crypto_sew32_lmul_x16_ops
vs_lmul_x16_args /* Args */};
/* A static operand information for vector_type func (vector_type).
- Some ins just supports SEW=64, such as crypto vectol Zvbc extension
+ Some insns just supports SEW=64, such as the crypto vector Zvbc extension
vclmul.vv, vclmul.vx.
* function registration. */
static CONSTEXPR const rvv_op_info u_vvv_crypto_sew64_ops
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 70448772093..abe1a56f20e 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9835,7 +9835,7 @@ riscv_init_machine_status (void)
return ggc_cleared_alloc ();
}
-/* Return the VLEN value associated with -march and -mwrvv-vector-bits.
+/* Return the VLEN value associated with -march and -mrvv-vector-bits.
TODO: So far we only support length-agnostic value. */
static poly_uint16
riscv_convert_vector_chunks (struct gcc_options *opts)
diff --git a/gcc/config/riscv/vector-iterators.md
b/gcc/config/riscv/vector-iterators.md
index 5409e9af81a..cbbd248c9bb 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -783,7 +783,7 @@
;;
;; In gather/scatter expand, we need to sign/zero extend the index mode into
vector
;; Pmode, so we need to check whether vector Pmode is available.
-;; E.g. when index mode = RVVM8QImde and Pmode = SImode, if it is not
zero_extend or
+;; E.g. when index mode = RVVM8QImode and Pmode = SImode, if it is not
zero_extend or
;; scalar != 1, such gather/scatter is not allowed since we don't have
RVVM32SImode.
(define_mode_iterator RATIO64 [
(RVVMF8QI "TARGET_MIN_VLEN > 32")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index fb625f611d5..aad34b3aa24 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1520,7 +1520,7 @@
;; 6. Configuration-Setting
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] genoutput: Accelerate the place_operands function.
https://gcc.gnu.org/g:5433bd714737a9b18b54f3579806af2c1f98656d
commit 5433bd714737a9b18b54f3579806af2c1f98656d
Author: Xianmiao Qu
Date: Wed May 22 15:25:16 2024 +0800
genoutput: Accelerate the place_operands function.
With the increase in the number of modes and patterns for some
backend architectures, the place_operands function becomes a
bottleneck int the speed of genoutput, and may even become a
bottleneck int the overall speed of building the GCC project.
This patch aims to accelerate the place_operands function,
the optimizations it includes are:
1. Use a hash table to store operand information,
improving the lookup time for the first operand.
2. Move mode comparison to the beginning to avoid the scenarios of most
strcmp.
I tested the speed improvements for the following backends,
Improvement Ratio
x86_64 197.9%
aarch64 954.5%
riscv 2578.6%
If the build machine is slow, then this improvement can save a lot of time.
I tested the genoutput output for x86_64/aarch64/riscv backends,
and there was no difference compared to before the optimization,
so this shouldn't introduce any functional issues.
gcc/
* genoutput.cc (struct operand_data): Add member 'eq_next' to
point to the next member with the same hash value in the
hash table.
(compare_operands): Move the comparison of the mode to the very
beginning to accelerate the comparison of the two operands.
(struct operand_data_hasher): New, a class that takes into account
the necessary elements for comparing the equality of two operands
in its hash value.
(operand_data_hasher::hash): New.
(operand_data_hasher::equal): New.
(operand_datas): New, hash table of konwn pattern operands.
(place_operands): Use a hash table instead of traversing the array
to find the same operand.
(main): Add initialization of the hash table 'operand_datas'.
(cherry picked from commit ca7936f7764116a39d785bb087584805072a3461)
Diff:
---
gcc/genoutput.cc | 111 +++
1 file changed, 88 insertions(+), 23 deletions(-)
diff --git a/gcc/genoutput.cc b/gcc/genoutput.cc
index efd81766bb5..16fd811b5dd 100644
--- a/gcc/genoutput.cc
+++ b/gcc/genoutput.cc
@@ -91,6 +91,7 @@ along with GCC; see the file COPYING3. If not see
#include "errors.h"
#include "read-md.h"
#include "gensupport.h"
+#include "hash-table.h"
/* No instruction can have more operands than this. Sorry for this
arbitrary limit, but what machine will have an instruction with
@@ -112,6 +113,8 @@ static int next_operand_number = 1;
struct operand_data
{
struct operand_data *next;
+ /* Point to the next member with the same hash value in the hash table. */
+ struct operand_data *eq_next;
int index;
const char *predicate;
const char *constraint;
@@ -127,7 +130,7 @@ struct operand_data
static struct operand_data null_operand =
{
- 0, 0, "", "", E_VOIDmode, 0, 0, 0, 0, 0
+ 0, 0, 0, "", "", E_VOIDmode, 0, 0, 0, 0, 0
};
static struct operand_data *odata = &null_operand;
@@ -174,8 +177,8 @@ static void output_operand_data (void);
static void output_insn_data (void);
static void output_get_insn_name (void);
static void scan_operands (class data *, rtx, int, int);
-static int compare_operands (struct operand_data *,
-struct operand_data *);
+static int compare_operands (const struct operand_data *,
+const struct operand_data *);
static void place_operands (class data *);
static void process_template (class data *, const char *);
static void validate_insn_alternatives (class data *);
@@ -528,10 +531,18 @@ scan_operands (class data *d, rtx part, int
this_address_p,
/* Compare two operands for content equality. */
static int
-compare_operands (struct operand_data *d0, struct operand_data *d1)
+compare_operands (const struct operand_data *d0,
+ const struct operand_data *d1)
{
const char *p0, *p1;
+ /* On one hand, comparing strings for predicate and constraint
+ is time-consuming, and on the other hand, the probability of
+ different modes is relatively high. Therefore, checking the mode
+ first can speed up the execution of the program. */
+ if (d0->mode != d1->mode)
+return 0;
+
p0 = d0->predicate;
if (!p0)
p0 = "";
@@ -550,9 +561,6 @@ compare_operands (struct operand_data *d0, struct
operand_data *d1)
if (strcmp (p0, p1) != 0)
return 0;
- if (d0->mode != d1->mode)
-return 0;
-
if (d0->strict_low != d1->strict_low)
return 0;
@@ -562,6 +570,46 @@ compare_operands (struct operand_data *d0, struct
operand_data *d1)
return 1;
}
+/* This is a class that takes into account the necessary elements for
+ comparing th
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: use fclass insns to implement isfinite, isnormal and isinf builtins
https://gcc.gnu.org/g:7192fa62bb919ca72168af1c31a95ebb6cbcfff6
commit 7192fa62bb919ca72168af1c31a95ebb6cbcfff6
Author: Vineet Gupta
Date: Thu Aug 15 09:24:27 2024 -0700
RISC-V: use fclass insns to implement isfinite,isnormal and isinf builtins
Currently these builtins use float compare instructions which require
FP flags to be saved/restored which could be costly in uarch.
RV Base ISA already has FCLASS.{d,s,h} instruction to compare/identify FP
values w/o disturbing FP exception flags.
Now that upstream supports the corresponding optabs, wire them up in the
backend.
gcc/ChangeLog:
* config/riscv/riscv.md: define_insn for fclass insn.
define_expand for isfinite, isnormal, isinf.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/fclass.c: New tests.
Tested-by: Edwin Lu # pre-commit-CI #2060
Signed-off-by: Vineet Gupta
(cherry picked from commit b0d041f0d4cace06433bf18ae53c40376f2088a7)
Diff:
---
gcc/config/riscv/riscv.md | 63 +
gcc/testsuite/gcc.target/riscv/fclass.c | 38
2 files changed, 101 insertions(+)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 5e3ef789e42..f8d8162c0f9 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -68,6 +68,7 @@
UNSPEC_FMAX
UNSPEC_FMINM
UNSPEC_FMAXM
+ UNSPEC_FCLASS
;; Stack tie
UNSPEC_TIE
@@ -3478,6 +3479,68 @@
(set_attr "mode" "")
(set (attr "length") (const_int 16))])
+;; fclass instruction output bitmap
+;; 0 negative infinity
+;; 1 negative normal number.
+;; 2 negative subnormal number.
+;; 3 -0
+;; 4 +0
+;; 5 positive subnormal number.
+;; 6 positive normal number.
+;; 7 positive infinity
+;; 8 signaling NaN.
+;; 9 quiet NaN
+
+(define_insn "fclass"
+ [(set (match_operand:X0 "register_operand" "=r")
+ (unspec [(match_operand:ANYF 1 "register_operand" " f")]
+ UNSPEC_FCLASS))]
+ "TARGET_HARD_FLOAT"
+ "fclass.\t%0,%1";
+ [(set_attr "type" "fcmp")
+ (set_attr "mode" "")])
+
+;; Implements optab for isfinite, isnormal, isinf
+
+(define_int_iterator FCLASS_MASK [126 66 129])
+(define_int_attr fclass_optab
+ [(126"isfinite")
+ (66 "isnormal")
+ (129"isinf")])
+
+(define_expand "2"
+ [(match_operand 0 "register_operand" "=r")
+ (match_operand:ANYF 1 "register_operand" " f")
+ (const_int FCLASS_MASK)]
+ "TARGET_HARD_FLOAT"
+{
+ if (GET_MODE (operands[0]) != SImode
+ && GET_MODE (operands[0]) != word_mode)
+FAIL;
+
+ rtx t = gen_reg_rtx (word_mode);
+ rtx t_op0 = gen_reg_rtx (word_mode);
+
+ if (TARGET_64BIT)
+emit_insn (gen_fclassdi (t, operands[1]));
+ else
+emit_insn (gen_fclasssi (t, operands[1]));
+
+ riscv_emit_binary (AND, t, t, GEN_INT ());
+ rtx cmp = gen_rtx_NE (word_mode, t, const0_rtx);
+ emit_insn (gen_cstore4 (t_op0, cmp, t, const0_rtx));
+
+ if (TARGET_64BIT)
+{
+ t_op0 = gen_lowpart (SImode, t_op0);
+ SUBREG_PROMOTED_VAR_P (t_op0) = 1;
+ SUBREG_PROMOTED_SET (t_op0, SRP_SIGNED);
+}
+
+ emit_move_insn (operands[0], t_op0);
+ DONE;
+})
+
(define_insn "*seq_zero_"
[(set (match_operand:GPR 0 "register_operand" "=r")
(eq:GPR (match_operand:X 1 "register_operand" " r")
diff --git a/gcc/testsuite/gcc.target/riscv/fclass.c
b/gcc/testsuite/gcc.target/riscv/fclass.c
new file mode 100644
index 000..ea0f173ecf4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/fclass.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target hard_float } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -ftrapping-math" { target { rv64 }
} } */
+/* { dg-options "-march=rv32gc -mabi=ilp32d -ftrapping-math" { target { rv32 }
} } */
+
+int d_isfinite(double a)
+{
+ return __builtin_isfinite(a);
+}
+
+int d_isnormal(double a)
+{
+ return __builtin_isnormal(a);
+}
+
+int d_isinf(double a)
+{
+ return __builtin_isinf(a);
+}
+
+int f_isfinite(float a)
+{
+ return __builtin_isfinite(a);
+}
+
+int f_isnormal(float a)
+{
+ return __builtin_isnormal(a);
+}
+
+int f_isinf(float a)
+{
+ return __builtin_isinf(a);
+}
+
+/* { dg-final { scan-assembler-not {\mfrflags} } } */
+/* { dg-final { scan-assembler-not {\mfsflags} } } */
+/* { dg-final { scan-assembler-times {\tfclass} 6 } } */
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Partial: Just the testsuite bits...
https://gcc.gnu.org/g:84684236ca332f9d4732c9d6c8a892ea058d61a1
commit 84684236ca332f9d4732c9d6c8a892ea058d61a1
Author: Pan Li
Date: Tue Aug 6 20:59:37 2024 +0800
Partial: Just the testsuite bits...
Vect: Make sure the lhs type of .SAT_TRUNC has its mode precision [PR116202]
The .SAT_TRUNC vect pattern recog is valid when the lhs type has
its mode precision. For example as below, QImode with 1 bit precision
like _Bool is invalid here.
g_12 = (long unsigned int) _2;
_13 = MIN_EXPR ;
_3 = (_Bool) _13;
The above pattern cannot be recog as .SAT_TRUNC (g_12) because the dest
only has 1 bit precision with QImode mode. Aka the type doesn't have
the mode precision.
The below tests are passed for this patch.
1. The rv64gcv fully regression tests.
2. The x86 bootstrap tests.
3. The x86 fully regression tests.
PR target/116202
gcc/ChangeLog:
* tree-vect-patterns.cc (vect_recog_sat_trunc_pattern): Add the
type_has_mode_precision_p check for the lhs type.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr116202-run-1.c: New test.
Signed-off-by: Pan Li
(cherry picked from commit 06d3f31384a89039c510531cf8012caed05b2ffd)
Diff:
---
.../gcc.target/riscv/rvv/base/pr116202-run-1.c | 24 ++
1 file changed, 24 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c
new file mode 100644
index 000..d150f20b5d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -march=rv64gcv_zvl256b -fdump-rtl-expand-details" } */
+
+int b[24];
+_Bool c[24];
+
+int main() {
+ for (int f = 0; f < 4; ++f)
+b[f] = 6;
+
+ for (int f = 0; f < 24; f += 4)
+c[f] = ({
+ int g = ({
+unsigned long g = -b[f];
+1 < g ? 1 : g;
+ });
+ g;
+});
+
+ if (c[0] != 1)
+__builtin_abort ();
+}
+
+/* { dg-final { scan-rtl-dump-not ".SAT_TRUNC " "expand" } } */
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Restrict pr116202-run-1.c test to riscv_v target
https://gcc.gnu.org/g:aa312daf3cf0333d369f9a9abaf5b356881cad0e
commit aa312daf3cf0333d369f9a9abaf5b356881cad0e
Author: Mark Wielaard
Date: Mon Aug 12 22:25:42 2024 +0200
Restrict pr116202-run-1.c test to riscv_v target
The testcase uses -march=rv64gcv and dg-do run, so should be
restricted to a riscv_v target.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr116202-run-1.c (dg-do run):
Add target riscv_v.
(cherry picked from commit 42aba4786e42ac2317b4f1185a93bffb3de2ce50)
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c
index 02814183dbb..979989f8a85 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c
@@ -1,4 +1,4 @@
-/* { dg-do run } */
+/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-O3 -march=rv64gcv_zvl256b -mabi=lp64d
-fdump-rtl-expand-details" } */
int b[24];
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix missing abi arg in test
https://gcc.gnu.org/g:48816efb27d1ed055eebc41fac543d183784f85e
commit 48816efb27d1ed055eebc41fac543d183784f85e
Author: Edwin Lu
Date: Wed Aug 7 10:34:10 2024 -0700
RISC-V: Fix missing abi arg in test
The following test was failing when building on 32 bit targets
due to not overwriting the mabi arg. This resulted in dejagnu
attempting to run the test with -mabi=ilp32d -march=rv64gcv_zvl256b
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr116202-run-1.c: Add mabi arg
Signed-off-by: Edwin Lu
(cherry picked from commit ef90a136da4c3e0b28997da25c30fdce1bcb115c)
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c
index d150f20b5d9..02814183dbb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-O3 -march=rv64gcv_zvl256b -fdump-rtl-expand-details" } */
+/* { dg-options "-O3 -march=rv64gcv_zvl256b -mabi=lp64d
-fdump-rtl-expand-details" } */
int b[24];
_Bool c[24];
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] testsuite: fix dg-add-options vs. dg-options ordering
https://gcc.gnu.org/g:d9c50df2fcbf50b078a31c0d876a68b25b0f4d4a
commit d9c50df2fcbf50b078a31c0d876a68b25b0f4d4a
Author: Sam James
Date: Sat Jul 27 00:31:54 2024 +0100
testsuite: fix dg-add-options vs. dg-options ordering
Per gccint, dg-add-options must be placed after all dg-options directives.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/cmpmem-2.c: Fix dg-add-options order.
(cherry picked from commit 542e3c4f0551f9a239163d09d98527d8d7d0200d)
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-2.c
index c782cc6c6e6..fdb402a787b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-2.c
@@ -1,6 +1,6 @@
/* { dg-do run { target { riscv_v } } } */
-/* { dg-add-options riscv_v } */
/* { dg-options "-O2 -mrvv-max-lmul=dynamic" } */
+/* { dg-add-options riscv_v } */
#include
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Manual application of riscv specific changes from:
https://gcc.gnu.org/g:0c66fc473a560e3cf87b07568044aec60dfad0a4
commit 0c66fc473a560e3cf87b07568044aec60dfad0a4
Author: Jeff Law
Date: Fri Aug 16 13:24:27 2024 -0600
Manual application of riscv specific changes from:
commit 2e662dedf84aa23fdff7bceca040432bf9f1ab72
Author: Sam James
Date: Tue Jul 30 12:20:47 2024 +0100
testsuite: fix whitespace in dg-do compile directives
Nothing seems to change here in reality at least on x86_64-pc-linux-gnu,
but important to fix nonetheless in case people copy it.
PR rtl-optimization/48633
PR tree-optimization/83072
PR tree-optimization/83073
PR tree-optimization/96542
PR tree-optimization/96707
PR tree-optimization/97567
PR target/69225
PR target/89929
PR target/96562
* g++.dg/pr48633.C: Fix whitespace in dg directive.
* g++.dg/pr96707.C: Likewise.
* g++.target/i386/mv28.C: Likewise.
* gcc.dg/Warray-bounds-flex-arrays-1.c: Likewise.
* gcc.dg/pr83072-2.c: Likewise.
* gcc.dg/pr83073.c: Likewise.
* gcc.dg/pr96542.c: Likewise.
* gcc.dg/pr97567-2.c: Likewise.
* gcc.target/i386/avx512fp16-11a.c: Likewise.
* gcc.target/i386/avx512fp16-13.c: Likewise.
* gcc.target/i386/avx512fp16-14.c: Likewise.
* gcc.target/i386/avx512fp16-conjugation-1.c: Likewise.
* gcc.target/i386/avx512fp16-neg-1a.c: Likewise.
* gcc.target/i386/avx512fp16-set1-pch-1a.c: Likewise.
* gcc.target/i386/avx512fp16vl-conjugation-1.c: Likewise.
* gcc.target/i386/avx512fp16vl-neg-1a.c: Likewise.
* gcc.target/i386/avx512fp16vl-set1-pch-1a.c: Likewise.
* gcc.target/i386/avx512vlfp16-11a.c: Likewise.
* gcc.target/i386/pr69225-1.c: Likewise.
* gcc.target/i386/pr69225-2.c: Likewise.
* gcc.target/i386/pr69225-3.c: Likewise.
* gcc.target/i386/pr69225-4.c: Likewise.
* gcc.target/i386/pr69225-5.c: Likewise.
* gcc.target/i386/pr69225-6.c: Likewise.
* gcc.target/i386/pr69225-7.c: Likewise.
* gcc.target/i386/pr96562-1.c: Likewise.
* gcc.target/riscv/rv32e_stack.c: Likewise.
* gfortran.dg/c-interop/removed-restrictions-3.f90: Likewise.
* gnat.dg/renaming1.adb: Likewise.
Diff:
---
gcc/testsuite/gcc.target/riscv/rv32e_stack.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rv32e_stack.c
b/gcc/testsuite/gcc.target/riscv/rv32e_stack.c
index cec90ede4b5..04aa230c52a 100644
--- a/gcc/testsuite/gcc.target/riscv/rv32e_stack.c
+++ b/gcc/testsuite/gcc.target/riscv/rv32e_stack.c
@@ -1,4 +1,4 @@
-/* { dg-do compile} */
+/* { dg-do compile } */
/* { dg-options "-O0 -march=rv32e -mabi=ilp32e -fomit-frame-pointer" } */
int getInt();
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Manual applicatoin of riscv specific changes from:
https://gcc.gnu.org/g:e6b322cc9a99caf4805952efc3ee1a4a6d0f8988
commit e6b322cc9a99caf4805952efc3ee1a4a6d0f8988
Author: Jeff Law
Date: Fri Aug 16 13:27:37 2024 -0600
Manual applicatoin of riscv specific changes from:
commit acc70606c59e3f14072cc8a164362e728d8df5d6
Author: Sam James
Date: Tue Jul 30 20:04:40 2024 +0100
testsuite: fix 'dg-compile' typos
'dg-compile' is not a thing, replace it with 'dg-do compile'.
PR target/68015
PR c++/83979
* c-c++-common/goacc/loop-shape.c: Fix 'dg-compile' typo.
* g++.dg/pr83979.C: Likewise.
* g++.target/aarch64/sve/acle/general-c++/attributes_2.C:
Likewise.
* gcc.dg/tree-ssa/builtin-sprintf-7.c: Likewise.
* gcc.dg/tree-ssa/builtin-sprintf-8.c: Likewise.
* gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c: Likewise.
* gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c:
Likewise.
* gcc.target/s390/20181024-1.c: Likewise.
* gcc.target/s390/addr-constraints-1.c: Likewise.
* gcc.target/s390/arch12/aghsghmgh-1.c: Likewise.
* gcc.target/s390/arch12/mul-1.c: Likewise.
* gcc.target/s390/arch13/bitops-1.c: Likewise.
* gcc.target/s390/arch13/bitops-2.c: Likewise.
* gcc.target/s390/arch13/fp-signedint-convert-1.c: Likewise.
* gcc.target/s390/arch13/fp-unsignedint-convert-1.c: Likewise.
* gcc.target/s390/arch13/popcount-1.c: Likewise.
* gcc.target/s390/pr68015.c: Likewise.
* gcc.target/s390/vector/fp-signedint-convert-1.c: Likewise.
* gcc.target/s390/vector/fp-unsignedint-convert-1.c: Likewise.
* gcc.target/s390/vector/reverse-elements-1.c: Likewise.
* gcc.target/s390/vector/reverse-elements-2.c: Likewise.
* gcc.target/s390/vector/reverse-elements-3.c: Likewise.
* gcc.target/s390/vector/reverse-elements-4.c: Likewise.
* gcc.target/s390/vector/reverse-elements-5.c: Likewise.
* gcc.target/s390/vector/reverse-elements-6.c: Likewise.
* gcc.target/s390/vector/reverse-elements-7.c: Likewise.
* gnat.dg/alignment15.adb: Likewise.
* gnat.dg/debug4.adb: Likewise.
* gnat.dg/inline21.adb: Likewise.
* gnat.dg/inline22.adb: Likewise.
* gnat.dg/opt37.adb: Likewise.
* gnat.dg/warn13.adb: Likewise.
Diff:
---
gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c | 2 +-
gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c
b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c
index 85841fd7036..58211207186 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c
@@ -1,5 +1,5 @@
/* Test __atomic routines for existence on 2 byte values with each valid
memory model. */
-/* { dg-compile } */
+/* { dg-do compile } */
/* { dg-options "-Wno-address-of-packed-member" } */
/* { dg-add-options riscv_zabha } */
/* { dg-remove-options riscv_ztso } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c
b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c
index edc0a2c8f8e..c846ca48d72 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c
@@ -1,5 +1,5 @@
/* Test __atomic routines for existence on 2 byte values with each valid
memory model. */
-/* { dg-compile } */
+/* { dg-do compile } */
/* { dg-options "-Wno-address-of-packed-member" } */
/* { dg-add-options riscv_zabha } */
/* { dg-remove-options riscv_ztso } */
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Drop accidental hunk.
https://gcc.gnu.org/g:0a279dfd56e5e38bf3c23257b92bab1ccfcd0747 commit 0a279dfd56e5e38bf3c23257b92bab1ccfcd0747 Author: Jeff Law Date: Fri Aug 16 13:52:44 2024 -0600 Drop accidental hunk. Not worth the effort to find the patch where it got incorrectly introduced (duplicate). Diff: --- gcc/config/riscv/riscv-subset.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-subset.h index ed7ca4d44fd..dace4de6575 100644 --- a/gcc/config/riscv/riscv-subset.h +++ b/gcc/config/riscv/riscv-subset.h @@ -62,9 +62,6 @@ private: /* X-len of m_arch. */ unsigned m_xlen; - /* Allow adding the same extension more than once. */ - bool m_allow_adding_dup; - /* Number of subsets. */ unsigned m_subset_num;
[gcc r15-2957] Fix maybe-uninitialized CodeView LF_INDEX warning
https://gcc.gnu.org/g:2e2a1cae88522b1966ec01db4c5fda4dbb5949ef commit r15-2957-g2e2a1cae88522b1966ec01db4c5fda4dbb5949ef Author: Mark Harmstone Date: Mon Aug 12 23:19:55 2024 +0100 Fix maybe-uninitialized CodeView LF_INDEX warning Initialize last_type to 0 to silence two spurious maybe-uninitialized warnings. We issue an LF_INDEX continuation subtype for any LF_FIELDLISTs that overflow, so LF_INDEXes will always have a subtype preceding them (and thus last_type will always be set). gcc/ * dwarf2codeview.cc (get_type_num_enumeration_type): Initialize last_type to 0. (get_type_num_struct): Likewise. Diff: --- gcc/dwarf2codeview.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/dwarf2codeview.cc b/gcc/dwarf2codeview.cc index f7107021bc7..7e4faaa9388 100644 --- a/gcc/dwarf2codeview.cc +++ b/gcc/dwarf2codeview.cc @@ -2448,7 +2448,7 @@ get_type_num_enumeration_type (dw_die_ref type, bool in_struct) dw_die_ref first_child; codeview_custom_type *ct; uint16_t count = 0; - uint32_t last_type; + uint32_t last_type = 0; if (get_AT_flag (type, DW_AT_declaration)) return add_enum_forward_def (type); @@ -2726,7 +2726,7 @@ get_type_num_struct (dw_die_ref type, bool in_struct, bool *is_fwd_ref) dw_die_ref first_child; codeview_custom_type *ct; uint16_t num_members = 0; - uint32_t last_type; + uint32_t last_type = 0; const char *name; if ((in_struct && get_AT_string (type, DW_AT_name))
[gcc r15-2958] Write CodeView information about local static variables
https://gcc.gnu.org/g:85e0d6723e7e056c079787486837bfb4f2fa6b8d
commit r15-2958-g85e0d6723e7e056c079787486837bfb4f2fa6b8d
Author: Mark Harmstone
Date: Sat Jul 13 21:32:40 2024 +0100
Write CodeView information about local static variables
Outputs CodeView S_LDATA32 symbols, for static variables within
functions, along with S_BLOCK32 and S_END for the beginning and end of
lexical blocks.
gcc/
* dwarf2codeview.cc (enum cv_sym_type): Add S_END and S_BLOCK32.
(write_local_s_ldata32): New function.
(write_unoptimized_local_variable): New function.
(write_s_block32): New function.
(write_s_end): New function.
(write_unoptimized_function_vars): New function.
(write_function): Call write_unoptimized_function_vars.
Diff:
---
gcc/dwarf2codeview.cc | 258 ++
1 file changed, 258 insertions(+)
diff --git a/gcc/dwarf2codeview.cc b/gcc/dwarf2codeview.cc
index 7e4faaa9388..cb2d64bfcc6 100644
--- a/gcc/dwarf2codeview.cc
+++ b/gcc/dwarf2codeview.cc
@@ -70,6 +70,8 @@ along with GCC; see the file COPYING3. If not see
/* This is enum SYM_ENUM_e in Microsoft's cvinfo.h. */
enum cv_sym_type {
+ S_END = 0x0006,
+ S_BLOCK32 = 0x1103,
S_LDATA32 = 0x110c,
S_GDATA32 = 0x110d,
S_COMPILE3 = 0x113c,
@@ -986,6 +988,260 @@ end:
free (s->data_symbol.name);
}
+/* Write an S_LDATA32 symbol, representing a static variable within a function.
+ This symbol can also appear outside of a function block - see
+ write_data_symbol. */
+
+static void
+write_local_s_ldata32 (dw_die_ref die, dw_loc_descr_ref loc_ref)
+{
+ unsigned int label_num = ++sym_label_num;
+ const char *name = get_AT_string (die, DW_AT_name);
+ uint32_t type;
+
+ /* This is struct datasym in binutils:
+
+ struct datasym
+ {
+ uint16_t size;
+ uint16_t kind;
+ uint32_t type;
+ uint32_t offset;
+ uint16_t section;
+ char name[];
+ } ATTRIBUTE_PACKED;
+ */
+
+ fputs (integer_asm_op (2, false), asm_out_file);
+ asm_fprintf (asm_out_file,
+ "%L" SYMBOL_END_LABEL "%u - %L" SYMBOL_START_LABEL "%u\n",
+ label_num, label_num);
+
+ targetm.asm_out.internal_label (asm_out_file, SYMBOL_START_LABEL, label_num);
+
+ fputs (integer_asm_op (2, false), asm_out_file);
+ fprint_whex (asm_out_file, S_LDATA32);
+ putc ('\n', asm_out_file);
+
+ type = get_type_num (get_AT_ref (die, DW_AT_type), false, false);
+
+ fputs (integer_asm_op (4, false), asm_out_file);
+ fprint_whex (asm_out_file, type);
+ putc ('\n', asm_out_file);
+
+ asm_fprintf (asm_out_file, "\t.secrel32 ");
+ output_addr_const (asm_out_file, loc_ref->dw_loc_oprnd1.v.val_addr);
+ fputc ('\n', asm_out_file);
+
+ asm_fprintf (asm_out_file, "\t.secidx ");
+ output_addr_const (asm_out_file, loc_ref->dw_loc_oprnd1.v.val_addr);
+ fputc ('\n', asm_out_file);
+
+ ASM_OUTPUT_ASCII (asm_out_file, name, strlen (name) + 1);
+
+ ASM_OUTPUT_ALIGN (asm_out_file, 2);
+
+ targetm.asm_out.internal_label (asm_out_file, SYMBOL_END_LABEL, label_num);
+}
+
+/* Write a symbol representing an unoptimized variable within a function, if
+ we're able to translate the DIE's DW_AT_location into its CodeView
+ equivalent. */
+
+static void
+write_unoptimized_local_variable (dw_die_ref die)
+{
+ dw_attr_node *loc;
+ dw_loc_descr_ref loc_ref;
+
+ loc = get_AT (die, DW_AT_location);
+ if (!loc)
+return;
+
+ if (loc->dw_attr_val.val_class != dw_val_class_loc)
+return;
+
+ loc_ref = loc->dw_attr_val.v.val_loc;
+ if (!loc_ref)
+return;
+
+ switch (loc_ref->dw_loc_opc)
+{
+case DW_OP_addr:
+ write_local_s_ldata32 (die, loc_ref);
+ break;
+
+default:
+ break;
+}
+}
+
+/* Translate a DW_TAG_lexical_block DIE into an S_BLOCK32 symbol, representing
+ a block within an unoptimized function. Returns false if we're not able
+ to resolve the location, which will prevent the caller from issuing an
+ unneeded S_END. */
+
+static bool
+write_s_block32 (dw_die_ref die)
+{
+ unsigned int label_num = ++sym_label_num;
+ dw_attr_node *loc_low, *loc_high;
+ const char *label_low, *label_high;
+ rtx rtx_low, rtx_high;
+
+ /* This is struct blocksym in binutils and BLOCKSYM32 in Microsoft's
+ cvinfo.h:
+
+struct blocksym
+{
+ uint16_t size;
+ uint16_t kind;
+ uint32_t parent;
+ uint32_t end;
+ uint32_t len;
+ uint32_t offset;
+ uint16_t section;
+ char name[];
+} ATTRIBUTE_PACKED;
+ */
+
+ loc_low = get_AT (die, DW_AT_low_pc);
+ if (!loc_low)
+return false;
+
+ if (loc_low->dw_attr_val.val_class != dw_val_class_lbl_id)
+return false;
+
+ label_low = loc_low->dw_attr_val.v.val_lbl_id;
+ if (!label_low)
+return false;
+
+ rtx_low = gen_rtx_SYMBOL_REF (Pmode, label_low);
+
+ loc_high = get_AT (die, DW_AT_high_pc);
+ if (!loc_high)
+return false;
+
+ if (lo
[gcc r15-2959] Write CodeView information about enregistered variables
https://gcc.gnu.org/g:af61fc99f7a98efd6446692cc61d9fa43f6173a4
commit r15-2959-gaf61fc99f7a98efd6446692cc61d9fa43f6173a4
Author: Mark Harmstone
Date: Thu Aug 8 02:36:41 2024 +0100
Write CodeView information about enregistered variables
Outputs CodeView S_REGISTER symbols, representing local variables or
parameters that are held in a register.
gcc/
* dwarf2codeview.cc (enum cv_sym_type): Add S_REGISTER.
(enum cv_x86_register): New type.
(enum cv_amd64_register): New type.
(dwarf_reg_to_cv): New function.
(write_s_register): New function.
(write_unoptimized_local_variable): Handle parameters and DW_OP_reg*
location types.
Diff:
---
gcc/dwarf2codeview.cc | 1188 +
1 file changed, 1188 insertions(+)
diff --git a/gcc/dwarf2codeview.cc b/gcc/dwarf2codeview.cc
index cb2d64bfcc6..4596408f2bb 100644
--- a/gcc/dwarf2codeview.cc
+++ b/gcc/dwarf2codeview.cc
@@ -72,6 +72,7 @@ along with GCC; see the file COPYING3. If not see
enum cv_sym_type {
S_END = 0x0006,
S_BLOCK32 = 0x1103,
+ S_REGISTER = 0x1106,
S_LDATA32 = 0x110c,
S_GDATA32 = 0x110d,
S_COMPILE3 = 0x113c,
@@ -110,6 +111,962 @@ enum cv_leaf_type {
LF_UQUADWORD = 0x800a
};
+/* These come from enum CV_HREG_e in Microsoft's cvconst.h. */
+
+enum cv_x86_register {
+ CV_REG_NONE = 0,
+ CV_REG_AL = 1,
+ CV_REG_CL = 2,
+ CV_REG_DL = 3,
+ CV_REG_BL = 4,
+ CV_REG_AH = 5,
+ CV_REG_CH = 6,
+ CV_REG_DH = 7,
+ CV_REG_BH = 8,
+ CV_REG_AX = 9,
+ CV_REG_CX = 10,
+ CV_REG_DX = 11,
+ CV_REG_BX = 12,
+ CV_REG_SP = 13,
+ CV_REG_BP = 14,
+ CV_REG_SI = 15,
+ CV_REG_DI = 16,
+ CV_REG_EAX = 17,
+ CV_REG_ECX = 18,
+ CV_REG_EDX = 19,
+ CV_REG_EBX = 20,
+ CV_REG_ESP = 21,
+ CV_REG_EBP = 22,
+ CV_REG_ESI = 23,
+ CV_REG_EDI = 24,
+ CV_REG_ES = 25,
+ CV_REG_CS = 26,
+ CV_REG_SS = 27,
+ CV_REG_DS = 28,
+ CV_REG_FS = 29,
+ CV_REG_GS = 30,
+ CV_REG_IP = 31,
+ CV_REG_FLAGS = 32,
+ CV_REG_EIP = 33,
+ CV_REG_EFLAGS = 34,
+ CV_REG_TEMP = 40,
+ CV_REG_TEMPH = 41,
+ CV_REG_QUOTE = 42,
+ CV_REG_PCDR3 = 43,
+ CV_REG_PCDR4 = 44,
+ CV_REG_PCDR5 = 45,
+ CV_REG_PCDR6 = 46,
+ CV_REG_PCDR7 = 47,
+ CV_REG_CR0 = 80,
+ CV_REG_CR1 = 81,
+ CV_REG_CR2 = 82,
+ CV_REG_CR3 = 83,
+ CV_REG_CR4 = 84,
+ CV_REG_DR0 = 90,
+ CV_REG_DR1 = 91,
+ CV_REG_DR2 = 92,
+ CV_REG_DR3 = 93,
+ CV_REG_DR4 = 94,
+ CV_REG_DR5 = 95,
+ CV_REG_DR6 = 96,
+ CV_REG_DR7 = 97,
+ CV_REG_GDTR = 110,
+ CV_REG_GDTL = 111,
+ CV_REG_IDTR = 112,
+ CV_REG_IDTL = 113,
+ CV_REG_LDTR = 114,
+ CV_REG_TR = 115,
+ CV_REG_PSEUDO1 = 116,
+ CV_REG_PSEUDO2 = 117,
+ CV_REG_PSEUDO3 = 118,
+ CV_REG_PSEUDO4 = 119,
+ CV_REG_PSEUDO5 = 120,
+ CV_REG_PSEUDO6 = 121,
+ CV_REG_PSEUDO7 = 122,
+ CV_REG_PSEUDO8 = 123,
+ CV_REG_PSEUDO9 = 124,
+ CV_REG_ST0 = 128,
+ CV_REG_ST1 = 129,
+ CV_REG_ST2 = 130,
+ CV_REG_ST3 = 131,
+ CV_REG_ST4 = 132,
+ CV_REG_ST5 = 133,
+ CV_REG_ST6 = 134,
+ CV_REG_ST7 = 135,
+ CV_REG_CTRL = 136,
+ CV_REG_STAT = 137,
+ CV_REG_TAG = 138,
+ CV_REG_FPIP = 139,
+ CV_REG_FPCS = 140,
+ CV_REG_FPDO = 141,
+ CV_REG_FPDS = 142,
+ CV_REG_ISEM = 143,
+ CV_REG_FPEIP = 144,
+ CV_REG_FPEDO = 145,
+ CV_REG_MM0 = 146,
+ CV_REG_MM1 = 147,
+ CV_REG_MM2 = 148,
+ CV_REG_MM3 = 149,
+ CV_REG_MM4 = 150,
+ CV_REG_MM5 = 151,
+ CV_REG_MM6 = 152,
+ CV_REG_MM7 = 153,
+ CV_REG_XMM0 = 154,
+ CV_REG_XMM1 = 155,
+ CV_REG_XMM2 = 156,
+ CV_REG_XMM3 = 157,
+ CV_REG_XMM4 = 158,
+ CV_REG_XMM5 = 159,
+ CV_REG_XMM6 = 160,
+ CV_REG_XMM7 = 161,
+ CV_REG_XMM00 = 162,
+ CV_REG_XMM01 = 163,
+ CV_REG_XMM02 = 164,
+ CV_REG_XMM03 = 165,
+ CV_REG_XMM10 = 166,
+ CV_REG_XMM11 = 167,
+ CV_REG_XMM12 = 168,
+ CV_REG_XMM13 = 169,
+ CV_REG_XMM20 = 170,
+ CV_REG_XMM21 = 171,
+ CV_REG_XMM22 = 172,
+ CV_REG_XMM23 = 173,
+ CV_REG_XMM30 = 174,
+ CV_REG_XMM31 = 175,
+ CV_REG_XMM32 = 176,
+ CV_REG_XMM33 = 177,
+ CV_REG_XMM40 = 178,
+ CV_REG_XMM41 = 179,
+ CV_REG_XMM42 = 180,
+ CV_REG_XMM43 = 181,
+ CV_REG_XMM50 = 182,
+ CV_REG_XMM51 = 183,
+ CV_REG_XMM52 = 184,
+ CV_REG_XMM53 = 185,
+ CV_REG_XMM60 = 186,
+ CV_REG_XMM61 = 187,
+ CV_REG_XMM62 = 188,
+ CV_REG_XMM63 = 189,
+ CV_REG_XMM70 = 190,
+ CV_REG_XMM71 = 191,
+ CV_REG_XMM72 = 192,
+ CV_REG_XMM73 = 193,
+ CV_REG_XMM0L = 194,
+ CV_REG_XMM1L = 195,
+ CV_REG_XMM2L = 196,
+ CV_REG_XMM3L = 197,
+ CV_REG_XMM4L = 198,
+ CV_REG_XMM5L = 199,
+ CV_REG_XMM6L = 200,
+ CV_REG_XMM7L = 201,
+ CV_REG_XMM0H = 202,
+ CV_REG_XMM1H = 203,
+ CV_REG_XMM2H = 204,
+ CV_REG_XMM3H = 205,
+ CV_REG_XMM4H = 206,
+ CV_REG_XMM5H = 207,
+ CV_REG_XMM6H = 208,
+ CV_REG_XMM7H = 209,
+ CV_REG_MXCSR = 211,
+ CV_REG_EDXEAX = 212,
+ CV_REG_EMM0L = 220,
+ CV_REG_EMM1L = 221,
+ CV_REG_EMM2L = 222,
+ CV_REG_EMM3L = 223,
+ CV_REG_EMM4L = 224,
+ CV_REG_EMM5L = 225,
+ CV_REG_EMM6L = 226,
+ CV_REG_EMM7L = 227,
+ CV_REG_EMM0H = 228,
+ CV_REG_EMM1H = 229,
+ CV_REG
[gcc r15-2960] Write CodeView information about stack variables
https://gcc.gnu.org/g:1e7dabbbe271bee0a9610dfdb0d62647c04a6194
commit r15-2960-g1e7dabbbe271bee0a9610dfdb0d62647c04a6194
Author: Mark Harmstone
Date: Thu Aug 8 02:38:54 2024 +0100
Write CodeView information about stack variables
Outputs CodeView S_REGREL32 symbols for unoptimized local variables that
are stored on the stack. This includes a change to dwarf2out.cc to make
it easier to extract the function frame base without having to worry
about the function prologue or epilogue.
gcc/
* dwarf2codeview.cc (enum cv_sym_type): Add S_REGREL32.
(write_fbreg_variable): New function.
(write_unoptimized_local_variable): Add fblock parameter, and handle
DW_OP_fbreg locations.
(write_unoptimized_function_vars): Add fbloc parameter.
(write_function): Extract frame base from DWARF.
* dwarf2out.cc (convert_cfa_to_fb_loc_list): Output simplified frame
base information for CodeView.
Diff:
---
gcc/dwarf2codeview.cc | 105 +++---
gcc/dwarf2out.cc | 23 +++
2 files changed, 122 insertions(+), 6 deletions(-)
diff --git a/gcc/dwarf2codeview.cc b/gcc/dwarf2codeview.cc
index 4596408f2bb..e01515a0ec4 100644
--- a/gcc/dwarf2codeview.cc
+++ b/gcc/dwarf2codeview.cc
@@ -75,6 +75,7 @@ enum cv_sym_type {
S_REGISTER = 0x1106,
S_LDATA32 = 0x110c,
S_GDATA32 = 0x110d,
+ S_REGREL32 = 0x,
S_COMPILE3 = 0x113c,
S_LPROC32_ID = 0x1146,
S_GPROC32_ID = 0x1147,
@@ -2195,12 +2196,94 @@ write_s_register (dw_die_ref die, dw_loc_descr_ref
loc_ref)
targetm.asm_out.internal_label (asm_out_file, SYMBOL_END_LABEL, label_num);
}
+/* Write an S_REGREL32 symbol in order to represent an unoptimized stack
+ variable. The memory address is given by a register value plus an offset,
+ so we need to parse the function's DW_AT_frame_base attribute for this. */
+
+static void
+write_fbreg_variable (dw_die_ref die, dw_loc_descr_ref loc_ref,
+ dw_loc_descr_ref fbloc)
+{
+ unsigned int label_num = ++sym_label_num;
+ const char *name = get_AT_string (die, DW_AT_name);
+ uint32_t type;
+ uint16_t regno;
+ int offset;
+
+ /* This is struct regrel in binutils and REGREL32 in Microsoft's cvinfo.h:
+
+struct regrel
+{
+ uint16_t size;
+ uint16_t kind;
+ uint32_t offset;
+ uint32_t type;
+ uint16_t reg;
+ char name[];
+} ATTRIBUTE_PACKED;
+ */
+
+ if (!fbloc)
+return;
+
+ if (fbloc->dw_loc_opc >= DW_OP_breg0 && fbloc->dw_loc_opc <= DW_OP_breg31)
+{
+ regno = dwarf_reg_to_cv (fbloc->dw_loc_opc - DW_OP_breg0);
+ offset = fbloc->dw_loc_oprnd1.v.val_int;
+}
+ else if (fbloc->dw_loc_opc == DW_OP_bregx)
+{
+ regno = dwarf_reg_to_cv (fbloc->dw_loc_oprnd1.v.val_int);
+ offset = fbloc->dw_loc_oprnd2.v.val_int;
+}
+ else
+{
+ return;
+}
+
+ if (loc_ref->dw_loc_oprnd1.val_class != dw_val_class_unsigned_const)
+return;
+
+ offset += loc_ref->dw_loc_oprnd1.v.val_int;
+
+ fputs (integer_asm_op (2, false), asm_out_file);
+ asm_fprintf (asm_out_file,
+ "%L" SYMBOL_END_LABEL "%u - %L" SYMBOL_START_LABEL "%u\n",
+ label_num, label_num);
+
+ targetm.asm_out.internal_label (asm_out_file, SYMBOL_START_LABEL, label_num);
+
+ fputs (integer_asm_op (2, false), asm_out_file);
+ fprint_whex (asm_out_file, S_REGREL32);
+ putc ('\n', asm_out_file);
+
+ fputs (integer_asm_op (4, false), asm_out_file);
+ fprint_whex (asm_out_file, offset);
+ putc ('\n', asm_out_file);
+
+ type = get_type_num (get_AT_ref (die, DW_AT_type), false, false);
+
+ fputs (integer_asm_op (4, false), asm_out_file);
+ fprint_whex (asm_out_file, type);
+ putc ('\n', asm_out_file);
+
+ fputs (integer_asm_op (2, false), asm_out_file);
+ fprint_whex (asm_out_file, regno);
+ putc ('\n', asm_out_file);
+
+ ASM_OUTPUT_ASCII (asm_out_file, name, strlen (name) + 1);
+
+ ASM_OUTPUT_ALIGN (asm_out_file, 2);
+
+ targetm.asm_out.internal_label (asm_out_file, SYMBOL_END_LABEL, label_num);
+}
+
/* Write a symbol representing an unoptimized variable within a function, if
we're able to translate the DIE's DW_AT_location into its CodeView
equivalent. */
static void
-write_unoptimized_local_variable (dw_die_ref die)
+write_unoptimized_local_variable (dw_die_ref die, dw_loc_descr_ref fbloc)
{
dw_attr_node *loc;
dw_loc_descr_ref loc_ref;
@@ -2258,6 +2341,10 @@ write_unoptimized_local_variable (dw_die_ref die)
write_s_register (die, loc_ref);
break;
+case DW_OP_fbreg:
+ write_fbreg_variable (die, loc_ref, fbloc);
+ break;
+
default:
break;
}
@@ -2390,7 +2477,7 @@ write_s_end (void)
or blocks that we encounter. */
static void
-write_unoptimized_function_vars (dw_die_ref die)
+write_unoptimized_function_vars (dw_die_ref die, dw_loc_descr_ref fbloc)
{
dw_die_ref first_child, c;
[gcc] Created branch 'meissner/heads/work176' in namespace 'refs/users'
The branch 'meissner/heads/work176' was created in namespace 'refs/users' pointing to: 1e7dabbbe27... Write CodeView information about stack variables
[gcc(refs/users/meissner/heads/work176)] Add ChangeLog.meissner and REVISION.
https://gcc.gnu.org/g:9bd8691e25ca16ebbe2385182d8f7d5bc16bd32c commit 9bd8691e25ca16ebbe2385182d8f7d5bc16bd32c Author: Michael Meissner Date: Fri Aug 16 20:00:35 2024 -0400 Add ChangeLog.meissner and REVISION. 2024-08-16 Michael Meissner gcc/ * REVISION: New file for branch. * ChangeLog.meissner: New file. gcc/c-family/ * ChangeLog.meissner: New file. gcc/c/ * ChangeLog.meissner: New file. gcc/cp/ * ChangeLog.meissner: New file. gcc/fortran/ * ChangeLog.meissner: New file. gcc/testsuite/ * ChangeLog.meissner: New file. libgcc/ * ChangeLog.meissner: New file. Diff: --- gcc/ChangeLog.meissner | 6 ++ gcc/REVISION | 1 + gcc/c-family/ChangeLog.meissner | 6 ++ gcc/c/ChangeLog.meissner | 6 ++ gcc/cp/ChangeLog.meissner| 6 ++ gcc/fortran/ChangeLog.meissner | 6 ++ gcc/testsuite/ChangeLog.meissner | 6 ++ libgcc/ChangeLog.meissner| 6 ++ libstdc++-v3/ChangeLog.meissner | 6 ++ 9 files changed, 49 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner new file mode 100644 index 000..6bd73d667fe --- /dev/null +++ b/gcc/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work176, baseline + +2024-08-16 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index 000..9974885ad20 --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work176 branch diff --git a/gcc/c-family/ChangeLog.meissner b/gcc/c-family/ChangeLog.meissner new file mode 100644 index 000..6bd73d667fe --- /dev/null +++ b/gcc/c-family/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work176, baseline + +2024-08-16 Michael Meissner + + Clone branch + diff --git a/gcc/c/ChangeLog.meissner b/gcc/c/ChangeLog.meissner new file mode 100644 index 000..6bd73d667fe --- /dev/null +++ b/gcc/c/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work176, baseline + +2024-08-16 Michael Meissner + + Clone branch + diff --git a/gcc/cp/ChangeLog.meissner b/gcc/cp/ChangeLog.meissner new file mode 100644 index 000..6bd73d667fe --- /dev/null +++ b/gcc/cp/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work176, baseline + +2024-08-16 Michael Meissner + + Clone branch + diff --git a/gcc/fortran/ChangeLog.meissner b/gcc/fortran/ChangeLog.meissner new file mode 100644 index 000..6bd73d667fe --- /dev/null +++ b/gcc/fortran/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work176, baseline + +2024-08-16 Michael Meissner + + Clone branch + diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner new file mode 100644 index 000..6bd73d667fe --- /dev/null +++ b/gcc/testsuite/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work176, baseline + +2024-08-16 Michael Meissner + + Clone branch + diff --git a/libgcc/ChangeLog.meissner b/libgcc/ChangeLog.meissner new file mode 100644 index 000..6bd73d667fe --- /dev/null +++ b/libgcc/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work176, baseline + +2024-08-16 Michael Meissner + + Clone branch + diff --git a/libstdc++-v3/ChangeLog.meissner b/libstdc++-v3/ChangeLog.meissner new file mode 100644 index 000..6bd73d667fe --- /dev/null +++ b/libstdc++-v3/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work176, baseline + +2024-08-16 Michael Meissner + + Clone branch +
[gcc] Created branch 'meissner/heads/work176-dmf' in namespace 'refs/users'
The branch 'meissner/heads/work176-dmf' was created in namespace 'refs/users' pointing to: 9bd8691e25c... Add ChangeLog.meissner and REVISION.
[gcc(refs/users/meissner/heads/work176-dmf)] Add ChangeLog.dmf and update REVISION.
https://gcc.gnu.org/g:2f5f585dae78be0166b9367c752dcd6f6054808f commit 2f5f585dae78be0166b9367c752dcd6f6054808f Author: Michael Meissner Date: Fri Aug 16 20:01:40 2024 -0400 Add ChangeLog.dmf and update REVISION. 2024-08-16 Michael Meissner gcc/ * ChangeLog.dmf: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.dmf | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf new file mode 100644 index 000..c5ecfe8ec49 --- /dev/null +++ b/gcc/ChangeLog.dmf @@ -0,0 +1,6 @@ + Branch work176-dmf, baseline + +2024-08-16 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 9974885ad20..3c346ba1d56 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work176 branch +work176-dmf branch
[gcc] Created branch 'meissner/heads/work176-vpair' in namespace 'refs/users'
The branch 'meissner/heads/work176-vpair' was created in namespace 'refs/users' pointing to: 9bd8691e25c... Add ChangeLog.meissner and REVISION.
[gcc(refs/users/meissner/heads/work176-vpair)] Add ChangeLog.vpair and update REVISION.
https://gcc.gnu.org/g:217eac978ad1f41265f54228db31152de2f94b70 commit 217eac978ad1f41265f54228db31152de2f94b70 Author: Michael Meissner Date: Fri Aug 16 20:02:38 2024 -0400 Add ChangeLog.vpair and update REVISION. 2024-08-16 Michael Meissner gcc/ * ChangeLog.vpair: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.vpair | 6 ++ gcc/REVISION| 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair new file mode 100644 index 000..2157c2b62b0 --- /dev/null +++ b/gcc/ChangeLog.vpair @@ -0,0 +1,6 @@ + Branch work176-vpair, baseline + +2024-08-16 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 9974885ad20..b858d38e1b1 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work176 branch +work176-vpair branch
[gcc] Created branch 'meissner/heads/work176-tar' in namespace 'refs/users'
The branch 'meissner/heads/work176-tar' was created in namespace 'refs/users' pointing to: 9bd8691e25c... Add ChangeLog.meissner and REVISION.
