[PATCH] D48044: [Power9] Update fp128 as a valid homogenous aggregate base type
lei created this revision.
lei added reviewers: hfinkel, kbarton, nemanjai, power-llvm-team.
Update clang to treat fp128 as a valid base type for homogeneous aggregate
passing and returning.
https://reviews.llvm.org/D48044
Files:
include/clang/AST/Type.h
lib/CodeGen/TargetInfo.cpp
test/CodeGen/ppc64le-f128Aggregates.c
Index: test/CodeGen/ppc64le-f128Aggregates.c
===
--- /dev/null
+++ test/CodeGen/ppc64le-f128Aggregates.c
@@ -0,0 +1,124 @@
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -emit-llvm \
+// RUN: -target-cpu pwr9 -target-feature +float128 -o - %s | FileCheck %s
+
+// Test homogeneous fp128 aggregate passing and returning.
+
+struct fp1 { __float128 f[1]; };
+struct fp2 { __float128 f[2]; };
+struct fp3 { __float128 f[3]; };
+struct fp4 { __float128 f[4]; };
+struct fp5 { __float128 f[5]; };
+struct fp6 { __float128 f[6]; };
+struct fp7 { __float128 f[7]; };
+struct fp8 { __float128 f[8]; };
+struct fp9 { __float128 f[9]; };
+
+struct fpab { __float128 a; __float128 b; };
+struct fpabc { __float128 a; __float128 b; __float128 c; };
+
+struct fp2a2b { __float128 a[2]; __float128 b[2]; };
+
+// CHECK: define [1 x fp128] @func_f1(fp128 inreg %x.coerce)
+struct fp1 func_f1(struct fp1 x) { return x; }
+
+// CHECK: define [2 x fp128] @func_f2([2 x fp128] %x.coerce)
+struct fp2 func_f2(struct fp2 x) { return x; }
+
+// CHECK: define [3 x fp128] @func_f3([3 x fp128] %x.coerce)
+struct fp3 func_f3(struct fp3 x) { return x; }
+
+// CHECK: define [4 x fp128] @func_f4([4 x fp128] %x.coerce)
+struct fp4 func_f4(struct fp4 x) { return x; }
+
+// CHECK: define [5 x fp128] @func_f5([5 x fp128] %x.coerce)
+struct fp5 func_f5(struct fp5 x) { return x; }
+
+// CHECK: define [6 x fp128] @func_f6([6 x fp128] %x.coerce)
+struct fp6 func_f6(struct fp6 x) { return x; }
+
+// CHECK: define [7 x fp128] @func_f7([7 x fp128] %x.coerce)
+struct fp7 func_f7(struct fp7 x) { return x; }
+
+// CHECK: define [8 x fp128] @func_f8([8 x fp128] %x.coerce)
+struct fp8 func_f8(struct fp8 x) { return x; }
+
+// CHECK: define void @func_f9(%struct.fp9* noalias sret %agg.result, %struct.fp9* byval align 16 %x)
+struct fp9 func_f9(struct fp9 x) { return x; }
+
+// CHECK: define [2 x fp128] @func_fab([2 x fp128] %x.coerce)
+struct fpab func_fab(struct fpab x) { return x; }
+
+// CHECK: define [3 x fp128] @func_fabc([3 x fp128] %x.coerce)
+struct fpabc func_fabc(struct fpabc x) { return x; }
+
+// CHECK: define [4 x fp128] @func_f2a2b([4 x fp128] %x.coerce)
+struct fp2a2b func_f2a2b(struct fp2a2b x) { return x; }
+
+// CHECK-LABEL: @call_fp1
+// CHECK: %[[TMP:[^ ]+]] = load fp128, fp128* getelementptr inbounds (%struct.fp1, %struct.fp1* @global_f1, i32 0, i32 0, i32 0), align 16
+// CHECK: call [1 x fp128] @func_f1(fp128 inreg %[[TMP]])
+struct fp1 global_f1;
+void call_fp1(void) { global_f1 = func_f1(global_f1); }
+
+// CHECK-LABEL: @call_fp2
+// CHECK: %[[TMP:[^ ]+]] = load [2 x fp128], [2 x fp128]* getelementptr inbounds (%struct.fp2, %struct.fp2* @global_f2, i32 0, i32 0), align 16
+// CHECK: call [2 x fp128] @func_f2([2 x fp128] %[[TMP]])
+struct fp2 global_f2;
+void call_fp2(void) { global_f2 = func_f2(global_f2); }
+
+// CHECK-LABEL: @call_fp3
+// CHECK: %[[TMP:[^ ]+]] = load [3 x fp128], [3 x fp128]* getelementptr inbounds (%struct.fp3, %struct.fp3* @global_f3, i32 0, i32 0), align 16
+// CHECK: call [3 x fp128] @func_f3([3 x fp128] %[[TMP]])
+struct fp3 global_f3;
+void call_fp3(void) { global_f3 = func_f3(global_f3); }
+
+// CHECK-LABEL: @call_fp4
+// CHECK: %[[TMP:[^ ]+]] = load [4 x fp128], [4 x fp128]* getelementptr inbounds (%struct.fp4, %struct.fp4* @global_f4, i32 0, i32 0), align 16
+// CHECK: call [4 x fp128] @func_f4([4 x fp128] %[[TMP]])
+struct fp4 global_f4;
+void call_fp4(void) { global_f4 = func_f4(global_f4); }
+
+// CHECK-LABEL: @call_fp5
+// CHECK: %[[TMP:[^ ]+]] = load [5 x fp128], [5 x fp128]* getelementptr inbounds (%struct.fp5, %struct.fp5* @global_f5, i32 0, i32 0), align 16
+// CHECK: call [5 x fp128] @func_f5([5 x fp128] %[[TMP]])
+struct fp5 global_f5;
+void call_fp5(void) { global_f5 = func_f5(global_f5); }
+
+// CHECK-LABEL: @call_fp6
+// CHECK: %[[TMP:[^ ]+]] = load [6 x fp128], [6 x fp128]* getelementptr inbounds (%struct.fp6, %struct.fp6* @global_f6, i32 0, i32 0), align 16
+// CHECK: call [6 x fp128] @func_f6([6 x fp128] %[[TMP]])
+struct fp6 global_f6;
+void call_fp6(void) { global_f6 = func_f6(global_f6); }
+
+// CHECK-LABEL: @call_fp7
+// CHECK: %[[TMP:[^ ]+]] = load [7 x fp128], [7 x fp128]* getelementptr inbounds (%struct.fp7, %struct.fp7* @global_f7, i32 0, i32 0), align 16
+// CHECK: call [7 x fp128] @func_f7([7 x fp128] %[[TMP]])
+struct fp7 global_f7;
+void call_fp7(void) { global_f7 = func_f7(global_f7); }
+
+// CHECK-LABEL: @call_fp8
+// CHECK: %[[TMP:[^ ]+]] = load [8 x fp128], [8 x fp128]* getelementptr inbounds (%struct.fp8, %struct.fp8* @global_f8, i32 0, i32 0), align 16
+// CHECK: call [8 x fp128]
[PATCH] D48044: [Power9] Update fp128 as a valid homogenous aggregate base type
lei updated this revision to Diff 150821.
https://reviews.llvm.org/D48044
Files:
include/clang/AST/Type.h
lib/CodeGen/TargetInfo.cpp
test/CodeGen/ppc64le-f128Aggregates.c
Index: test/CodeGen/ppc64le-f128Aggregates.c
===
--- /dev/null
+++ test/CodeGen/ppc64le-f128Aggregates.c
@@ -0,0 +1,124 @@
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -emit-llvm \
+// RUN: -target-cpu pwr9 -target-feature +float128 -o - %s | FileCheck %s
+
+// Test homogeneous fp128 aggregate passing and returning.
+
+struct fp1 { __float128 f[1]; };
+struct fp2 { __float128 f[2]; };
+struct fp3 { __float128 f[3]; };
+struct fp4 { __float128 f[4]; };
+struct fp5 { __float128 f[5]; };
+struct fp6 { __float128 f[6]; };
+struct fp7 { __float128 f[7]; };
+struct fp8 { __float128 f[8]; };
+struct fp9 { __float128 f[9]; };
+
+struct fpab { __float128 a; __float128 b; };
+struct fpabc { __float128 a; __float128 b; __float128 c; };
+
+struct fp2a2b { __float128 a[2]; __float128 b[2]; };
+
+// CHECK: define [1 x fp128] @func_f1(fp128 inreg %x.coerce)
+struct fp1 func_f1(struct fp1 x) { return x; }
+
+// CHECK: define [2 x fp128] @func_f2([2 x fp128] %x.coerce)
+struct fp2 func_f2(struct fp2 x) { return x; }
+
+// CHECK: define [3 x fp128] @func_f3([3 x fp128] %x.coerce)
+struct fp3 func_f3(struct fp3 x) { return x; }
+
+// CHECK: define [4 x fp128] @func_f4([4 x fp128] %x.coerce)
+struct fp4 func_f4(struct fp4 x) { return x; }
+
+// CHECK: define [5 x fp128] @func_f5([5 x fp128] %x.coerce)
+struct fp5 func_f5(struct fp5 x) { return x; }
+
+// CHECK: define [6 x fp128] @func_f6([6 x fp128] %x.coerce)
+struct fp6 func_f6(struct fp6 x) { return x; }
+
+// CHECK: define [7 x fp128] @func_f7([7 x fp128] %x.coerce)
+struct fp7 func_f7(struct fp7 x) { return x; }
+
+// CHECK: define [8 x fp128] @func_f8([8 x fp128] %x.coerce)
+struct fp8 func_f8(struct fp8 x) { return x; }
+
+// CHECK: define void @func_f9(%struct.fp9* noalias sret %agg.result, %struct.fp9* byval align 16 %x)
+struct fp9 func_f9(struct fp9 x) { return x; }
+
+// CHECK: define [2 x fp128] @func_fab([2 x fp128] %x.coerce)
+struct fpab func_fab(struct fpab x) { return x; }
+
+// CHECK: define [3 x fp128] @func_fabc([3 x fp128] %x.coerce)
+struct fpabc func_fabc(struct fpabc x) { return x; }
+
+// CHECK: define [4 x fp128] @func_f2a2b([4 x fp128] %x.coerce)
+struct fp2a2b func_f2a2b(struct fp2a2b x) { return x; }
+
+// CHECK-LABEL: @call_fp1
+// CHECK: %[[TMP:[^ ]+]] = load fp128, fp128* getelementptr inbounds (%struct.fp1, %struct.fp1* @global_f1, i32 0, i32 0, i32 0), align 16
+// CHECK: call [1 x fp128] @func_f1(fp128 inreg %[[TMP]])
+struct fp1 global_f1;
+void call_fp1(void) { global_f1 = func_f1(global_f1); }
+
+// CHECK-LABEL: @call_fp2
+// CHECK: %[[TMP:[^ ]+]] = load [2 x fp128], [2 x fp128]* getelementptr inbounds (%struct.fp2, %struct.fp2* @global_f2, i32 0, i32 0), align 16
+// CHECK: call [2 x fp128] @func_f2([2 x fp128] %[[TMP]])
+struct fp2 global_f2;
+void call_fp2(void) { global_f2 = func_f2(global_f2); }
+
+// CHECK-LABEL: @call_fp3
+// CHECK: %[[TMP:[^ ]+]] = load [3 x fp128], [3 x fp128]* getelementptr inbounds (%struct.fp3, %struct.fp3* @global_f3, i32 0, i32 0), align 16
+// CHECK: call [3 x fp128] @func_f3([3 x fp128] %[[TMP]])
+struct fp3 global_f3;
+void call_fp3(void) { global_f3 = func_f3(global_f3); }
+
+// CHECK-LABEL: @call_fp4
+// CHECK: %[[TMP:[^ ]+]] = load [4 x fp128], [4 x fp128]* getelementptr inbounds (%struct.fp4, %struct.fp4* @global_f4, i32 0, i32 0), align 16
+// CHECK: call [4 x fp128] @func_f4([4 x fp128] %[[TMP]])
+struct fp4 global_f4;
+void call_fp4(void) { global_f4 = func_f4(global_f4); }
+
+// CHECK-LABEL: @call_fp5
+// CHECK: %[[TMP:[^ ]+]] = load [5 x fp128], [5 x fp128]* getelementptr inbounds (%struct.fp5, %struct.fp5* @global_f5, i32 0, i32 0), align 16
+// CHECK: call [5 x fp128] @func_f5([5 x fp128] %[[TMP]])
+struct fp5 global_f5;
+void call_fp5(void) { global_f5 = func_f5(global_f5); }
+
+// CHECK-LABEL: @call_fp6
+// CHECK: %[[TMP:[^ ]+]] = load [6 x fp128], [6 x fp128]* getelementptr inbounds (%struct.fp6, %struct.fp6* @global_f6, i32 0, i32 0), align 16
+// CHECK: call [6 x fp128] @func_f6([6 x fp128] %[[TMP]])
+struct fp6 global_f6;
+void call_fp6(void) { global_f6 = func_f6(global_f6); }
+
+// CHECK-LABEL: @call_fp7
+// CHECK: %[[TMP:[^ ]+]] = load [7 x fp128], [7 x fp128]* getelementptr inbounds (%struct.fp7, %struct.fp7* @global_f7, i32 0, i32 0), align 16
+// CHECK: call [7 x fp128] @func_f7([7 x fp128] %[[TMP]])
+struct fp7 global_f7;
+void call_fp7(void) { global_f7 = func_f7(global_f7); }
+
+// CHECK-LABEL: @call_fp8
+// CHECK: %[[TMP:[^ ]+]] = load [8 x fp128], [8 x fp128]* getelementptr inbounds (%struct.fp8, %struct.fp8* @global_f8, i32 0, i32 0), align 16
+// CHECK: call [8 x fp128] @func_f8([8 x fp128] %[[TMP]])
+struct fp8 global_f8;
+void call_fp8(void) { global_f8 = func_f8(global_f8); }
+
+// CHECK-LABEL: @call_fp9
+// CHECK: %
[PATCH] D48044: [Power9] Update fp128 as a valid homogenous aggregate base type
This revision was automatically updated to reflect the committed changes.
Closed by commit rL336308: [Power9] Update fp128 as a valid homogenous
aggregate base type (authored by lei, committed by ).
Herald added a subscriber: llvm-commits.
Changed prior to commit:
https://reviews.llvm.org/D48044?vs=150821&id=154166#toc
Repository:
rL LLVM
https://reviews.llvm.org/D48044
Files:
cfe/trunk/include/clang/AST/Type.h
cfe/trunk/lib/CodeGen/TargetInfo.cpp
cfe/trunk/test/CodeGen/ppc64le-f128Aggregates.c
Index: cfe/trunk/include/clang/AST/Type.h
===
--- cfe/trunk/include/clang/AST/Type.h
+++ cfe/trunk/include/clang/AST/Type.h
@@ -1807,6 +1807,7 @@
bool isFloatingType() const; // C99 6.2.5p11 (real floating + complex)
bool isHalfType() const; // OpenCL 6.1.1.1, NEON (IEEE 754-2008 half)
bool isFloat16Type() const; // C11 extension ISO/IEC TS 18661
+ bool isFloat128Type() const;
bool isRealType() const; // C99 6.2.5p17 (real floating + integer)
bool isArithmeticType() const; // C99 6.2.5p18 (integer + floating)
bool isVoidType() const; // C99 6.2.5p19
@@ -6299,6 +6300,12 @@
return false;
}
+inline bool Type::isFloat128Type() const {
+ if (const auto *BT = dyn_cast(CanonicalType))
+return BT->getKind() == BuiltinType::Float128;
+ return false;
+}
+
inline bool Type::isNullPtrType() const {
if (const auto *BT = getAs())
return BT->getKind() == BuiltinType::NullPtr;
Index: cfe/trunk/test/CodeGen/ppc64le-f128Aggregates.c
===
--- cfe/trunk/test/CodeGen/ppc64le-f128Aggregates.c
+++ cfe/trunk/test/CodeGen/ppc64le-f128Aggregates.c
@@ -0,0 +1,124 @@
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -emit-llvm \
+// RUN: -target-cpu pwr9 -target-feature +float128 -o - %s | FileCheck %s
+
+// Test homogeneous fp128 aggregate passing and returning.
+
+struct fp1 { __float128 f[1]; };
+struct fp2 { __float128 f[2]; };
+struct fp3 { __float128 f[3]; };
+struct fp4 { __float128 f[4]; };
+struct fp5 { __float128 f[5]; };
+struct fp6 { __float128 f[6]; };
+struct fp7 { __float128 f[7]; };
+struct fp8 { __float128 f[8]; };
+struct fp9 { __float128 f[9]; };
+
+struct fpab { __float128 a; __float128 b; };
+struct fpabc { __float128 a; __float128 b; __float128 c; };
+
+struct fp2a2b { __float128 a[2]; __float128 b[2]; };
+
+// CHECK: define [1 x fp128] @func_f1(fp128 inreg %x.coerce)
+struct fp1 func_f1(struct fp1 x) { return x; }
+
+// CHECK: define [2 x fp128] @func_f2([2 x fp128] %x.coerce)
+struct fp2 func_f2(struct fp2 x) { return x; }
+
+// CHECK: define [3 x fp128] @func_f3([3 x fp128] %x.coerce)
+struct fp3 func_f3(struct fp3 x) { return x; }
+
+// CHECK: define [4 x fp128] @func_f4([4 x fp128] %x.coerce)
+struct fp4 func_f4(struct fp4 x) { return x; }
+
+// CHECK: define [5 x fp128] @func_f5([5 x fp128] %x.coerce)
+struct fp5 func_f5(struct fp5 x) { return x; }
+
+// CHECK: define [6 x fp128] @func_f6([6 x fp128] %x.coerce)
+struct fp6 func_f6(struct fp6 x) { return x; }
+
+// CHECK: define [7 x fp128] @func_f7([7 x fp128] %x.coerce)
+struct fp7 func_f7(struct fp7 x) { return x; }
+
+// CHECK: define [8 x fp128] @func_f8([8 x fp128] %x.coerce)
+struct fp8 func_f8(struct fp8 x) { return x; }
+
+// CHECK: define void @func_f9(%struct.fp9* noalias sret %agg.result, %struct.fp9* byval align 16 %x)
+struct fp9 func_f9(struct fp9 x) { return x; }
+
+// CHECK: define [2 x fp128] @func_fab([2 x fp128] %x.coerce)
+struct fpab func_fab(struct fpab x) { return x; }
+
+// CHECK: define [3 x fp128] @func_fabc([3 x fp128] %x.coerce)
+struct fpabc func_fabc(struct fpabc x) { return x; }
+
+// CHECK: define [4 x fp128] @func_f2a2b([4 x fp128] %x.coerce)
+struct fp2a2b func_f2a2b(struct fp2a2b x) { return x; }
+
+// CHECK-LABEL: @call_fp1
+// CHECK: %[[TMP:[^ ]+]] = load fp128, fp128* getelementptr inbounds (%struct.fp1, %struct.fp1* @global_f1, i32 0, i32 0, i32 0), align 16
+// CHECK: call [1 x fp128] @func_f1(fp128 inreg %[[TMP]])
+struct fp1 global_f1;
+void call_fp1(void) { global_f1 = func_f1(global_f1); }
+
+// CHECK-LABEL: @call_fp2
+// CHECK: %[[TMP:[^ ]+]] = load [2 x fp128], [2 x fp128]* getelementptr inbounds (%struct.fp2, %struct.fp2* @global_f2, i32 0, i32 0), align 16
+// CHECK: call [2 x fp128] @func_f2([2 x fp128] %[[TMP]])
+struct fp2 global_f2;
+void call_fp2(void) { global_f2 = func_f2(global_f2); }
+
+// CHECK-LABEL: @call_fp3
+// CHECK: %[[TMP:[^ ]+]] = load [3 x fp128], [3 x fp128]* getelementptr inbounds (%struct.fp3, %struct.fp3* @global_f3, i32 0, i32 0), align 16
+// CHECK: call [3 x fp128] @func_f3([3 x fp128] %[[TMP]])
+struct fp3 global_f3;
+void call_fp3(void) { global_f3 = func_f3(global_f3); }
+
+// CHECK-LABEL: @call_fp4
+// CHECK: %[[TMP:[^ ]+]] = load [4 x fp128], [4 x fp128]* getelementptr inbounds (%struct.fp4, %struct.fp4* @global_f4, i32 0, i32 0), align 16
+// CHECK: call [4 x fp12
[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm
lei added inline comments.
Comment at: clang/lib/Basic/Targets/PPC.cpp:339
if (!(ArchDefs & ArchDefinePwr9) && (ArchDefs & ArchDefinePpcgr) &&
llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) {
NeHuang wrote:
> I think we also need to check for `ArchDefinePwr10` and `ArchDefineFuture`
> based on the comment "// We have __float128 on PPC but not power 9 and
> above."
>
> `!(ArchDefs & ArchDefinePwr9)` -> `!(ArchDefs & (ArchDefinePwr9 |
> ArchDefinePwr10 | ArchDefineFuture))`
I would think this would be redundant since `-mcpu=pwr10` also defines
`ArchDefinePwr9` ...
Comment at: llvm/lib/Target/PowerPC/PPC.td:211
+ "true",
+ "Enable instructions added in ISA 3.1.">;
def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec",
"true",
steven.zhang wrote:
> Nit: no ending dot.
That's needed to indicate the end of the sentence. Similar to line 208.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D80020/new/
https://reviews.llvm.org/D80020
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[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm
lei updated this revision to Diff 266073.
lei marked 7 inline comments as done.
lei added a comment.
address review comments
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D80020/new/
https://reviews.llvm.org/D80020
Files:
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/lib/Driver/ToolChains/Arch/PPC.cpp
clang/test/Misc/target-invalid-cpu-note.c
clang/test/Preprocessor/init-ppc64.c
llvm/lib/Support/Host.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/test/CodeGen/PowerPC/check-cpu.ll
Index: llvm/test/CodeGen/PowerPC/check-cpu.ll
===
--- llvm/test/CodeGen/PowerPC/check-cpu.ll
+++ llvm/test/CodeGen/PowerPC/check-cpu.ll
@@ -2,9 +2,13 @@
; RUN: -mcpu=future < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=future < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=power10 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 < %s | FileCheck %s
-; Test mcpu=future that should be recognized on PowerPC.
+; Test -mcpu=[pwr10|future] is recognized on PowerPC.
; CHECK-NOT: is not a recognized processor for this target
; CHECK: .text
Index: llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
===
--- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -654,7 +654,8 @@
unsigned Directive = ST->getCPUDirective();
// Assume that Future CPU has the same cache line size as the others.
if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
- Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+ Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+ Directive == PPC::DIR_PWR_FUTURE)
return 128;
// On other processors return a default of 64 bytes.
@@ -688,7 +689,8 @@
// FIXME: the same for P9 as previous gen until POWER9 scheduling is ready
// Assume that future is the same as the others.
if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
- Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+ Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+ Directive == PPC::DIR_PWR_FUTURE)
return 12;
// For most things, modern systems have two execution units (and
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -34,32 +34,33 @@
namespace PPC {
// -m directive values.
- enum {
-DIR_NONE,
-DIR_32,
-DIR_440,
-DIR_601,
-DIR_602,
-DIR_603,
-DIR_7400,
-DIR_750,
-DIR_970,
-DIR_A2,
-DIR_E500,
-DIR_E500mc,
-DIR_E5500,
-DIR_PWR3,
-DIR_PWR4,
-DIR_PWR5,
-DIR_PWR5X,
-DIR_PWR6,
-DIR_PWR6X,
-DIR_PWR7,
-DIR_PWR8,
-DIR_PWR9,
-DIR_PWR_FUTURE,
-DIR_64
- };
+enum {
+ DIR_NONE,
+ DIR_32,
+ DIR_440,
+ DIR_601,
+ DIR_602,
+ DIR_603,
+ DIR_7400,
+ DIR_750,
+ DIR_970,
+ DIR_A2,
+ DIR_E500,
+ DIR_E500mc,
+ DIR_E5500,
+ DIR_PWR3,
+ DIR_PWR4,
+ DIR_PWR5,
+ DIR_PWR5X,
+ DIR_PWR6,
+ DIR_PWR6X,
+ DIR_PWR7,
+ DIR_PWR8,
+ DIR_PWR9,
+ DIR_PWR10,
+ DIR_PWR_FUTURE,
+ DIR_64
+};
}
class GlobalValue;
@@ -138,6 +139,7 @@
bool HasAddiLoadFusion;
bool HasAddisLoadFusion;
bool IsISA3_0;
+ bool IsISA3_1;
bool UseLongCalls;
bool SecurePlt;
bool VectorsUseTwoUnits;
@@ -308,6 +310,7 @@
bool hasHTM() const { return HasHTM; }
bool hasFloat128() const { return HasFloat128; }
bool isISA3_0() const { return IsISA3_0; }
+ bool isISA3_1() const { return IsISA3_1; }
bool useLongCalls() const { return UseLongCalls; }
bool hasFusion() const { return HasFusion; }
bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1305,6 +1305,7 @@
case PPC::DIR_PWR7:
case PPC::DIR_PWR8:
case PPC::DIR_PWR9:
+ case PPC::DIR_PWR10:
case PPC::DIR_PWR_FUTURE:
setPrefLoopAlignment(Align(16));
setPrefFunctionAlignment(Align(16));
@@ -14912,6 +14913,7 @@
case PPC::DIR_PWR7:
case PPC::DIR_PWR8:
case PPC::DIR_PWR9:
+ case PPC::DIR_PWR10:
case PPC::DIR_PWR_FUTURE: {
if (!ML)
break;
@@ -16101,6 +16103,7 @@
// vector7 2 2
return true;
case PPC::DIR_PWR9:
+case PPC::
[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm
lei updated this revision to Diff 266283.
lei added a comment.
update as per reviewers comments
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D80020/new/
https://reviews.llvm.org/D80020
Files:
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/lib/Driver/ToolChains/Arch/PPC.cpp
clang/test/Misc/target-invalid-cpu-note.c
clang/test/Preprocessor/init-ppc64.c
llvm/lib/Support/Host.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/test/CodeGen/PowerPC/check-cpu.ll
Index: llvm/test/CodeGen/PowerPC/check-cpu.ll
===
--- llvm/test/CodeGen/PowerPC/check-cpu.ll
+++ llvm/test/CodeGen/PowerPC/check-cpu.ll
@@ -2,9 +2,13 @@
; RUN: -mcpu=future < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=future < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=power10 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 < %s | FileCheck %s
-; Test mcpu=future that should be recognized on PowerPC.
+; Test -mcpu=[pwr10|future] is recognized on PowerPC.
; CHECK-NOT: is not a recognized processor for this target
; CHECK: .text
Index: llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
===
--- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -651,11 +651,12 @@
if (CacheLineSize.getNumOccurrences() > 0)
return CacheLineSize;
- // On P7, P8 or P9 we have a cache line size of 128.
+ // Starting with P7 we have a cache line size of 128.
unsigned Directive = ST->getCPUDirective();
// Assume that Future CPU has the same cache line size as the others.
if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
- Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+ Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+ Directive == PPC::DIR_PWR_FUTURE)
return 128;
// On other processors return a default of 64 bytes.
@@ -687,9 +688,11 @@
// For P7 and P8, floating-point instructions have a 6-cycle latency and
// there are two execution units, so unroll by 12x for latency hiding.
// FIXME: the same for P9 as previous gen until POWER9 scheduling is ready
+ // FIXME: the same for P10 as previous gen until POWER10 scheduling is ready
// Assume that future is the same as the others.
if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
- Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+ Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+ Directive == PPC::DIR_PWR_FUTURE)
return 12;
// For most things, modern systems have two execution units (and
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -34,32 +34,33 @@
namespace PPC {
// -m directive values.
- enum {
-DIR_NONE,
-DIR_32,
-DIR_440,
-DIR_601,
-DIR_602,
-DIR_603,
-DIR_7400,
-DIR_750,
-DIR_970,
-DIR_A2,
-DIR_E500,
-DIR_E500mc,
-DIR_E5500,
-DIR_PWR3,
-DIR_PWR4,
-DIR_PWR5,
-DIR_PWR5X,
-DIR_PWR6,
-DIR_PWR6X,
-DIR_PWR7,
-DIR_PWR8,
-DIR_PWR9,
-DIR_PWR_FUTURE,
-DIR_64
- };
+enum {
+ DIR_NONE,
+ DIR_32,
+ DIR_440,
+ DIR_601,
+ DIR_602,
+ DIR_603,
+ DIR_7400,
+ DIR_750,
+ DIR_970,
+ DIR_A2,
+ DIR_E500,
+ DIR_E500mc,
+ DIR_E5500,
+ DIR_PWR3,
+ DIR_PWR4,
+ DIR_PWR5,
+ DIR_PWR5X,
+ DIR_PWR6,
+ DIR_PWR6X,
+ DIR_PWR7,
+ DIR_PWR8,
+ DIR_PWR9,
+ DIR_PWR10,
+ DIR_PWR_FUTURE,
+ DIR_64
+};
}
class GlobalValue;
@@ -138,6 +139,7 @@
bool HasAddiLoadFusion;
bool HasAddisLoadFusion;
bool IsISA3_0;
+ bool IsISA3_1;
bool UseLongCalls;
bool SecurePlt;
bool VectorsUseTwoUnits;
@@ -308,6 +310,7 @@
bool hasHTM() const { return HasHTM; }
bool hasFloat128() const { return HasFloat128; }
bool isISA3_0() const { return IsISA3_0; }
+ bool isISA3_1() const { return IsISA3_1; }
bool useLongCalls() const { return UseLongCalls; }
bool hasFusion() const { return HasFusion; }
bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -115,6 +115,7 @@
HasAddiLoadFusion = false;
HasAddisLoadFusion = false;
IsISA3_0 = fals
[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm
This revision was automatically updated to reflect the committed changes.
Closed by commit rG7eb666b1556b: [PowerPC] Add support for -mcpu=pwr10 in both
clang and llvm (authored by lei).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D80020/new/
https://reviews.llvm.org/D80020
Files:
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/lib/Driver/ToolChains/Arch/PPC.cpp
clang/test/Misc/target-invalid-cpu-note.c
clang/test/Preprocessor/init-ppc64.c
llvm/lib/Support/Host.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/test/CodeGen/PowerPC/check-cpu.ll
Index: llvm/test/CodeGen/PowerPC/check-cpu.ll
===
--- llvm/test/CodeGen/PowerPC/check-cpu.ll
+++ llvm/test/CodeGen/PowerPC/check-cpu.ll
@@ -2,9 +2,13 @@
; RUN: -mcpu=future < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=future < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=power10 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 < %s | FileCheck %s
-; Test mcpu=future that should be recognized on PowerPC.
+; Test -mcpu=[pwr10|future] is recognized on PowerPC.
; CHECK-NOT: is not a recognized processor for this target
; CHECK: .text
Index: llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
===
--- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -651,11 +651,12 @@
if (CacheLineSize.getNumOccurrences() > 0)
return CacheLineSize;
- // On P7, P8 or P9 we have a cache line size of 128.
+ // Starting with P7 we have a cache line size of 128.
unsigned Directive = ST->getCPUDirective();
// Assume that Future CPU has the same cache line size as the others.
if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
- Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+ Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+ Directive == PPC::DIR_PWR_FUTURE)
return 128;
// On other processors return a default of 64 bytes.
@@ -687,9 +688,11 @@
// For P7 and P8, floating-point instructions have a 6-cycle latency and
// there are two execution units, so unroll by 12x for latency hiding.
// FIXME: the same for P9 as previous gen until POWER9 scheduling is ready
+ // FIXME: the same for P10 as previous gen until POWER10 scheduling is ready
// Assume that future is the same as the others.
if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
- Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+ Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+ Directive == PPC::DIR_PWR_FUTURE)
return 12;
// For most things, modern systems have two execution units (and
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -34,32 +34,33 @@
namespace PPC {
// -m directive values.
- enum {
-DIR_NONE,
-DIR_32,
-DIR_440,
-DIR_601,
-DIR_602,
-DIR_603,
-DIR_7400,
-DIR_750,
-DIR_970,
-DIR_A2,
-DIR_E500,
-DIR_E500mc,
-DIR_E5500,
-DIR_PWR3,
-DIR_PWR4,
-DIR_PWR5,
-DIR_PWR5X,
-DIR_PWR6,
-DIR_PWR6X,
-DIR_PWR7,
-DIR_PWR8,
-DIR_PWR9,
-DIR_PWR_FUTURE,
-DIR_64
- };
+enum {
+ DIR_NONE,
+ DIR_32,
+ DIR_440,
+ DIR_601,
+ DIR_602,
+ DIR_603,
+ DIR_7400,
+ DIR_750,
+ DIR_970,
+ DIR_A2,
+ DIR_E500,
+ DIR_E500mc,
+ DIR_E5500,
+ DIR_PWR3,
+ DIR_PWR4,
+ DIR_PWR5,
+ DIR_PWR5X,
+ DIR_PWR6,
+ DIR_PWR6X,
+ DIR_PWR7,
+ DIR_PWR8,
+ DIR_PWR9,
+ DIR_PWR10,
+ DIR_PWR_FUTURE,
+ DIR_64
+};
}
class GlobalValue;
@@ -138,6 +139,7 @@
bool HasAddiLoadFusion;
bool HasAddisLoadFusion;
bool IsISA3_0;
+ bool IsISA3_1;
bool UseLongCalls;
bool SecurePlt;
bool VectorsUseTwoUnits;
@@ -308,6 +310,7 @@
bool hasHTM() const { return HasHTM; }
bool hasFloat128() const { return HasFloat128; }
bool isISA3_0() const { return IsISA3_0; }
+ bool isISA3_1() const { return IsISA3_1; }
bool useLongCalls() const { return UseLongCalls; }
bool hasFusion() const { return HasFusion; }
bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -115,6
[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm
lei updated this revision to Diff 266321.
lei added a comment.
change how we generate p10 feature list.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D80020/new/
https://reviews.llvm.org/D80020
Files:
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/lib/Driver/ToolChains/Arch/PPC.cpp
clang/test/Misc/target-invalid-cpu-note.c
clang/test/Preprocessor/init-ppc64.c
llvm/lib/Support/Host.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/test/CodeGen/PowerPC/check-cpu.ll
Index: llvm/test/CodeGen/PowerPC/check-cpu.ll
===
--- llvm/test/CodeGen/PowerPC/check-cpu.ll
+++ llvm/test/CodeGen/PowerPC/check-cpu.ll
@@ -2,9 +2,13 @@
; RUN: -mcpu=future < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=future < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=power10 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 < %s | FileCheck %s
-; Test mcpu=future that should be recognized on PowerPC.
+; Test -mcpu=[pwr10|future] is recognized on PowerPC.
; CHECK-NOT: is not a recognized processor for this target
; CHECK: .text
Index: llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
===
--- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -651,11 +651,12 @@
if (CacheLineSize.getNumOccurrences() > 0)
return CacheLineSize;
- // On P7, P8 or P9 we have a cache line size of 128.
+ // Starting with P7 we have a cache line size of 128.
unsigned Directive = ST->getCPUDirective();
// Assume that Future CPU has the same cache line size as the others.
if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
- Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+ Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+ Directive == PPC::DIR_PWR_FUTURE)
return 128;
// On other processors return a default of 64 bytes.
@@ -687,9 +688,11 @@
// For P7 and P8, floating-point instructions have a 6-cycle latency and
// there are two execution units, so unroll by 12x for latency hiding.
// FIXME: the same for P9 as previous gen until POWER9 scheduling is ready
+ // FIXME: the same for P10 as previous gen until POWER10 scheduling is ready
// Assume that future is the same as the others.
if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
- Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+ Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+ Directive == PPC::DIR_PWR_FUTURE)
return 12;
// For most things, modern systems have two execution units (and
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -34,32 +34,33 @@
namespace PPC {
// -m directive values.
- enum {
-DIR_NONE,
-DIR_32,
-DIR_440,
-DIR_601,
-DIR_602,
-DIR_603,
-DIR_7400,
-DIR_750,
-DIR_970,
-DIR_A2,
-DIR_E500,
-DIR_E500mc,
-DIR_E5500,
-DIR_PWR3,
-DIR_PWR4,
-DIR_PWR5,
-DIR_PWR5X,
-DIR_PWR6,
-DIR_PWR6X,
-DIR_PWR7,
-DIR_PWR8,
-DIR_PWR9,
-DIR_PWR_FUTURE,
-DIR_64
- };
+enum {
+ DIR_NONE,
+ DIR_32,
+ DIR_440,
+ DIR_601,
+ DIR_602,
+ DIR_603,
+ DIR_7400,
+ DIR_750,
+ DIR_970,
+ DIR_A2,
+ DIR_E500,
+ DIR_E500mc,
+ DIR_E5500,
+ DIR_PWR3,
+ DIR_PWR4,
+ DIR_PWR5,
+ DIR_PWR5X,
+ DIR_PWR6,
+ DIR_PWR6X,
+ DIR_PWR7,
+ DIR_PWR8,
+ DIR_PWR9,
+ DIR_PWR10,
+ DIR_PWR_FUTURE,
+ DIR_64
+};
}
class GlobalValue;
@@ -138,6 +139,7 @@
bool HasAddiLoadFusion;
bool HasAddisLoadFusion;
bool IsISA3_0;
+ bool IsISA3_1;
bool UseLongCalls;
bool SecurePlt;
bool VectorsUseTwoUnits;
@@ -308,6 +310,7 @@
bool hasHTM() const { return HasHTM; }
bool hasFloat128() const { return HasFloat128; }
bool isISA3_0() const { return IsISA3_0; }
+ bool isISA3_1() const { return IsISA3_1; }
bool useLongCalls() const { return UseLongCalls; }
bool hasFusion() const { return HasFusion; }
bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -115,6 +115,7 @@
HasAddiLoadFusion = false;
HasAddisLoadFusion = false;
IsISA3_
[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm
lei updated this revision to Diff 266533.
lei added a comment.
rebased
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D80020/new/
https://reviews.llvm.org/D80020
Files:
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -176,6 +176,7 @@
StringRef CPU,
const std::vector &FeaturesVec) const override;
+ void addP10SpecificFeatures(llvm::StringMap &Features) const;
void addFutureSpecificFeatures(llvm::StringMap &Features) const;
bool handleTargetFeatures(std::vector &Features,
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -325,6 +325,13 @@
.Case("e500", true)
.Default(false);
+ // Power10 includes all the same features as Power9 plus any features
specific
+ // to the Power10 core.
+ if (CPU == "pwr10" || CPU == "power10") {
+initFeatureMap(Features, Diags, "pwr9", FeaturesVec);
+addP10SpecificFeatures(Features);
+ }
+
// Future CPU should include all of the features of Power 10 as well as any
// additional features (yet to be determined) specific to it.
if (CPU == "future") {
@@ -345,6 +352,13 @@
return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
}
+// Add any Power10 specific features.
+void PPCTargetInfo::addP10SpecificFeatures(
+llvm::StringMap &Features) const {
+ Features["htm"] = false; // HTM was removed for P10.
+ return;
+}
+
// Add features specific to the "Future" CPU.
void PPCTargetInfo::addFutureSpecificFeatures(
llvm::StringMap &Features) const {
Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -176,6 +176,7 @@
StringRef CPU,
const std::vector &FeaturesVec) const override;
+ void addP10SpecificFeatures(llvm::StringMap &Features) const;
void addFutureSpecificFeatures(llvm::StringMap &Features) const;
bool handleTargetFeatures(std::vector &Features,
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -325,6 +325,13 @@
.Case("e500", true)
.Default(false);
+ // Power10 includes all the same features as Power9 plus any features specific
+ // to the Power10 core.
+ if (CPU == "pwr10" || CPU == "power10") {
+initFeatureMap(Features, Diags, "pwr9", FeaturesVec);
+addP10SpecificFeatures(Features);
+ }
+
// Future CPU should include all of the features of Power 10 as well as any
// additional features (yet to be determined) specific to it.
if (CPU == "future") {
@@ -345,6 +352,13 @@
return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
}
+// Add any Power10 specific features.
+void PPCTargetInfo::addP10SpecificFeatures(
+llvm::StringMap &Features) const {
+ Features["htm"] = false; // HTM was removed for P10.
+ return;
+}
+
// Add features specific to the "Future" CPU.
void PPCTargetInfo::addFutureSpecificFeatures(
llvm::StringMap &Features) const {
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
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[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm
lei updated this revision to Diff 266548.
lei added a comment.
fix up rebase issue after revert
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D80020/new/
https://reviews.llvm.org/D80020
Files:
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/lib/Driver/ToolChains/Arch/PPC.cpp
clang/test/Misc/target-invalid-cpu-note.c
clang/test/Preprocessor/init-ppc64.c
llvm/lib/Support/Host.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/test/CodeGen/PowerPC/check-cpu.ll
Index: llvm/test/CodeGen/PowerPC/check-cpu.ll
===
--- llvm/test/CodeGen/PowerPC/check-cpu.ll
+++ llvm/test/CodeGen/PowerPC/check-cpu.ll
@@ -2,9 +2,13 @@
; RUN: -mcpu=future < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=future < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=power10 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 < %s | FileCheck %s
-; Test mcpu=future that should be recognized on PowerPC.
+; Test -mcpu=[pwr10|future] is recognized on PowerPC.
; CHECK-NOT: is not a recognized processor for this target
; CHECK: .text
Index: llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
===
--- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -651,11 +651,12 @@
if (CacheLineSize.getNumOccurrences() > 0)
return CacheLineSize;
- // On P7, P8 or P9 we have a cache line size of 128.
+ // Starting with P7 we have a cache line size of 128.
unsigned Directive = ST->getCPUDirective();
// Assume that Future CPU has the same cache line size as the others.
if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
- Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+ Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+ Directive == PPC::DIR_PWR_FUTURE)
return 128;
// On other processors return a default of 64 bytes.
@@ -687,9 +688,11 @@
// For P7 and P8, floating-point instructions have a 6-cycle latency and
// there are two execution units, so unroll by 12x for latency hiding.
// FIXME: the same for P9 as previous gen until POWER9 scheduling is ready
+ // FIXME: the same for P10 as previous gen until POWER10 scheduling is ready
// Assume that future is the same as the others.
if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
- Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+ Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+ Directive == PPC::DIR_PWR_FUTURE)
return 12;
// For most things, modern systems have two execution units (and
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -34,32 +34,33 @@
namespace PPC {
// -m directive values.
- enum {
-DIR_NONE,
-DIR_32,
-DIR_440,
-DIR_601,
-DIR_602,
-DIR_603,
-DIR_7400,
-DIR_750,
-DIR_970,
-DIR_A2,
-DIR_E500,
-DIR_E500mc,
-DIR_E5500,
-DIR_PWR3,
-DIR_PWR4,
-DIR_PWR5,
-DIR_PWR5X,
-DIR_PWR6,
-DIR_PWR6X,
-DIR_PWR7,
-DIR_PWR8,
-DIR_PWR9,
-DIR_PWR_FUTURE,
-DIR_64
- };
+enum {
+ DIR_NONE,
+ DIR_32,
+ DIR_440,
+ DIR_601,
+ DIR_602,
+ DIR_603,
+ DIR_7400,
+ DIR_750,
+ DIR_970,
+ DIR_A2,
+ DIR_E500,
+ DIR_E500mc,
+ DIR_E5500,
+ DIR_PWR3,
+ DIR_PWR4,
+ DIR_PWR5,
+ DIR_PWR5X,
+ DIR_PWR6,
+ DIR_PWR6X,
+ DIR_PWR7,
+ DIR_PWR8,
+ DIR_PWR9,
+ DIR_PWR10,
+ DIR_PWR_FUTURE,
+ DIR_64
+};
}
class GlobalValue;
@@ -138,6 +139,7 @@
bool HasAddiLoadFusion;
bool HasAddisLoadFusion;
bool IsISA3_0;
+ bool IsISA3_1;
bool UseLongCalls;
bool SecurePlt;
bool VectorsUseTwoUnits;
@@ -308,6 +310,7 @@
bool hasHTM() const { return HasHTM; }
bool hasFloat128() const { return HasFloat128; }
bool isISA3_0() const { return IsISA3_0; }
+ bool isISA3_1() const { return IsISA3_1; }
bool useLongCalls() const { return UseLongCalls; }
bool hasFusion() const { return HasFusion; }
bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -115,6 +115,7 @@
HasAddiLoadFusion = false;
HasAddisLoadFusion = false;
IsISA3_0 = fals
[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm
This revision was automatically updated to reflect the committed changes.
Closed by commit rG2368bf52cd77: [PowerPC] Add support for -mcpu=pwr10 in both
clang and llvm (authored by lei).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D80020/new/
https://reviews.llvm.org/D80020
Files:
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/lib/Driver/ToolChains/Arch/PPC.cpp
clang/test/Misc/target-invalid-cpu-note.c
clang/test/Preprocessor/init-ppc64.c
llvm/lib/Support/Host.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/test/CodeGen/PowerPC/check-cpu.ll
Index: llvm/test/CodeGen/PowerPC/check-cpu.ll
===
--- llvm/test/CodeGen/PowerPC/check-cpu.ll
+++ llvm/test/CodeGen/PowerPC/check-cpu.ll
@@ -2,9 +2,13 @@
; RUN: -mcpu=future < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=future < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=power10 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 < %s | FileCheck %s
-; Test mcpu=future that should be recognized on PowerPC.
+; Test -mcpu=[pwr10|future] is recognized on PowerPC.
; CHECK-NOT: is not a recognized processor for this target
; CHECK: .text
Index: llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
===
--- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -651,11 +651,12 @@
if (CacheLineSize.getNumOccurrences() > 0)
return CacheLineSize;
- // On P7, P8 or P9 we have a cache line size of 128.
+ // Starting with P7 we have a cache line size of 128.
unsigned Directive = ST->getCPUDirective();
// Assume that Future CPU has the same cache line size as the others.
if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
- Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+ Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+ Directive == PPC::DIR_PWR_FUTURE)
return 128;
// On other processors return a default of 64 bytes.
@@ -687,9 +688,11 @@
// For P7 and P8, floating-point instructions have a 6-cycle latency and
// there are two execution units, so unroll by 12x for latency hiding.
// FIXME: the same for P9 as previous gen until POWER9 scheduling is ready
+ // FIXME: the same for P10 as previous gen until POWER10 scheduling is ready
// Assume that future is the same as the others.
if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
- Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+ Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+ Directive == PPC::DIR_PWR_FUTURE)
return 12;
// For most things, modern systems have two execution units (and
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -34,32 +34,33 @@
namespace PPC {
// -m directive values.
- enum {
-DIR_NONE,
-DIR_32,
-DIR_440,
-DIR_601,
-DIR_602,
-DIR_603,
-DIR_7400,
-DIR_750,
-DIR_970,
-DIR_A2,
-DIR_E500,
-DIR_E500mc,
-DIR_E5500,
-DIR_PWR3,
-DIR_PWR4,
-DIR_PWR5,
-DIR_PWR5X,
-DIR_PWR6,
-DIR_PWR6X,
-DIR_PWR7,
-DIR_PWR8,
-DIR_PWR9,
-DIR_PWR_FUTURE,
-DIR_64
- };
+enum {
+ DIR_NONE,
+ DIR_32,
+ DIR_440,
+ DIR_601,
+ DIR_602,
+ DIR_603,
+ DIR_7400,
+ DIR_750,
+ DIR_970,
+ DIR_A2,
+ DIR_E500,
+ DIR_E500mc,
+ DIR_E5500,
+ DIR_PWR3,
+ DIR_PWR4,
+ DIR_PWR5,
+ DIR_PWR5X,
+ DIR_PWR6,
+ DIR_PWR6X,
+ DIR_PWR7,
+ DIR_PWR8,
+ DIR_PWR9,
+ DIR_PWR10,
+ DIR_PWR_FUTURE,
+ DIR_64
+};
}
class GlobalValue;
@@ -138,6 +139,7 @@
bool HasAddiLoadFusion;
bool HasAddisLoadFusion;
bool IsISA3_0;
+ bool IsISA3_1;
bool UseLongCalls;
bool SecurePlt;
bool VectorsUseTwoUnits;
@@ -308,6 +310,7 @@
bool hasHTM() const { return HasHTM; }
bool hasFloat128() const { return HasFloat128; }
bool isISA3_0() const { return IsISA3_0; }
+ bool isISA3_1() const { return IsISA3_1; }
bool useLongCalls() const { return UseLongCalls; }
bool hasFusion() const { return HasFusion; }
bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -115,6
[PATCH] D80757: [PowerPC] Add clang option -m[no-]pcrel
lei created this revision.
lei added reviewers: stefanp, nemanjai, hfinkel, power-llvm-team.
Herald added subscribers: shchenz, wuzish.
Herald added a project: clang.
Add user-facing front end option to turn off pc-relative memops.
This will be compatible with gcc.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D80757
Files:
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/test/Driver/ppc-pcrel.cpp
Index: clang/test/Driver/ppc-pcrel.cpp
===
--- /dev/null
+++ clang/test/Driver/ppc-pcrel.cpp
@@ -0,0 +1,12 @@
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10 -mpcrel
-o %t.o 2>&1 | FileCheck -check-prefix=CHECK-PCREL %s
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10
-mno-pcrel -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOPCREL %s
+// CHECK-NOPCREL: "-target-feature" "-pcrel"
+// CHECK-PCREL: "-target-feature" "+pcrel"
+
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -emit-llvm -S
%s -o - | grep "attributes.*+pcrelative-memops"
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -mpcrel
-emit-llvm -S %s -o - | grep "attributes.*+pcrelative-memops"
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -mno-pcrel
-emit-llvm -S %s -o - | grep "attributes.*\-pcrelative-memops"
+
+int main(int argc, char *argv[]) {
+ return 0;
+}
Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -69,6 +69,7 @@
bool HasExtDiv = false;
bool HasP9Vector = false;
bool HasSPE = false;
+ bool HasPCRelativeMemops = false;
protected:
std::string ABI;
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -54,6 +54,8 @@
HasFloat128 = true;
} else if (Feature == "+power9-vector") {
HasP9Vector = true;
+} else if (Feature == "+pcrelative-memops") {
+ HasPCRelativeMemops = true;
} else if (Feature == "+spe") {
HasSPE = true;
LongDoubleWidth = LongDoubleAlign = 64;
@@ -346,6 +348,7 @@
void PPCTargetInfo::addP10SpecificFeatures(
llvm::StringMap &Features) const {
Features["htm"] = false; // HTM was removed for P10.
+ Features["pcrelative-memops"] = true;
return;
}
@@ -369,6 +372,7 @@
.Case("extdiv", HasExtDiv)
.Case("float128", HasFloat128)
.Case("power9-vector", HasP9Vector)
+ .Case("pcrelative-memops", HasPCRelativeMemops)
.Case("spe", HasSPE)
.Default(false);
}
@@ -389,7 +393,10 @@
Features["vsx"] = Features["altivec"] = true;
if (Name == "power9-vector")
Features["power8-vector"] = true;
-Features[Name] = true;
+if (Name == "pcrel")
+ Features["pcrelative-memops"] = true;
+else
+ Features[Name] = true;
} else {
// If we're disabling altivec or vsx go ahead and disable all of the vsx
// features.
@@ -398,7 +405,10 @@
Features["float128"] = Features["power9-vector"] = false;
if (Name == "power8-vector")
Features["power9-vector"] = false;
-Features[Name] = false;
+if (Name == "pcrel")
+ Features["pcrelative-memops"] = false;
+else
+ Features[Name] = false;
}
}
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -2470,6 +2470,8 @@
def fno_altivec : Flag<["-"], "fno-altivec">, Group,
Flags<[DriverOption]>;
def maltivec : Flag<["-"], "maltivec">, Group;
def mno_altivec : Flag<["-"], "mno-altivec">, Group;
+def mpcrel: Flag<["-"], "mpcrel">, Group;
+def mno_pcrel: Flag<["-"], "mno-pcrel">, Group;
def mspe : Flag<["-"], "mspe">, Group;
def mno_spe : Flag<["-"], "mno-spe">, Group;
def mvsx : Flag<["-"], "mvsx">, Group;
Index: clang/test/Driver/ppc-pcrel.cpp
===
--- /dev/null
+++ clang/test/Driver/ppc-pcrel.cpp
@@ -0,0 +1,12 @@
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10 -mpcrel -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-PCREL %s
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10 -mno-pcrel -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOPCREL %s
+// CHECK-NOPCREL: "-target-feature" "-pcrel"
+// CHECK-PCREL: "-target-feature" "+pcrel"
+
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -emit-llvm -S %s -o - | grep "attributes.*+pcrelative-memops"
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -mpcrel -emit-llvm -S %s -o - | grep "attributes.*+pcrelative-memops"
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -mno-pcrel -emit-llvm
[PATCH] D80757: [PowerPC] Add clang option -m[no-]pcrel
lei marked an inline comment as done. lei added inline comments. Comment at: clang/test/Driver/ppc-pcrel.cpp:1 +// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10 -mpcrel -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-PCREL %s +// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10 -mno-pcrel -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOPCREL %s saghir wrote: > nit: would the first two checks be better off in > `clang/test/Driver/ppc-features.cpp`? I think it's better to keep all tests for pcrel within this specific pcrel test file. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80757/new/ https://reviews.llvm.org/D80757 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D80758: [PowerPC] Add -m[no-]power10-vector clang and llvm option
lei added inline comments. Comment at: clang/lib/Basic/Targets/PPC.cpp:414 +if (Name == "power9-vector") + Features["power10-vector"] = false; Features[Name] = false; I think it would be good to change this into a switch-stmt as there are enough conditional changed based on `Name` and probably more to come. Comment at: llvm/lib/Target/PowerPC/PPC.td:219 FeatureP9Altivec]>; +def FeatureP10Altivec : SubtargetFeature<"power10-altivec", "HasP10Altivec", + "true", what's the relationship between this and p10 vector support? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80758/new/ https://reviews.llvm.org/D80758 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D80757: [PowerPC] Add clang option -m[no-]pcrel
This revision was automatically updated to reflect the committed changes.
Closed by commit rG7cfded350a7e: [PowerPC] Add clang option -m[no-]pcrel
(authored by lei).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D80757/new/
https://reviews.llvm.org/D80757
Files:
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/test/Driver/ppc-pcrel.cpp
Index: clang/test/Driver/ppc-pcrel.cpp
===
--- /dev/null
+++ clang/test/Driver/ppc-pcrel.cpp
@@ -0,0 +1,12 @@
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10 -mpcrel
-o %t.o 2>&1 | FileCheck -check-prefix=CHECK-PCREL %s
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10
-mno-pcrel -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOPCREL %s
+// CHECK-NOPCREL: "-target-feature" "-pcrel"
+// CHECK-PCREL: "-target-feature" "+pcrel"
+
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -emit-llvm -S
%s -o - | grep "attributes.*+pcrelative-memops"
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -mpcrel
-emit-llvm -S %s -o - | grep "attributes.*+pcrelative-memops"
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -mno-pcrel
-emit-llvm -S %s -o - | grep "attributes.*\-pcrelative-memops"
+
+int main(int argc, char *argv[]) {
+ return 0;
+}
Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -69,6 +69,7 @@
bool HasExtDiv = false;
bool HasP9Vector = false;
bool HasSPE = false;
+ bool HasPCRelativeMemops = false;
protected:
std::string ABI;
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -54,6 +54,8 @@
HasFloat128 = true;
} else if (Feature == "+power9-vector") {
HasP9Vector = true;
+} else if (Feature == "+pcrelative-memops") {
+ HasPCRelativeMemops = true;
} else if (Feature == "+spe") {
HasSPE = true;
LongDoubleWidth = LongDoubleAlign = 64;
@@ -346,6 +348,7 @@
void PPCTargetInfo::addP10SpecificFeatures(
llvm::StringMap &Features) const {
Features["htm"] = false; // HTM was removed for P10.
+ Features["pcrelative-memops"] = true;
return;
}
@@ -369,6 +372,7 @@
.Case("extdiv", HasExtDiv)
.Case("float128", HasFloat128)
.Case("power9-vector", HasP9Vector)
+ .Case("pcrelative-memops", HasPCRelativeMemops)
.Case("spe", HasSPE)
.Default(false);
}
@@ -389,7 +393,10 @@
Features["vsx"] = Features["altivec"] = true;
if (Name == "power9-vector")
Features["power8-vector"] = true;
-Features[Name] = true;
+if (Name == "pcrel")
+ Features["pcrelative-memops"] = true;
+else
+ Features[Name] = true;
} else {
// If we're disabling altivec or vsx go ahead and disable all of the vsx
// features.
@@ -398,7 +405,10 @@
Features["float128"] = Features["power9-vector"] = false;
if (Name == "power8-vector")
Features["power9-vector"] = false;
-Features[Name] = false;
+if (Name == "pcrel")
+ Features["pcrelative-memops"] = false;
+else
+ Features[Name] = false;
}
}
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -2470,6 +2470,8 @@
def fno_altivec : Flag<["-"], "fno-altivec">, Group,
Flags<[DriverOption]>;
def maltivec : Flag<["-"], "maltivec">, Group;
def mno_altivec : Flag<["-"], "mno-altivec">, Group;
+def mpcrel: Flag<["-"], "mpcrel">, Group;
+def mno_pcrel: Flag<["-"], "mno-pcrel">, Group;
def mspe : Flag<["-"], "mspe">, Group;
def mno_spe : Flag<["-"], "mno-spe">, Group;
def mvsx : Flag<["-"], "mvsx">, Group;
Index: clang/test/Driver/ppc-pcrel.cpp
===
--- /dev/null
+++ clang/test/Driver/ppc-pcrel.cpp
@@ -0,0 +1,12 @@
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10 -mpcrel -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-PCREL %s
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10 -mno-pcrel -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOPCREL %s
+// CHECK-NOPCREL: "-target-feature" "-pcrel"
+// CHECK-PCREL: "-target-feature" "+pcrel"
+
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -emit-llvm -S %s -o - | grep "attributes.*+pcrelative-memops"
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -mpcrel -emit-llvm -S %s -o - | grep "attributes.*+pcrelative-memops"
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -mno-pcrel -emit-llvm -S %s -o - | grep "attributes.*\-pc
[PATCH] D80758: [PowerPC] Add -m[no-]power10-vector clang and llvm option
lei accepted this revision. lei added a comment. LGTM. Minor nit can be addressed during commit. Comment at: clang/lib/Basic/Targets/PPC.cpp:413 + Features["power9-vector"] = Features["power10-vector"] = false; +if (Name == "power9-vector") + Features["power10-vector"] = false; nit: this should be an `else if`, same as what you did on line 401. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80758/new/ https://reviews.llvm.org/D80758 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D82467: [PowerPC][Power10] Implement Truncate and Store VSX Vector Builtins
lei accepted this revision. lei added a comment. This revision is now accepted and ready to land. LGTM, Please add tests for BE in llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll prior to committing. Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll:2 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ stefanp wrote: > NeHuang wrote: > > Do we also need to run for big endian? > I don't think it would hurt to add a BE run for this as well. the only thing > to watch out for is the fact that this is not actually a new file. This test > file already exists on master so I assume that this will be merged in (and > not added as a new file). I believe this is a new file 🙂 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82467/new/ https://reviews.llvm.org/D82467 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D84197: [PowerPC][Power10] 128-bit Vector String Isolate instruction definitions and MC Tests
lei added a comment. Why are you removing MC tests for here? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D84197/new/ https://reviews.llvm.org/D84197 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend
lei added inline comments.
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:14166
+
+ SDValue LoadOps[] = {LD->getChain(), LD->getBasePtr(),
DAG.getIntPtrConstant(MemoryType.getScalarSizeInBits(), dl)};
+
nit: indentation.
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:14169
+ return DAG.getMemIntrinsicNode(PPCISD::LXVRZX, dl,
+ DAG.getVTList(MVT::v1i128, MVT::Other),
+ LoadOps, MemoryType, LD->getMemOperand());
nit: indentation
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[PATCH] D84382: [PowerPC][Power10] Cleanup p10vector clang test
lei accepted this revision. lei added a comment. This revision is now accepted and ready to land. LGTM thx! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D84382/new/ https://reviews.llvm.org/D84382 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D82502: [PowerPC] Implement Load VSX Vector and Sign Extend and Zero Extend
lei added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:14156 + + // This transformation is only valid if the we are loading either a byte, + // halfword, word, or doubleword. Conanap wrote: > NeHuang wrote: > > nit: if we are loading either a byte > I'm not too sure what you mean, would you be able to elaborate? > The comment is: > > > > This transformation is only valid if the we are loading either a byte, > > halfword, word, or doubleword. > > Thanks! > > Extra `the` in your sentence: `This transformation is only valid if the we are loading` -> `This transformation is only valid if we are loading` CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ https://reviews.llvm.org/D82502 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins
lei added a comment. Please address the auto generated clang-format issues for the added code in this patch. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83338/new/ https://reviews.llvm.org/D83338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D83722: [PowerPC] Add options to control paired vector memops support
This revision was automatically updated to reflect the committed changes.
Closed by commit rG7aaa85627b59: [PowerPC] Add options to control paired vector
memops support (authored by bsaleil, committed by lei).
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Files:
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/test/Driver/ppc-dependent-options.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCScheduleP9.td
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
llvm/test/CodeGen/PowerPC/future-check-features.ll
Index: llvm/test/CodeGen/PowerPC/future-check-features.ll
===
--- llvm/test/CodeGen/PowerPC/future-check-features.ll
+++ llvm/test/CodeGen/PowerPC/future-check-features.ll
@@ -1,9 +1,9 @@
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs -verify-machineinstrs \
-; RUN: -mtriple=powerpc64le-unknown-unknown -ppc-asm-full-reg-names \
-; RUN: %s -o - 2>&1 | FileCheck %s
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs -verify-machineinstrs \
-; RUN: -mtriple=powerpc64-unknown-unknown -ppc-asm-full-reg-names \
-; RUN: %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops \
+; RUN: -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops \
+; RUN: -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
define dso_local signext i32 @f() {
entry:
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -145,6 +145,7 @@
bool VectorsUseTwoUnits;
bool UsePPCPreRASchedStrategy;
bool UsePPCPostRASchedStrategy;
+ bool PairedVectorMemops;
bool PredictableSelectIsExpensive;
POPCNTDKind HasPOPCNTD;
@@ -259,6 +260,7 @@
bool hasP10Vector() const { return HasP10Vector; }
bool hasPrefixInstrs() const { return HasPrefixInstrs; }
bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
+ bool pairedVectorMemops() const { return PairedVectorMemops; }
bool hasMFOCRF() const { return HasMFOCRF; }
bool hasISEL() const { return HasISEL; }
bool hasBPERMD() const { return HasBPERMD; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -116,6 +116,7 @@
VectorsUseTwoUnits = false;
UsePPCPreRASchedStrategy = false;
UsePPCPostRASchedStrategy = false;
+ PairedVectorMemops = false;
PredictableSelectIsExpensive = false;
HasPOPCNTD = POPCNTD_Unavailable;
Index: llvm/lib/Target/PowerPC/PPCScheduleP9.td
===
--- llvm/lib/Target/PowerPC/PPCScheduleP9.td
+++ llvm/lib/Target/PowerPC/PPCScheduleP9.td
@@ -41,8 +41,10 @@
let CompleteModel = 1;
// Do not support SPE (Signal Processing Engine), prefixed instructions on
- // Power 9, PC relative mem ops, or instructions introduced in ISA 3.1.
- let UnsupportedFeatures = [HasSPE, PrefixInstrs, PCRelativeMemops, IsISA3_1];
+ // Power 9, paired vector mem ops, PC relative mem ops, or instructions
+ // introduced in ISA 3.1.
+ let UnsupportedFeatures = [HasSPE, PrefixInstrs, PairedVectorMemops,
+ PCRelativeMemops, IsISA3_1];
}
let SchedModel = P9Model in {
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -454,6 +454,7 @@
def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
+def PairedVectorMemops : Predicate<"PPCSubTarget->pairedVectorMemops()">;
let Predicates = [PrefixInstrs] in {
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -234,6 +234,10 @@
SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true",
"Enable PC relative Memory Ops",
[FeatureISA3_0]>;
+def FeaturePairedVectorMemops:
+ SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true",
+ "32Byte load and store instructions",
+ [FeatureISA3_0]>;
def FeaturePredictableSelectIsExpensive :
Subt
[PATCH] D80970: [PowerPC][Power10] Implement centrifuge, vector gather every nth bit, vector evaluate Builtins in LLVM/Clang
lei accepted this revision as: lei. lei added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80970/new/ https://reviews.llvm.org/D80970 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D81774: [PowerPC][Power10] Implement VSX PCV Generate Operations in LLVM/Clang
lei accepted this revision as: lei. lei added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D81774/new/ https://reviews.llvm.org/D81774 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D80935: [PowerPC][Power10] Implement Parallel Bits Deposit/Extract Builtins in LLVM/Clang
lei accepted this revision as: lei. lei added a comment. This revision is now accepted and ready to land. LGTM, just 1 minor comment/question. Comment at: llvm/lib/Target/PowerPC/PPCScheduleP9.td:47 + let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs, PCRelativeMemops, + IsISA3_1]; Are `PrefixInstrs` and `PCRelativeMemops` not part of `IsISA3_1`? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80935/new/ https://reviews.llvm.org/D80935 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D81707: [PowerPC][Power10] Implement Vector Clear Left/Rightmost Bytes Builtins in LLVM/Clang
lei accepted this revision as: lei. lei added a comment. This revision is now accepted and ready to land. LGTM Minor nit to be addressed during commit. Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:522 + [(set v16i8:$vD, + (int_ppc_altivec_vclrlb v16i8:$vA, i32:$rB))]>; + def VCLRRB : VXForm_1<461, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB), nit: indentation. Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:526 + [(set v16i8:$vD, + (int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>; } nit: indentation Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D81707/new/ https://reviews.llvm.org/D81707 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10
lei requested changes to this revision.
lei added inline comments.
This revision now requires changes to proceed.
Comment at: clang/lib/Sema/DeclSpec.cpp:1155
+ // TODO: Update comment with correct Programming Interface Manual
+ // version once it is available. __int128 has also been added
+ // to vector bool for Power10.
Not sure what you mean here.
Comment at: clang/lib/Sema/DeclSpec.cpp:1168
+ (!S.Context.getTargetInfo().hasFeature("vsx")) &&
+ (!S.Context.getTargetInfo().hasFeature("power10-vector")))
+S.Diag(TSTLoc, diag::err_invalid_vector_bool_int128_decl_spec);
I think you should only check for "power10-vector" since this requires pwr10?
Comment at: clang/test/Parser/altivec-bool-128.c:2
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-feature
+altivec -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-feature
+altivec -fsyntax-only -verify %s
+
test for `-mcpu=pwr10 -target-feature -power10-vector` and `-mcpu=pwr10
-target-feature -vsx`
same for cxx-altivec-bool-128.cpp
Comment at: clang/test/Parser/p10-vector-bool-128.c:2
+// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-feature
+altivec -target-feature +vsx -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-feature
+altivec -target-feature +vsx -fsyntax-only -verify %s
+// expected-no-diagnostics
add run line for feature `cpu=pwr10 +power10-vector`
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[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10
lei added inline comments. Comment at: clang/test/Parser/altivec-bool-128.c:2 +// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-feature +altivec -fsyntax-only -verify %s +// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-feature +altivec -fsyntax-only -verify %s + saghir wrote: > lei wrote: > > test for `-mcpu=pwr10 -target-feature -power10-vector` and `-mcpu=pwr10 > > -target-feature -vsx` > > same for cxx-altivec-bool-128.cpp > This test basically checks that `VSX` needs to be enabled to have `vector > bool __int128` type work. Yes. I am asking you to add a test to check that `power10-vector` is also needed to be enabled for this type to work. eg. this type should not be enabled for `-mcpu=pwr10 -target-feature +vsx -target-feature -power10-vector` Comment at: clang/test/Parser/p10-vector-bool-128.c:2 +// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-feature +altivec -target-feature +vsx -fsyntax-only -verify %s +// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-feature +altivec -target-feature +vsx -fsyntax-only -verify %s +// expected-no-diagnostics saghir wrote: > lei wrote: > > add run line for feature `cpu=pwr10 +power10-vector` > Added `pwr10`. > `vector bool __int128` type should work with `pwr10` and `vsx` enabled, > `power10-vector` is not needed explicitly. `cpu=pwr10 -vsx +power10-vector` Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D81816/new/ https://reviews.llvm.org/D81816 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10
lei added inline comments. Comment at: clang/lib/Sema/DeclSpec.cpp:1155 + // TODO: Update comment with correct Programming Interface Manual + // version once it is available. __int128 has also been added + // to vector bool for Power10. saghir wrote: > lei wrote: > > Not sure what you mean here. > Earlier comment had the Programming Interface Manual version number (PIM > 2.1); asserting only char/int were valid with vector bool. > This patch adds __int128, so the comment needs to be updated with the latest > version of the document once it is available. Maybe need to add a TODO in all the sections of code, that you update, where it mentions PIM 2.1 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D81816/new/ https://reviews.llvm.org/D81816 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10
lei added inline comments. Comment at: clang/lib/Sema/DeclSpec.cpp:1170 // Only 'short' and 'long long' are valid with vector bool. (PIM 2.1) if ((TypeSpecWidth != TSW_unspecified) && (TypeSpecWidth != TSW_short) && Do we not need to add a check for int128 to this check as well? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D81816/new/ https://reviews.llvm.org/D81816 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10
lei added inline comments. Comment at: clang/test/Parser/p10-vector-bool-128.c:2 +// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-feature +altivec -target-feature +vsx -fsyntax-only -verify %s +// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-feature +altivec -target-feature +vsx -fsyntax-only -verify %s +// expected-no-diagnostics saghir wrote: > lei wrote: > > saghir wrote: > > > lei wrote: > > > > add run line for feature `cpu=pwr10 +power10-vector` > > > Added `pwr10`. > > > `vector bool __int128` type should work with `pwr10` and `vsx` enabled, > > > `power10-vector` is not needed explicitly. > > `cpu=pwr10 -vsx +power10-vector` > I have now added both `-target-cpu pwr10` and `-target-feature > +power10-vector` as you mentioned in the first comment. > However, I am not quite sure what you are looking to test here by adding > `-vsx` because that would disable `vsx`, which in turn would disable > `power10-vector` and we would not be able to test the legitimate use here. `-vsx` diable it, but the following `+power10-vector` should enable it. So: ``` // RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-cpu pwr10 \ // RUN:-target-feature -vsx -target-feature +power10-vector ``` Comment at: clang/test/Parser/p10-vector-bool-128.c:2 +// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-cpu pwr10 \ +// RUN:-target-feature +altivec -target-feature +vsx \ +// RUN:-target-feature +power10-vector -fsyntax-only -verify %s I don't think you need `-target-feature +altivec ` here. Comment at: clang/test/Parser/p10-vector-bool-128.c:5 +// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-cpu pwr10 \ +// RUN:-target-feature +altivec -target-feature +vsx \ +// RUN:-target-feature +power10-vector -fsyntax-only -verify %s this line shouldn't be needed. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D81816/new/ https://reviews.llvm.org/D81816 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D82467: [PowerPC][Power10] Implement Truncate and Store VSX Vector Builtins
lei added inline comments.
Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:108
+ signed char *__c) {
+ // CHECK-BE: store i8 %{{.+}}, i8* %{{.+}}, align 1
+ // CHECK-LE: store i8 %{{.+}}, i8* %{{.+}}, align 1
amyk wrote:
> lei wrote:
> > I don't see a run line above that uses `CHECK-BE|CHECK-LE`. Since all
> > these look the same, did you mean to use the default `CHECK`?
> You're right - unfortunately in the previous tests that use
> `CHECK-BE`/`CHECK-LE` that were committed, I did not realize that I forgot to
> upstream the appropriate RUN lines... If it is okay, I can add them into this
> patch when I update it.
Not sure what you mean by appropriate RUN lines. From the checks you are
adding seems there is no diff between BE and LE so both can use the default
`CHECK`.
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[PATCH] D82440: [Power10] Implement Vector Shift Double Bit Immediate Builtins in LLVM/Clang
This revision was automatically updated to reflect the committed changes.
Closed by commit rG88874f074644: [PowerPC]Implement Vector Shift Double Bit
Immediate Builtins (authored by biplmish, committed by lei).
Herald added a project: clang.
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Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Headers/altivec.h
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
@@ -0,0 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr10 \
+; RUN: -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr10 \
+; RUN: -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
+
+define <16 x i8> @testVSLDBI(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: testVSLDBI:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vsldbi v2, v2, v3, 1
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call <16 x i8> @llvm.ppc.altivec.vsldbi(<16 x i8> %a, <16 x i8> %b, i32 1)
+ ret <16 x i8> %0
+}
+declare <16 x i8> @llvm.ppc.altivec.vsldbi(<16 x i8>, <16 x i8>, i32 immarg)
+
+define <16 x i8> @testVSRDBI(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: testVSRDBI:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vsrdbi v2, v2, v3, 1
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call <16 x i8> @llvm.ppc.altivec.vsrdbi(<16 x i8> %a, <16 x i8> %b, i32 1)
+ ret <16 x i8> %0
+}
+declare <16 x i8> @llvm.ppc.altivec.vsrdbi(<16 x i8>, <16 x i8>, i32 immarg)
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -738,11 +738,19 @@
def VSLDBI : VNForm_VTAB5_SD3<22, 0, (outs vrrc:$VRT),
(ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH),
"vsldbi $VRT, $VRA, $VRB, $SH",
-IIC_VecGeneral, []>;
+IIC_VecGeneral,
+[(set v16i8:$VRT,
+ (int_ppc_altivec_vsldbi v16i8:$VRA,
+ v16i8:$VRB,
+ i32:$SH))]>;
def VSRDBI : VNForm_VTAB5_SD3<22, 1, (outs vrrc:$VRT),
(ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH),
"vsrdbi $VRT, $VRA, $VRB, $SH",
-IIC_VecGeneral, []>;
+IIC_VecGeneral,
+[(set v16i8:$VRT,
+ (int_ppc_altivec_vsrdbi v16i8:$VRA,
+ v16i8:$VRB,
+ i32:$SH))]>;
def VPDEPD : VXForm_1<1485, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vpdepd $vD, $vA, $vB", IIC_VecGeneral,
[(set v2i64:$vD,
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -454,6 +454,16 @@
def int_ppc_altivec_vclrrb : GCCBuiltin<"__builtin_altivec_vclrrb">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty],
[IntrNoMem]>;
+
+ // P10 Vector Shift Double Bit Immediate.
+ def int_ppc_altivec_vsldbi : GCCBuiltin<"__builtin_altivec_vsldbi">,
+ Intrinsic<[llvm_v16i8_ty],
+[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty],
+[IntrNoMem, ImmArg>]>;
+ def int_ppc_altivec_vsrdbi : GCCBuiltin<"__builtin_altivec_vsrdbi">,
+ Intrinsic<[llvm_v16i8_ty],
+[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty],
+[IntrNoMem, ImmArg>]>;
}
// Vector average.
Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -5,10 +5,13 @@
#include
-vector signed char vsca;
+vector signed char vsca, vscb;
vector unsigned char vuca, vucb, vucc;
+vector signed short vssa, vs
[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend
lei added inline comments.
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.h:487
+/// Allows utilization of the Load VSX Vector Rightmost Instructions.
+LXVRZX
+
missing `,`?
Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:220
+
+def SDT_PPCLXVRZX : SDTypeProfile<1, 2, [
+ SDTCisVT<0, v1i128>, SDTCisPtrTy<1>, SDTCisPtrTy<2>
We should put all such def at the top of this file under:
```
// PowerPC specific type constraints.
```
Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:224
+
+def PPClxvrzx : SDNode<"PPCISD::LXVRZX", SDT_PPCLXVRZX,
+ [SDNPHasChain, SDNPMayLoad]>;
Put these under the `type constraints` section and doc with:
```
// PowerPC specific DAG Nodes.
```
Comment at: llvm/test/CodeGen/PowerPC/p10-vsx-builtins.ll:3
+; These test cases tests that zero extending loads utilize the Load VSX Vector
Rightmost
+
+; (lxvr[b|h|w|d]x) instructions in Power10.
remve extra line. Makes the comment harder to read.
Comment at: llvm/test/CodeGen/PowerPC/p10-vsx-builtins.ll:10
+; Function Attrs: norecurse nounwind readonly
+define dso_local <1 x i128> @vec_xl_zext(i64 %__offset, i8* nocapture readonly
%__pointer) local_unnamed_addr #0 {
+; CHECK-LABEL: vec_xl_zext:
You don't need the `local_unnamed_addr #0`
Repository:
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[PATCH] D82869: [Power10] Implement Vector Permute Extended Builtins in LLVM/Clang
This revision was automatically updated to reflect the committed changes.
Closed by commit rG286073484f7d: [PowerPC]Implement Vector Permute Extended
Builtin (authored by biplmish, committed by lei).
Herald added a project: clang.
Herald added a subscriber: cfe-commits.
Changed prior to commit:
https://reviews.llvm.org/D82869?vs=274993&id=275208#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82869/new/
https://reviews.llvm.org/D82869
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Headers/altivec.h
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
@@ -26,3 +26,14 @@
ret <16 x i8> %0
}
declare <16 x i8> @llvm.ppc.altivec.vsrdbi(<16 x i8>, <16 x i8>, i32 immarg)
+
+define <16 x i8> @testXXPERMX(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: testXXPERMX:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:xxpermx v2, v2, v3, v4, 1
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call <16 x i8> @llvm.ppc.vsx.xxpermx(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, i32 1)
+ ret <16 x i8> %0
+}
+declare <16 x i8> @llvm.ppc.vsx.xxpermx(<16 x i8>, <16 x i8>, <16 x i8>, i32 immarg)
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -845,3 +845,11 @@
(COPY_TO_REGCLASS (XXSPLTIDP (getFPAs32BitInt fpimm:$A)),
VSFRC)>;
}
+
+let Predicates = [PrefixInstrs] in {
+ def : Pat<(v16i8 (int_ppc_vsx_xxpermx v16i8:$A, v16i8:$B, v16i8:$C, timm:$D)),
+(COPY_TO_REGCLASS (XXPERMX (COPY_TO_REGCLASS $A, VSRC),
+ (COPY_TO_REGCLASS $B, VSRC),
+ (COPY_TO_REGCLASS $C, VSRC), $D), VSRC)>;
+}
+
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1017,6 +1017,13 @@
def int_ppc_vsx_xxgenpcvdm :
PowerPC_VSX_Intrinsic<"xxgenpcvdm", [llvm_v2i64_ty],
[llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
+
+// P10 VSX Vector permute extended.
+def int_ppc_vsx_xxpermx :
+ GCCBuiltin<"__builtin_vsx_xxpermx">,
+ Intrinsic<[llvm_v16i8_ty],
+[llvm_v16i8_ty,llvm_v16i8_ty,llvm_v16i8_ty,llvm_i32_ty],
+[IntrNoMem, ImmArg>]>;
}
//===--===//
Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -14,6 +14,8 @@
vector signed long long vslla, vsllb;
vector unsigned long long vulla, vullb, vullc;
vector unsigned __int128 vui128a, vui128b, vui128c;
+vector float vfa, vfb;
+vector double vda, vdb;
unsigned int uia;
vector unsigned long long test_vpdepd(void) {
@@ -257,3 +259,71 @@
// CHECK-NEXT: ret <2 x i64>
return vec_srdb(vulla, vullb, 7);
}
+
+vector signed char test_vec_permx_sc(void) {
+ // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32
+ // CHECK-NEXT: ret <16 x i8>
+ return vec_permx(vsca, vscb, vucc, 0);
+}
+
+vector unsigned char test_vec_permx_uc(void) {
+ // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32
+ // CHECK-NEXT: ret <16 x i8>
+ return vec_permx(vuca, vucb, vucc, 1);
+}
+
+vector signed short test_vec_permx_ss(void) {
+ // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32
+ // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <8 x i16>
+ // CHECK-NEXT: ret <8 x i16>
+ return vec_permx(vssa, vssb, vucc, 2);
+}
+
+vector unsigned short test_vec_permx_us(void) {
+ // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32
+ // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <8 x i16>
+ // CHECK-NEXT: ret <8 x i16>
+ return vec_permx(vusa, vusb, vucc, 3);
+}
+
+vector signed int test_vec_permx_si(void) {
+ // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32
+ // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <4 x i32>
+ // CHECK-NEXT: ret <4 x i32>
+ return vec_permx(vsia, vsib, vucc, 4);
+}
+
+vector unsigned int test_vec_permx_ui(void) {
+ // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}},
[PATCH] D82774: [Power10] Implement Vector Blend Builtins in LLVM/Clang
This revision was automatically updated to reflect the committed changes.
Closed by commit rGca464639a1c9: [PowerPC] Implement Vector Blend Builtins in
LLVM/Clang (authored by biplmish, committed by lei).
Herald added a project: clang.
Herald added a subscriber: cfe-commits.
Changed prior to commit:
https://reviews.llvm.org/D82774?vs=275215&id=275247#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82774/new/
https://reviews.llvm.org/D82774
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
@@ -37,3 +37,47 @@
ret <16 x i8> %0
}
declare <16 x i8> @llvm.ppc.vsx.xxpermx(<16 x i8>, <16 x i8>, <16 x i8>, i32 immarg)
+
+define <16 x i8> @testXXBLENDVB(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; CHECK-LABEL: testXXBLENDVB:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:xxblendvb v2, v2, v3, v4
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call <16 x i8> @llvm.ppc.vsx.xxblendvb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c)
+ ret <16 x i8> %0
+}
+declare <16 x i8> @llvm.ppc.vsx.xxblendvb(<16 x i8>, <16 x i8>, <16 x i8>)
+
+define <8 x i16> @testXXBLENDVH(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
+; CHECK-LABEL: testXXBLENDVH:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:xxblendvh v2, v2, v3, v4
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call <8 x i16> @llvm.ppc.vsx.xxblendvh(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c)
+ ret <8 x i16> %0
+}
+declare <8 x i16> @llvm.ppc.vsx.xxblendvh(<8 x i16>, <8 x i16>, <8 x i16>)
+
+define <4 x i32> @testXXBLENDVW(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
+; CHECK-LABEL: testXXBLENDVW:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:xxblendvw v2, v2, v3, v4
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call <4 x i32> @llvm.ppc.vsx.xxblendvw(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c)
+ ret <4 x i32> %0
+}
+declare <4 x i32> @llvm.ppc.vsx.xxblendvw(<4 x i32>, <4 x i32>, <4 x i32>)
+
+define <2 x i64> @testXXBLENDVD(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
+; CHECK-LABEL: testXXBLENDVD:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:xxblendvd v2, v2, v3, v4
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call <2 x i64> @llvm.ppc.vsx.xxblendvd(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c)
+ ret <2 x i64> %0
+}
+declare <2 x i64> @llvm.ppc.vsx.xxblendvd(<2 x i64>, <2 x i64>, <2 x i64>)
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -891,5 +891,19 @@
(COPY_TO_REGCLASS (XXPERMX (COPY_TO_REGCLASS $A, VSRC),
(COPY_TO_REGCLASS $B, VSRC),
(COPY_TO_REGCLASS $C, VSRC), $D), VSRC)>;
+ def : Pat<(v16i8 (int_ppc_vsx_xxblendvb v16i8:$A, v16i8:$B, v16i8:$C)),
+(COPY_TO_REGCLASS
+ (XXBLENDVB (COPY_TO_REGCLASS $A, VSRC),
+ (COPY_TO_REGCLASS $B, VSRC),
+ (COPY_TO_REGCLASS $C, VSRC)), VSRC)>;
+ def : Pat<(v8i16 (int_ppc_vsx_xxblendvh v8i16:$A, v8i16:$B, v8i16:$C)),
+(COPY_TO_REGCLASS
+ (XXBLENDVH (COPY_TO_REGCLASS $A, VSRC),
+ (COPY_TO_REGCLASS $B, VSRC),
+ (COPY_TO_REGCLASS $C, VSRC)), VSRC)>;
+ def : Pat<(int_ppc_vsx_xxblendvw v4i32:$A, v4i32:$B, v4i32:$C),
+(XXBLENDVW $A, $B, $C)>;
+ def : Pat<(int_ppc_vsx_xxblendvd v2i64:$A, v2i64:$B, v2i64:$C),
+(XXBLENDVD $A, $B, $C)>;
}
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1024,6 +1024,19 @@
Intrinsic<[llvm_v16i8_ty],
[llvm_v16i8_ty,llvm_v16i8_ty,llvm_v16i8_ty,llvm_i32_ty],
[IntrNoMem, ImmArg>]>;
+// P10 VSX Vector Blend Variable.
+def int_ppc_vsx_xxblendvb: GCCBuiltin<"__builtin_vsx_xxblendvb">,
+ Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
+ [IntrNoMem]>;
+def int_ppc_vsx_xxblendvh: GCCBuiltin<"__builtin_vsx_xxblendvh">,
+ Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty,llvm_v8i16_ty],
+ [IntrNoMem]>;
+def int_ppc_vsx_xxblendvw: GCCBuiltin<"__builtin_vsx_xxblendvw">,
+ Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+ [IntrNoMem]>;
+de
[PATCH] D82365: [Power10] Implement Vector Insert Builtins in LLVM/Clang
This revision was automatically updated to reflect the committed changes.
Closed by commit rG0939e04e4176: [PowerPC] Implement Vector Insert Builtins in
LLVM/Clang (authored by biplmish, committed by lei).
Herald added a project: clang.
Herald added a subscriber: cfe-commits.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82365/new/
https://reviews.llvm.org/D82365
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
@@ -81,3 +81,153 @@
ret <2 x i64> %0
}
declare <2 x i64> @llvm.ppc.vsx.xxblendvd(<2 x i64>, <2 x i64>, <2 x i64>)
+
+define <16 x i8> @testVINSBLX(<16 x i8> %a, i64 %b, i64 %c) {
+; CHECK-LABEL: testVINSBLX:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vinsblx v2, r5, r6
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call <16 x i8> @llvm.ppc.altivec.vinsblx(<16 x i8> %a, i64 %b, i64 %c)
+ ret <16 x i8> %0
+}
+declare <16 x i8> @llvm.ppc.altivec.vinsblx(<16 x i8>, i64, i64)
+
+define <16 x i8> @testVINSBRX(<16 x i8> %a, i64 %b, i64 %c) {
+; CHECK-LABEL: testVINSBRX:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vinsbrx v2, r5, r6
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call <16 x i8> @llvm.ppc.altivec.vinsbrx(<16 x i8> %a, i64 %b, i64 %c)
+ ret <16 x i8> %0
+}
+declare <16 x i8> @llvm.ppc.altivec.vinsbrx(<16 x i8>, i64, i64)
+
+define <8 x i16> @testVINSHLX(<8 x i16> %a, i64 %b, i64 %c) {
+; CHECK-LABEL: testVINSHLX:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vinshlx v2, r5, r6
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call <8 x i16> @llvm.ppc.altivec.vinshlx(<8 x i16> %a, i64 %b, i64 %c)
+ ret <8 x i16> %0
+}
+declare <8 x i16> @llvm.ppc.altivec.vinshlx(<8 x i16>, i64, i64)
+
+define <8 x i16> @testVINSHRX(<8 x i16> %a, i64 %b, i64 %c) {
+; CHECK-LABEL: testVINSHRX:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vinshrx v2, r5, r6
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call <8 x i16> @llvm.ppc.altivec.vinshrx(<8 x i16> %a, i64 %b, i64 %c)
+ ret <8 x i16> %0
+}
+declare <8 x i16> @llvm.ppc.altivec.vinshrx(<8 x i16>, i64, i64)
+
+define <4 x i32> @testVINSWLX(<4 x i32> %a, i64 %b, i64 %c) {
+; CHECK-LABEL: testVINSWLX:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vinswlx v2, r5, r6
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call <4 x i32> @llvm.ppc.altivec.vinswlx(<4 x i32> %a, i64 %b, i64 %c)
+ ret <4 x i32> %0
+}
+declare <4 x i32> @llvm.ppc.altivec.vinswlx(<4 x i32>, i64, i64)
+
+define <4 x i32> @testVINSWRX(<4 x i32> %a, i64 %b, i64 %c) {
+; CHECK-LABEL: testVINSWRX:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vinswrx v2, r5, r6
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call <4 x i32> @llvm.ppc.altivec.vinswrx(<4 x i32> %a, i64 %b, i64 %c)
+ ret <4 x i32> %0
+}
+declare <4 x i32> @llvm.ppc.altivec.vinswrx(<4 x i32>, i64, i64)
+
+define <2 x i64> @testVINSDLX(<2 x i64> %a, i64 %b, i64 %c) {
+; CHECK-LABEL: testVINSDLX:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vinsdlx v2, r5, r6
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call <2 x i64> @llvm.ppc.altivec.vinsdlx(<2 x i64> %a, i64 %b, i64 %c)
+ ret <2 x i64> %0
+}
+declare <2 x i64> @llvm.ppc.altivec.vinsdlx(<2 x i64>, i64, i64)
+
+define <2 x i64> @testVINSDRX(<2 x i64> %a, i64 %b, i64 %c) {
+; CHECK-LABEL: testVINSDRX:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vinsdrx v2, r5, r6
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call <2 x i64> @llvm.ppc.altivec.vinsdrx(<2 x i64> %a, i64 %b, i64 %c)
+ ret <2 x i64> %0
+}
+declare <2 x i64> @llvm.ppc.altivec.vinsdrx(<2 x i64>, i64, i64)
+
+define <16 x i8> @testVINSBVLX(<16 x i8> %a, i64 %b, <16 x i8> %c) {
+; CHECK-LABEL: testVINSBVLX:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vinsbvlx v2, r5, v3
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call <16 x i8> @llvm.ppc.altivec.vinsbvlx(<16 x i8> %a, i64 %b, <16 x i8> %c)
+ ret <16 x i8> %0
+}
+declare <16 x i8> @llvm.ppc.altivec.vinsbvlx(<16 x i8>, i64, <16 x i8>)
+
+define <16 x i8> @testVINSBVRX(<16 x i8> %a, i64 %b, <16 x i8> %c) {
+; CHECK-LABEL: testVINSBVRX:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vinsbvrx v2, r5, v3
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call <16 x i8> @llvm.ppc.altivec.vinsbvrx(<16 x i8> %a, i64 %b, <16 x i8> %c)
+ ret <16 x i8> %0
+}
+declare <16 x i8> @llvm.ppc.altivec.vinsbvrx(<16 x i8>, i64, <16 x i8>)
+
+define <8 x i16> @testVINSHVLX(<8 x i16> %a, i64 %b, <8 x i16> %c) {
+; CHECK-LABEL: testVINSHVLX:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vinshvlx v2, r5, v3
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call <8
[PATCH] D82365: [Power10] Implement Vector Insert Builtins in LLVM/Clang
lei added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:12 +// RUN: -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \ +// RUN: -o - | FileCheck %s -check-prefix=CHECK-LE + I just noticed this. There is no need to add this RUN line since it's the same as the one on line 2. Please post a patch to remove this and update tests to use the default `CHECK`. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82365/new/ https://reviews.llvm.org/D82365 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D82365: [Power10] Implement Vector Insert Builtins in LLVM/Clang
lei added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:12 +// RUN: -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \ +// RUN: -o - | FileCheck %s -check-prefix=CHECK-LE + biplmish wrote: > lei wrote: > > I just noticed this. There is no need to add this RUN line since it's the > > same as the one on line 2. Please post a patch to remove this and update > > tests to use the default `CHECK`. > Sure. However there are also tests in Line 125,133 etc which would need > modification. > > Can we also do "RUN: -o - | FileCheck %s -check-prefixes=CHECK,CHECK-LE" in > the test1 and remove the test3 so that the tests work in the current format. Please make all the necessary modification all affected testcases to use `CHECK` instead of `CHECK-LE`. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82365/new/ https://reviews.llvm.org/D82365 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D82520: [Power10] Implement Vector Splat Immediate Builtins in LLVM/Clang
This revision was automatically updated to reflect the committed changes.
Closed by commit rG0c6b6e28e70c: [PowerPC] Implement Vector Splat Immediate
Builtins in Clang (authored by biplmish, committed by lei).
Herald added a project: clang.
Herald added a subscriber: cfe-commits.
Changed prior to commit:
https://reviews.llvm.org/D82520?vs=275790&id=275881#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82520/new/
https://reviews.llvm.org/D82520
Files:
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/test/CodeGen/PowerPC/p10-splatImm.ll
Index: llvm/test/CodeGen/PowerPC/p10-splatImm.ll
===
--- llvm/test/CodeGen/PowerPC/p10-splatImm.ll
+++ llvm/test/CodeGen/PowerPC/p10-splatImm.ll
@@ -286,3 +286,21 @@
entry:
ret double 0.00e+00
}
+
+define dso_local <4 x i32> @vec_splati() local_unnamed_addr {
+; CHECK-LABEL: vec_splati:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:xxspltiw vs34, -17
+; CHECK-NEXT:blr
+entry:
+ ret <4 x i32>
+}
+
+define dso_local <2 x double> @vec_splatid() local_unnamed_addr {
+; CHECK-LABEL: vec_splatid:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:xxspltidp vs34, 1065353216
+; CHECK-NEXT:blr
+entry:
+ ret <2 x double>
+}
Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -512,3 +512,72 @@
// CHECK-LE-NEXT: ret <4 x i32>
return vec_inserth(vuia, vuib, uia);
}
+
+vector signed int test_vec_vec_splati_si(void) {
+ // CHECK-BE: ret <4 x i32>
+ // CHECK: ret <4 x i32>
+ return vec_splati(-17);
+}
+
+vector unsigned int test_vec_vec_splati_ui(void) {
+ // CHECK-BE: ret <4 x i32>
+ // CHECK: ret <4 x i32>
+ return vec_splati(16U);
+}
+
+vector float test_vec_vec_splati_f(void) {
+ // CHECK-BE: ret <4 x float>
+ // CHECK: ret <4 x float>
+ return vec_splati(1.0f);
+}
+
+vector double test_vec_vec_splatid(void) {
+ // CHECK-BE: [[T1:%.+]] = fpext float %{{.+}} to double
+ // CHECK-BE-NEXT: [[T2:%.+]] = insertelement <2 x double> undef, double [[T1:%.+]], i32 0
+ // CHECK-BE-NEXT: [[T3:%.+]] = shufflevector <2 x double> [[T2:%.+]], <2 x double> undef, <2 x i32> zeroinitialize
+ // CHECK-BE-NEXT: ret <2 x double> [[T3:%.+]]
+ // CHECK: [[T1:%.+]] = fpext float %{{.+}} to double
+ // CHECK-NEXT: [[T2:%.+]] = insertelement <2 x double> undef, double [[T1:%.+]], i32 0
+ // CHECK-NEXT: [[T3:%.+]] = shufflevector <2 x double> [[T2:%.+]], <2 x double> undef, <2 x i32> zeroinitialize
+ // CHECK-NEXT: ret <2 x double> [[T3:%.+]]
+ return vec_splatid(1.0);
+}
+
+vector signed int test_vec_vec_splati_ins_si(void) {
+ // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
+ // CHECK-BE: [[T1:%.+]] = add i32 2, %{{.+}}
+ // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
+ // CHECK-BE: ret <4 x i32>
+ // CHECK: [[T1:%.+]] = sub i32 1, %{{.+}}
+ // CHECK: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
+ // CHECK: [[T2:%.+]] = sub i32 3, %{{.+}}
+ // CHECK: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T2]]
+ // CHECK: ret <4 x i32>
+ return vec_splati_ins(vsia, 0, -17);
+}
+
+vector unsigned int test_vec_vec_splati_ins_ui(void) {
+ // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
+ // CHECK-BE: [[T1:%.+]] = add i32 2, %{{.+}}
+ // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
+ // CHECK-BE: ret <4 x i32>
+ // CHECK: [[T1:%.+]] = sub i32 1, %{{.+}}
+ // CHECK: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
+ // CHECK: [[T2:%.+]] = sub i32 3, %{{.+}}
+ // CHECK: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T2]]
+ // CHECK: ret <4 x i32>
+ return vec_splati_ins(vuia, 1, 16U);
+}
+
+vector float test_vec_vec_splati_ins_f(void) {
+ // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 %{{.+}}
+ // CHECK-BE: [[T1:%.+]] = add i32 2, %{{.+}}
+ // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
+ // CHECK-BE: ret <4 x float>
+ // CHECK: [[T1:%.+]] = sub i32 1, %{{.+}}
+ // CHECK: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
+ // CHECK: [[T2:%.+]] = sub i32 3, %{{.+}}
+ // CHECK: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T2]]
+ // CHECK: ret <4 x float>
+ return vec_splati_ins(vfa, 0, 1.0f);
+}
Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -17094,6 +17094,58 @@
vector unsigned long long __c) {
return __builtin_vsx_xxblendvd(__a, __b, __c);
}
+
+/* vec_splati */
+
+#define vec_splati(__a)\
+ _Generic((__a), signed int
[PATCH] D82520: [Power10] Implement Vector Splat Immediate Builtins in LLVM/Clang
This revision was not accepted when it landed; it landed in state "Needs
Revision".
This revision was automatically updated to reflect the committed changes.
Closed by commit rG0c6b6e28e70c: [PowerPC] Implement Vector Splat Immediate
Builtins in Clang (authored by biplmish, committed by lei).
Herald added a project: clang.
Herald added a subscriber: cfe-commits.
Changed prior to commit:
https://reviews.llvm.org/D82520?vs=274748&id=275642#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82520/new/
https://reviews.llvm.org/D82520
Files:
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/test/CodeGen/PowerPC/p10-splatImm.ll
Index: llvm/test/CodeGen/PowerPC/p10-splatImm.ll
===
--- llvm/test/CodeGen/PowerPC/p10-splatImm.ll
+++ llvm/test/CodeGen/PowerPC/p10-splatImm.ll
@@ -286,3 +286,21 @@
entry:
ret double 0.00e+00
}
+
+define dso_local <4 x i32> @vec_splati() local_unnamed_addr {
+; CHECK-LABEL: vec_splati:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:xxspltiw vs34, -17
+; CHECK-NEXT:blr
+entry:
+ ret <4 x i32>
+}
+
+define dso_local <2 x double> @vec_splatid() local_unnamed_addr {
+; CHECK-LABEL: vec_splatid:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:xxspltidp vs34, 1065353216
+; CHECK-NEXT:blr
+entry:
+ ret <2 x double>
+}
Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -512,3 +512,72 @@
// CHECK-LE-NEXT: ret <4 x i32>
return vec_inserth(vuia, vuib, uia);
}
+
+vector signed int test_vec_vec_splati_si(void) {
+ // CHECK-BE: ret <4 x i32>
+ // CHECK: ret <4 x i32>
+ return vec_splati(-17);
+}
+
+vector unsigned int test_vec_vec_splati_ui(void) {
+ // CHECK-BE: ret <4 x i32>
+ // CHECK: ret <4 x i32>
+ return vec_splati(16U);
+}
+
+vector float test_vec_vec_splati_f(void) {
+ // CHECK-BE: ret <4 x float>
+ // CHECK: ret <4 x float>
+ return vec_splati(1.0f);
+}
+
+vector double test_vec_vec_splatid(void) {
+ // CHECK-BE: [[T1:%.+]] = fpext float %{{.+}} to double
+ // CHECK-BE-NEXT: [[T2:%.+]] = insertelement <2 x double> undef, double [[T1:%.+]], i32 0
+ // CHECK-BE-NEXT: [[T3:%.+]] = shufflevector <2 x double> [[T2:%.+]], <2 x double> undef, <2 x i32> zeroinitialize
+ // CHECK-BE-NEXT: ret <2 x double> [[T3:%.+]]
+ // CHECK: [[T1:%.+]] = fpext float %{{.+}} to double
+ // CHECK-NEXT: [[T2:%.+]] = insertelement <2 x double> undef, double [[T1:%.+]], i32 0
+ // CHECK-NEXT: [[T3:%.+]] = shufflevector <2 x double> [[T2:%.+]], <2 x double> undef, <2 x i32> zeroinitialize
+ // CHECK-NEXT: ret <2 x double> [[T3:%.+]]
+ return vec_splatid(1.0);
+}
+
+vector signed int test_vec_vec_splati_ins_si(void) {
+ // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
+ // CHECK-BE: [[T1:%.+]] = add i32 2, %{{.+}}
+ // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
+ // CHECK-BE: ret <4 x i32>
+ // CHECK: [[T1:%.+]] = sub i32 1, %{{.+}}
+ // CHECK: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
+ // CHECK: [[T2:%.+]] = sub i32 3, %{{.+}}
+ // CHECK: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T2]]
+ // CHECK: ret <4 x i32>
+ return vec_splati_ins(vsia, 0, -17);
+}
+
+vector unsigned int test_vec_vec_splati_ins_ui(void) {
+ // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
+ // CHECK-BE: [[T1:%.+]] = add i32 2, %{{.+}}
+ // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
+ // CHECK-BE: ret <4 x i32>
+ // CHECK: [[T1:%.+]] = sub i32 1, %{{.+}}
+ // CHECK: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
+ // CHECK: [[T2:%.+]] = sub i32 3, %{{.+}}
+ // CHECK: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T2]]
+ // CHECK: ret <4 x i32>
+ return vec_splati_ins(vuia, 1, 16U);
+}
+
+vector float test_vec_vec_splati_ins_f(void) {
+ // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 %{{.+}}
+ // CHECK-BE: [[T1:%.+]] = add i32 2, %{{.+}}
+ // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
+ // CHECK-BE: ret <4 x float>
+ // CHECK: [[T1:%.+]] = sub i32 1, %{{.+}}
+ // CHECK: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
+ // CHECK: [[T2:%.+]] = sub i32 3, %{{.+}}
+ // CHECK: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T2]]
+ // CHECK: ret <4 x float>
+ return vec_splati_ins(vfa, 0, 1.0f);
+}
Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -17094,6 +17094,58 @@
vector unsigned long long __c) {
return __builtin_vsx_xxblendvd(__a, __b, __c);
}
+
+/* vec_splati */
+
+#define vec_splati(__a)
[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend
lei added inline comments.
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13791
+ // Ensure that the load from the narrow width is being zero extended to i128.
+ if ((!ValidLDType) || (LD->getValueType(0) != MVT::i128) ||
+ (LD->getExtensionType() != ISD::ZEXTLOAD))
nit: don't need `()` aroud `!ValidLDType`
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13797
+ // we are creating in order to pattern match to the appropriate instruction
+ // in the backend.
+ SDValue Width = DAG.getIntPtrConstant(MemoryType.getScalarSizeInBits(), dl);
I don't think we need to explicitly say this sine everything we do here is for
pattern matching to appropriate instructions in the backend...
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13798
+ // in the backend.
+ SDValue Width = DAG.getIntPtrConstant(MemoryType.getScalarSizeInBits(), dl);
+ SDValue LoadOps[] = {LD->getChain(), LD->getBasePtr(), Width};
Can just merge this into the next line and remove this tmp value.
Comment at: llvm/test/CodeGen/PowerPC/p10-vsx-builtins.ll:6
+; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN: FileCheck %s
+
Please add tests for BE.
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[PATCH] D83364: [PowerPC][Power10] Implement Instruction definition and MC Tests for Load and Store VSX Vector with Zero or Sign Extend
lei added inline comments.
Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:431
+let mayLoad = 1, mayStore = 0, Predicates = [IsISA3_1] in {
+ // The XFormMemOp flag is set on the instruction format.
Instead of creating a new section like this, why not add to the existing one on
line 469? I realize that does not have `Predicates = [IsISA3_1]`, but I think
that is an oversight from previous patch and it should be added as those
instructions are also part of ISA3.1.
Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:439
+
+let mayLoad = 0, mayStore = 1, Predicates = [IsISA3_1] in {
+ // The XFormMemOp flag is set on the instruction format.
same.
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[PATCH] D82609: [PowerPC][Power10] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang
lei added inline comments.
Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:79
+vector signed int test_vec_dive_si(void) {
+ // CHECK: @llvm.ppc.altivec.vdivesw(<4 x i32>
+ // CHECK-NEXT: ret <4 x i32>
why does the ck stops matching at the first param? Shouldn't we check the
remaining param type and number of param are correct as well?
Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:854
+ [(set v4i32:$vD,
+ (int_ppc_altivec_vdivesw v4i32:$vA, v4i32:$vB))]>;
def VDIVEUW : VXForm_1<651, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
nit: indent to match up with `v4i32` on the previous line.
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[PATCH] D83364: [PowerPC][Power10] Implement Instruction definition and MC Tests for Load and Store VSX Vector with Zero or Sign Extend
lei accepted this revision. lei added a comment. LGTM thx. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83364/new/ https://reviews.llvm.org/D83364 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.
lei added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:14273 +// The third argument to vec_replace_elt will be emitted to either +// the vinsw or vinsd instruction. It must be a compile time constant. +ConstantInt *ArgCI = dyn_cast(Ops[2]); Do you mean? ``` // The third argument of vec_replace_elt must be a compile time constant and will be emitted either // to the vinsw or vinsd instruction. ``` Comment at: clang/lib/CodeGen/CGBuiltin.cpp:14289 + else +ConstArg = (ConstArg * 4); + Ops[2] = ConstantInt::getSigned(Int32Ty, ConstArg); ``` ConstArg *= 4; // Fix the constant according to endianess. if (getTarget().isLittleEndian()) ConstArg = 12 - ConstArg; ``` Comment at: clang/lib/CodeGen/CGBuiltin.cpp:14320 +Call = Builder.CreateCall(F, Ops); +} +return Call; What are the chances of reaching to the end of this if/else-if section and `Call` is null? ie `getPrimitiveSizeInBits() != [32|64]` I feel like it would be better if we can structure it so that we are not doing all these nesting of `if`s and just do returns within the diff if-conditions. Have you tried to pull out the diff handling of 32/64bit arg and consolidating the code a bit? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83500/new/ https://reviews.llvm.org/D83500 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D83516: [PowerPC][Power10] 128-bit Binary Integer Operation instruction definitions and MC Tests
lei accepted this revision. lei added a comment. This revision is now accepted and ready to land. LGTM Please address the nits on commit. Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:1022 + def XSCVUQQP : X_VT5_XO5_VB5<63, 3, 836, "xscvuqqp", []>; + def XSCVSQQP: X_VT5_XO5_VB5<63, 11, 836, "xscvsqqp", []>; } nit: looks like there's a mix of diff spacings in the section above. Please keep it consistent. It should be `def NAME : DEF` Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83516/new/ https://reviews.llvm.org/D83516 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10
lei accepted this revision as: lei. lei added a comment. LGTM, please address the 1 comment I have on commit. Comment at: clang/test/Parser/altivec-bool-128.c:6 +// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-cpu pwr10 \ +// RUN:-target-feature +altivec -target-feature +vsx \ +// RUN:-target-feature -power10-vector -fsyntax-only -verify %s I don't think this is needed here `-target-feature +altivec` Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D81816/new/ https://reviews.llvm.org/D81816 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D81836: [PowerPC][Power10] Implement Vector Permute Builtins in LLVM/Clang
lei added a comment. This is PR still valid? I see dup def in https://reviews.llvm.org/D82365. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D81836/new/ https://reviews.llvm.org/D81836 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D82431: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang
lei accepted this revision as: lei. lei added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82431/new/ https://reviews.llvm.org/D82431 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D82431: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang
lei added a comment. encoding tests need to be placed in corresponding `ppc64-encoding-ISA31*` files Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82431/new/ https://reviews.llvm.org/D82431 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend
lei added a comment. Please move encoding tests to `ppc64-encoding-ISA31.[txt|s]`. Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13792 + if ((LD->getValueType(0) != MVT::i128) || + (LD->getExtensionType() != ISD::ZEXTLOAD) || (!ValidLDType)) +return SDValue(); nit: check ValidLDType first: ``` if (! ValidLDType || (LD->getValueType(0) != MVT::i128) || (LD->getExtensionType() != ISD::ZEXTLOAD) ||) ``` Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.h:528 +/// Allows utilization of the Load VSX Vector Rightmost Instructions. +LXVRZX }; nit: This shouldn't matter to code gen, but it would be nice to have this defined closer to other similar instructions. Maybe after `LXVD2X`? Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:225 +def PPClxvrzx : SDNode<"PPCISD::LXVRZX", SDT_PPCLXVRZX, +[SDNPHasChain, SDNPMayLoad]>; + nit: indentation Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ https://reviews.llvm.org/D82502 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D82467: [PowerPC][Power10] Implement Truncate and Store VSX Vector Builtins
lei requested changes to this revision.
lei added a comment.
This revision now requires changes to proceed.
Please move encoding tests to ppc64-encoding-ISA31.[txt|s].
Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:108
+ signed char *__c) {
+ // CHECK-BE: store i8 %{{.+}}, i8* %{{.+}}, align 1
+ // CHECK-LE: store i8 %{{.+}}, i8* %{{.+}}, align 1
I don't see a run line above that uses `CHECK-BE|CHECK-LE`. Since all these
look the same, did you mean to use the default `CHECK`?
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[PATCH] D82431: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang
lei accepted this revision. lei added a comment. LGTM thx! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82431/new/ https://reviews.llvm.org/D82431 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D78308: [NFC][PowerPC] Refactor ppcUserFeaturesCheck()
lei created this revision.
lei added reviewers: nemanjai, stefanp.
Herald added subscribers: shchenz, kbarton.
Herald added a project: clang.
This function keeps growing, refactor to use lambda.
Repository:
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Files:
clang/lib/Basic/Targets/PPC.cpp
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -228,33 +228,23 @@
static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
const std::vector &FeaturesVec) {
- if (llvm::find(FeaturesVec, "-vsx") != FeaturesVec.end()) {
-if (llvm::find(FeaturesVec, "+power8-vector") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector"
- << "-mno-vsx";
- return false;
-}
+ if (llvm::find(FeaturesVec, "-vsx") == FeaturesVec.end())
+return true;
-if (llvm::find(FeaturesVec, "+direct-move") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move"
- << "-mno-vsx";
+ auto CheckVSXSubfeature = [&](StringRef Feature, StringRef Option) {
+if (llvm::find(FeaturesVec, Feature) != FeaturesVec.end()) {
+ Diags.Report(diag::err_opt_not_valid_with_opt) << Option << "-mno-vsx";
return false;
}
+return true;
+ };
-if (llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128"
- << "-mno-vsx";
- return false;
-}
+ bool Passed = CheckVSXSubfeature("+power8-vector", "-mpower8-vector");
+ Passed |= CheckVSXSubfeature("+direct-move", "-mdirect-move");
+ Passed |= CheckVSXSubfeature("+direct-move", "-mfloat128");
+ Passed |= CheckVSXSubfeature("+direct-move", "-mpower9-vector");
-if (llvm::find(FeaturesVec, "+power9-vector") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector"
- << "-mno-vsx";
- return false;
-}
- }
-
- return true;
+ return Passed;
}
bool PPCTargetInfo::initFeatureMap(
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -228,33 +228,23 @@
static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
const std::vector &FeaturesVec) {
- if (llvm::find(FeaturesVec, "-vsx") != FeaturesVec.end()) {
-if (llvm::find(FeaturesVec, "+power8-vector") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector"
- << "-mno-vsx";
- return false;
-}
+ if (llvm::find(FeaturesVec, "-vsx") == FeaturesVec.end())
+return true;
-if (llvm::find(FeaturesVec, "+direct-move") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move"
- << "-mno-vsx";
+ auto CheckVSXSubfeature = [&](StringRef Feature, StringRef Option) {
+if (llvm::find(FeaturesVec, Feature) != FeaturesVec.end()) {
+ Diags.Report(diag::err_opt_not_valid_with_opt) << Option << "-mno-vsx";
return false;
}
+return true;
+ };
-if (llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128"
- << "-mno-vsx";
- return false;
-}
+ bool Passed = CheckVSXSubfeature("+power8-vector", "-mpower8-vector");
+ Passed |= CheckVSXSubfeature("+direct-move", "-mdirect-move");
+ Passed |= CheckVSXSubfeature("+direct-move", "-mfloat128");
+ Passed |= CheckVSXSubfeature("+direct-move", "-mpower9-vector");
-if (llvm::find(FeaturesVec, "+power9-vector") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector"
- << "-mno-vsx";
- return false;
-}
- }
-
- return true;
+ return Passed;
}
bool PPCTargetInfo::initFeatureMap(
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[PATCH] D78308: [NFC][PowerPC] Refactor ppcUserFeaturesCheck()
lei updated this revision to Diff 258119.
lei added a comment.
Fix mistake in code
Repository:
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Files:
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Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -241,8 +241,8 @@
bool Passed = CheckVSXSubfeature("+power8-vector", "-mpower8-vector");
Passed |= CheckVSXSubfeature("+direct-move", "-mdirect-move");
- Passed |= CheckVSXSubfeature("+direct-move", "-mfloat128");
- Passed |= CheckVSXSubfeature("+direct-move", "-mpower9-vector");
+ Passed |= CheckVSXSubfeature("+mfloat128", "-mfloat128");
+ Passed |= CheckVSXSubfeature("+mpower9-vector", "-mpower9-vector");
return Passed;
}
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -241,8 +241,8 @@
bool Passed = CheckVSXSubfeature("+power8-vector", "-mpower8-vector");
Passed |= CheckVSXSubfeature("+direct-move", "-mdirect-move");
- Passed |= CheckVSXSubfeature("+direct-move", "-mfloat128");
- Passed |= CheckVSXSubfeature("+direct-move", "-mpower9-vector");
+ Passed |= CheckVSXSubfeature("+mfloat128", "-mfloat128");
+ Passed |= CheckVSXSubfeature("+mpower9-vector", "-mpower9-vector");
return Passed;
}
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[PATCH] D78308: [NFC][PowerPC] Refactor ppcUserFeaturesCheck()
lei updated this revision to Diff 258121.
lei added a comment.
update
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Files:
clang/lib/Basic/Targets/PPC.cpp
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -228,33 +228,23 @@
static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
const std::vector &FeaturesVec) {
- if (llvm::find(FeaturesVec, "-vsx") != FeaturesVec.end()) {
-if (llvm::find(FeaturesVec, "+power8-vector") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector"
- << "-mno-vsx";
- return false;
-}
+ if (llvm::find(FeaturesVec, "-vsx") == FeaturesVec.end())
+return true;
-if (llvm::find(FeaturesVec, "+direct-move") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move"
- << "-mno-vsx";
+ auto CheckVSXSubfeature = [&](StringRef Feature, StringRef Option) {
+if (llvm::find(FeaturesVec, Feature) != FeaturesVec.end()) {
+ Diags.Report(diag::err_opt_not_valid_with_opt) << Option << "-mno-vsx";
return false;
}
+return true;
+ };
-if (llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128"
- << "-mno-vsx";
- return false;
-}
+ bool Passed = CheckVSXSubfeature("+power8-vector", "-mpower8-vector");
+ Passed |= CheckVSXSubfeature("+direct-move", "-mdirect-move");
+ Passed |= CheckVSXSubfeature("+mfloat128", "-mfloat128");
+ Passed |= CheckVSXSubfeature("+mpower9-vector", "-mpower9-vector");
-if (llvm::find(FeaturesVec, "+power9-vector") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector"
- << "-mno-vsx";
- return false;
-}
- }
-
- return true;
+ return Passed;
}
bool PPCTargetInfo::initFeatureMap(
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -228,33 +228,23 @@
static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
const std::vector &FeaturesVec) {
- if (llvm::find(FeaturesVec, "-vsx") != FeaturesVec.end()) {
-if (llvm::find(FeaturesVec, "+power8-vector") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector"
- << "-mno-vsx";
- return false;
-}
+ if (llvm::find(FeaturesVec, "-vsx") == FeaturesVec.end())
+return true;
-if (llvm::find(FeaturesVec, "+direct-move") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move"
- << "-mno-vsx";
+ auto CheckVSXSubfeature = [&](StringRef Feature, StringRef Option) {
+if (llvm::find(FeaturesVec, Feature) != FeaturesVec.end()) {
+ Diags.Report(diag::err_opt_not_valid_with_opt) << Option << "-mno-vsx";
return false;
}
+return true;
+ };
-if (llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128"
- << "-mno-vsx";
- return false;
-}
+ bool Passed = CheckVSXSubfeature("+power8-vector", "-mpower8-vector");
+ Passed |= CheckVSXSubfeature("+direct-move", "-mdirect-move");
+ Passed |= CheckVSXSubfeature("+mfloat128", "-mfloat128");
+ Passed |= CheckVSXSubfeature("+mpower9-vector", "-mpower9-vector");
-if (llvm::find(FeaturesVec, "+power9-vector") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector"
- << "-mno-vsx";
- return false;
-}
- }
-
- return true;
+ return Passed;
}
bool PPCTargetInfo::initFeatureMap(
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[PATCH] D78308: [NFC][PowerPC] Refactor ppcUserFeaturesCheck()
lei updated this revision to Diff 258175.
lei added a comment.
updated.
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Files:
clang/lib/Basic/Targets/PPC.cpp
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -228,33 +228,23 @@
static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
const std::vector &FeaturesVec) {
- if (llvm::find(FeaturesVec, "-vsx") != FeaturesVec.end()) {
-if (llvm::find(FeaturesVec, "+power8-vector") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector"
- << "-mno-vsx";
- return false;
-}
+ if (llvm::find(FeaturesVec, "-vsx") == FeaturesVec.end())
+return true;
-if (llvm::find(FeaturesVec, "+direct-move") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move"
- << "-mno-vsx";
+ auto CheckVSXSubfeature = [&](StringRef Feature, StringRef Option) {
+if (llvm::find(FeaturesVec, Feature) != FeaturesVec.end()) {
+ Diags.Report(diag::err_opt_not_valid_with_opt) << Option << "-mno-vsx";
return false;
}
+return true;
+ };
-if (llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128"
- << "-mno-vsx";
- return false;
-}
+ bool Passed = CheckVSXSubfeature("+power8-vector", "-mpower8-vector");
+ Passed |= CheckVSXSubfeature("+direct-move", "-mdirect-move");
+ Passed |= CheckVSXSubfeature("+float128", "-mfloat128");
+ Passed |= CheckVSXSubfeature("+power9-vector", "-mpower9-vector");
-if (llvm::find(FeaturesVec, "+power9-vector") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector"
- << "-mno-vsx";
- return false;
-}
- }
-
- return true;
+ return Passed;
}
bool PPCTargetInfo::initFeatureMap(
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -228,33 +228,23 @@
static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
const std::vector &FeaturesVec) {
- if (llvm::find(FeaturesVec, "-vsx") != FeaturesVec.end()) {
-if (llvm::find(FeaturesVec, "+power8-vector") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector"
- << "-mno-vsx";
- return false;
-}
+ if (llvm::find(FeaturesVec, "-vsx") == FeaturesVec.end())
+return true;
-if (llvm::find(FeaturesVec, "+direct-move") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move"
- << "-mno-vsx";
+ auto CheckVSXSubfeature = [&](StringRef Feature, StringRef Option) {
+if (llvm::find(FeaturesVec, Feature) != FeaturesVec.end()) {
+ Diags.Report(diag::err_opt_not_valid_with_opt) << Option << "-mno-vsx";
return false;
}
+return true;
+ };
-if (llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128"
- << "-mno-vsx";
- return false;
-}
+ bool Passed = CheckVSXSubfeature("+power8-vector", "-mpower8-vector");
+ Passed |= CheckVSXSubfeature("+direct-move", "-mdirect-move");
+ Passed |= CheckVSXSubfeature("+float128", "-mfloat128");
+ Passed |= CheckVSXSubfeature("+power9-vector", "-mpower9-vector");
-if (llvm::find(FeaturesVec, "+power9-vector") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector"
- << "-mno-vsx";
- return false;
-}
- }
-
- return true;
+ return Passed;
}
bool PPCTargetInfo::initFeatureMap(
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[PATCH] D78308: [NFC][PowerPC] Refactor ppcUserFeaturesCheck()
lei marked an inline comment as done.
lei added inline comments.
Comment at: clang/lib/Basic/Targets/PPC.cpp:243
+ bool Passed = CheckVSXSubfeature("+power8-vector", "-mpower8-vector");
+ Passed |= CheckVSXSubfeature("+direct-move", "-mdirect-move");
+ Passed |= CheckVSXSubfeature("+float128", "-mfloat128");
jsji wrote:
> Looks like this is will cause behavior change.. And NOT NFC at all..
>
> Before refactor, we will return false when *ANY* of the subfeature is ON.
> After refactor, we will only return false, when *ALL* of the subfeature are
> ON, Passed will be set to true when any of subfeature are off .
>
> Can you please double check?
You are right... will post an update.
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[PATCH] D78308: [NFC][PowerPC] Refactor ppcUserFeaturesCheck()
lei updated this revision to Diff 258375.
lei added a comment.
Address review comments
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Files:
clang/lib/Basic/Targets/PPC.cpp
clang/test/Driver/ppc-dependent-options.cpp
Index: clang/test/Driver/ppc-dependent-options.cpp
===
--- clang/test/Driver/ppc-dependent-options.cpp
+++ clang/test/Driver/ppc-dependent-options.cpp
@@ -54,6 +54,10 @@
// RUN: -mcpu=power9 -std=c++11 -mno-vsx -mfloat128 %s 2>&1 | \
// RUN: FileCheck %s -check-prefix=CHECK-NVSX-FLT128
+// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -mcpu=power9 -std=c++11 -mno-vsx -mfloat128 -mpower9-vector %s 2>&1 | \
+// RUN: FileCheck %s -check-prefix=CHECK-NVSX-MULTI
+
#ifdef __VSX__
static_assert(false, "VSX enabled");
#endif
@@ -78,5 +82,7 @@
// CHECK-NVSX-P9V: error: option '-mpower9-vector' cannot be specified with
'-mno-vsx'
// CHECK-NVSX-FLT128: error: option '-mfloat128' cannot be specified with
'-mno-vsx'
// CHECK-NVSX-DMV: error: option '-mdirect-move' cannot be specified with
'-mno-vsx'
+// CHECK-NVSX-MULTI: error: option '-mfloat128' cannot be specified with
'-mno-vsx'
+// CHECK-NVSX-MULTI: error: option '-mpower9-vector' cannot be specified with
'-mno-vsx'
// CHECK-NVSX: Neither enabled
// CHECK-VSX: VSX enabled
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -228,33 +228,25 @@
static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
const std::vector &FeaturesVec) {
- if (llvm::find(FeaturesVec, "-vsx") != FeaturesVec.end()) {
-if (llvm::find(FeaturesVec, "+power8-vector") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector"
- << "-mno-vsx";
- return false;
-}
-
-if (llvm::find(FeaturesVec, "+direct-move") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move"
- << "-mno-vsx";
- return false;
-}
-
-if (llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128"
- << "-mno-vsx";
- return false;
+ // vsx was not explicitly turned off.
+ if (llvm::find(FeaturesVec, "-vsx") == FeaturesVec.end())
+return true;
+
+ auto FindVSXSubfeature = [&](StringRef Feature, StringRef Option) {
+if (llvm::find(FeaturesVec, Feature) != FeaturesVec.end()) {
+ Diags.Report(diag::err_opt_not_valid_with_opt) << Option << "-mno-vsx";
+ return true;
}
+return false;
+ };
-if (llvm::find(FeaturesVec, "+power9-vector") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector"
- << "-mno-vsx";
- return false;
-}
- }
+ bool Found = FindVSXSubfeature("+power8-vector", "-mpower8-vector");
+ Found |= FindVSXSubfeature("+direct-move", "-mdirect-move");
+ Found |= FindVSXSubfeature("+float128", "-mfloat128");
+ Found |= FindVSXSubfeature("+power9-vector", "-mpower9-vector");
- return true;
+ // Return false if any vsx subfeatures was found.
+ return !Found;
}
bool PPCTargetInfo::initFeatureMap(
Index: clang/test/Driver/ppc-dependent-options.cpp
===
--- clang/test/Driver/ppc-dependent-options.cpp
+++ clang/test/Driver/ppc-dependent-options.cpp
@@ -54,6 +54,10 @@
// RUN: -mcpu=power9 -std=c++11 -mno-vsx -mfloat128 %s 2>&1 | \
// RUN: FileCheck %s -check-prefix=CHECK-NVSX-FLT128
+// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -mcpu=power9 -std=c++11 -mno-vsx -mfloat128 -mpower9-vector %s 2>&1 | \
+// RUN: FileCheck %s -check-prefix=CHECK-NVSX-MULTI
+
#ifdef __VSX__
static_assert(false, "VSX enabled");
#endif
@@ -78,5 +82,7 @@
// CHECK-NVSX-P9V: error: option '-mpower9-vector' cannot be specified with '-mno-vsx'
// CHECK-NVSX-FLT128: error: option '-mfloat128' cannot be specified with '-mno-vsx'
// CHECK-NVSX-DMV: error: option '-mdirect-move' cannot be specified with '-mno-vsx'
+// CHECK-NVSX-MULTI: error: option '-mfloat128' cannot be specified with '-mno-vsx'
+// CHECK-NVSX-MULTI: error: option '-mpower9-vector' cannot be specified with '-mno-vsx'
// CHECK-NVSX: Neither enabled
// CHECK-VSX: VSX enabled
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -228,33 +228,25 @@
static bool ppcUserFeaturesCheck(Diagnostics
[PATCH] D78308: [NFC][PowerPC] Refactor ppcUserFeaturesCheck()
This revision was automatically updated to reflect the committed changes.
lei marked an inline comment as done.
Closed by commit rG10b60dde7670: [PowerPC] Refactor ppcUserFeaturesCheck()
(authored by lei).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D78308/new/
https://reviews.llvm.org/D78308
Files:
clang/lib/Basic/Targets/PPC.cpp
clang/test/Driver/ppc-dependent-options.cpp
Index: clang/test/Driver/ppc-dependent-options.cpp
===
--- clang/test/Driver/ppc-dependent-options.cpp
+++ clang/test/Driver/ppc-dependent-options.cpp
@@ -54,6 +54,10 @@
// RUN: -mcpu=power9 -std=c++11 -mno-vsx -mfloat128 %s 2>&1 | \
// RUN: FileCheck %s -check-prefix=CHECK-NVSX-FLT128
+// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -mcpu=power9 -std=c++11 -mno-vsx -mfloat128 -mpower9-vector %s 2>&1 | \
+// RUN: FileCheck %s -check-prefix=CHECK-NVSX-MULTI
+
#ifdef __VSX__
static_assert(false, "VSX enabled");
#endif
@@ -78,5 +82,7 @@
// CHECK-NVSX-P9V: error: option '-mpower9-vector' cannot be specified with
'-mno-vsx'
// CHECK-NVSX-FLT128: error: option '-mfloat128' cannot be specified with
'-mno-vsx'
// CHECK-NVSX-DMV: error: option '-mdirect-move' cannot be specified with
'-mno-vsx'
+// CHECK-NVSX-MULTI: error: option '-mfloat128' cannot be specified with
'-mno-vsx'
+// CHECK-NVSX-MULTI: error: option '-mpower9-vector' cannot be specified with
'-mno-vsx'
// CHECK-NVSX: Neither enabled
// CHECK-VSX: VSX enabled
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -228,33 +228,25 @@
static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
const std::vector &FeaturesVec) {
- if (llvm::find(FeaturesVec, "-vsx") != FeaturesVec.end()) {
-if (llvm::find(FeaturesVec, "+power8-vector") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector"
- << "-mno-vsx";
- return false;
-}
-
-if (llvm::find(FeaturesVec, "+direct-move") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move"
- << "-mno-vsx";
- return false;
-}
-
-if (llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128"
- << "-mno-vsx";
- return false;
+ // vsx was not explicitly turned off.
+ if (llvm::find(FeaturesVec, "-vsx") == FeaturesVec.end())
+return true;
+
+ auto FindVSXSubfeature = [&](StringRef Feature, StringRef Option) {
+if (llvm::find(FeaturesVec, Feature) != FeaturesVec.end()) {
+ Diags.Report(diag::err_opt_not_valid_with_opt) << Option << "-mno-vsx";
+ return true;
}
+return false;
+ };
-if (llvm::find(FeaturesVec, "+power9-vector") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector"
- << "-mno-vsx";
- return false;
-}
- }
+ bool Found = FindVSXSubfeature("+power8-vector", "-mpower8-vector");
+ Found |= FindVSXSubfeature("+direct-move", "-mdirect-move");
+ Found |= FindVSXSubfeature("+float128", "-mfloat128");
+ Found |= FindVSXSubfeature("+power9-vector", "-mpower9-vector");
- return true;
+ // Return false if any vsx subfeatures was found.
+ return !Found;
}
bool PPCTargetInfo::initFeatureMap(
Index: clang/test/Driver/ppc-dependent-options.cpp
===
--- clang/test/Driver/ppc-dependent-options.cpp
+++ clang/test/Driver/ppc-dependent-options.cpp
@@ -54,6 +54,10 @@
// RUN: -mcpu=power9 -std=c++11 -mno-vsx -mfloat128 %s 2>&1 | \
// RUN: FileCheck %s -check-prefix=CHECK-NVSX-FLT128
+// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -mcpu=power9 -std=c++11 -mno-vsx -mfloat128 -mpower9-vector %s 2>&1 | \
+// RUN: FileCheck %s -check-prefix=CHECK-NVSX-MULTI
+
#ifdef __VSX__
static_assert(false, "VSX enabled");
#endif
@@ -78,5 +82,7 @@
// CHECK-NVSX-P9V: error: option '-mpower9-vector' cannot be specified with '-mno-vsx'
// CHECK-NVSX-FLT128: error: option '-mfloat128' cannot be specified with '-mno-vsx'
// CHECK-NVSX-DMV: error: option '-mdirect-move' cannot be specified with '-mno-vsx'
+// CHECK-NVSX-MULTI: error: option '-mfloat128' cannot be specified with '-mno-vsx'
+// CHECK-NVSX-MULTI: error: option '-mpower9-vector' cannot be specified with '-mno-vsx'
// CHECK-NVSX: Neither enabled
// CHECK-VSX: VSX enabled
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/T
[PATCH] D77542: [PowerPC] Treat 'Z' inline asm constraint as a true memory constraint
lei accepted this revision as: lei. lei added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D77542/new/ https://reviews.llvm.org/D77542 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in the front end
lei created this revision.
lei added reviewers: stefanp, nemanjai, amyk, hfinkel, power-llvm-team.
Herald added subscribers: shchenz, wuzish.
Herald added a project: clang.
jsji added a reviewer: PowerPC.
jsji added a project: PowerPC.
This patch simply adds support for the new CPU in anticipation of
Power10. There isn't really any functionality added so there are no
associated test cases at this time.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D80020
Files:
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/lib/Driver/ToolChains/Arch/PPC.cpp
clang/test/Misc/target-invalid-cpu-note.c
clang/test/Preprocessor/init-ppc64.c
Index: clang/test/Preprocessor/init-ppc64.c
===
--- clang/test/Preprocessor/init-ppc64.c
+++ clang/test/Preprocessor/init-ppc64.c
@@ -627,6 +627,22 @@
// PPCPOWER9:#define _ARCH_PWR7 1
// PPCPOWER9:#define _ARCH_PWR9 1
//
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu pwr10 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER10 %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu power10 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER10 %s
+//
+// PPCPOWER10:#define _ARCH_PPC 1
+// PPCPOWER10:#define _ARCH_PPC64 1
+// PPCPOWER10:#define _ARCH_PPCGR 1
+// PPCPOWER10:#define _ARCH_PPCSQ 1
+// PPCPOWER10:#define _ARCH_PWR10 1
+// PPCPOWER10:#define _ARCH_PWR4 1
+// PPCPOWER10:#define _ARCH_PWR5 1
+// PPCPOWER10:#define _ARCH_PWR5X 1
+// PPCPOWER10:#define _ARCH_PWR6 1
+// PPCPOWER10-NOT:#define _ARCH_PWR6X 1
+// PPCPOWER10:#define _ARCH_PWR7 1
+// PPCPOWER10:#define _ARCH_PWR9 1
+//
// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu future -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCFUTURE %s
//
// PPCFUTURE:#define _ARCH_PPC 1
Index: clang/test/Misc/target-invalid-cpu-note.c
===
--- clang/test/Misc/target-invalid-cpu-note.c
+++ clang/test/Misc/target-invalid-cpu-note.c
@@ -81,7 +81,7 @@
// PPC-SAME: 603e, 603ev, 604, 604e, 620, 630, g3, 7400, g4, 7450, g4+, 750,
// PPC-SAME: 8548, 970, g5, a2, a2q, e500, e500mc, e5500, power3, pwr3, power4,
// PPC-SAME: pwr4, power5, pwr5, power5x, pwr5x, power6, pwr6, power6x, pwr6x,
-// PPC-SAME: power7, pwr7, power8, pwr8, power9, pwr9, powerpc, ppc, powerpc64,
+// PPC-SAME: power7, pwr7, power8, pwr8, power9, pwr9, power10, pwr10, powerpc, ppc, powerpc64,
// PPC-SAME: ppc64, powerpc64le, ppc64le, future
// RUN: not %clang_cc1 -triple mips--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix MIPS
Index: clang/lib/Driver/ToolChains/Arch/PPC.cpp
===
--- clang/lib/Driver/ToolChains/Arch/PPC.cpp
+++ clang/lib/Driver/ToolChains/Arch/PPC.cpp
@@ -70,6 +70,7 @@
.Case("power7", "pwr7")
.Case("power8", "pwr8")
.Case("power9", "pwr9")
+.Case("power10", "pwr10")
.Case("future", "future")
.Case("pwr3", "pwr3")
.Case("pwr4", "pwr4")
@@ -80,6 +81,7 @@
.Case("pwr7", "pwr7")
.Case("pwr8", "pwr8")
.Case("pwr9", "pwr9")
+.Case("pwr10", "pwr10")
.Case("powerpc", "ppc")
.Case("powerpc64", "ppc64")
.Case("powerpc64le", "ppc64le")
@@ -91,14 +93,16 @@
const char *ppc::getPPCAsmModeForCPU(StringRef Name) {
return llvm::StringSwitch(Name)
-.Case("pwr7", "-mpower7")
-.Case("power7", "-mpower7")
-.Case("pwr8", "-mpower8")
-.Case("power8", "-mpower8")
-.Case("ppc64le", "-mpower8")
-.Case("pwr9", "-mpower9")
-.Case("power9", "-mpower9")
-.Default("-many");
+ .Case("pwr7", "-mpower7")
+ .Case("power7", "-mpower7")
+ .Case("pwr8", "-mpower8")
+ .Case("power8", "-mpower8")
+ .Case("ppc64le", "-mpower8")
+ .Case("pwr9", "-mpower9")
+ .Case("power9", "-mpower9")
+ .Case("pwr10", "-mpower10")
+ .Case("power10", "-mpower10")
+ .Default("-many");
}
void ppc::getPPCTargetFeatures(const Driver &D, const llvm::Triple &Triple,
Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -43,13 +43,13 @@
ArchDefinePwr7 = 1 << 11,
ArchDefinePwr8 = 1 << 12,
ArchDefinePwr9 = 1 << 13,
-ArchDefineFuture = 1 << 14,
-ArchDefineA2 = 1 << 15,
-ArchDefineA2q = 1 << 16,
-ArchDefineE500 = 1 << 17
+ArchDefinePwr10 = 1 << 14,
+ArchDefineFuture = 1 << 15,
+ArchDefineA2 = 1 << 16,
+ArchDefineA2q = 1 << 17,
+ArchDefineE500 = 1 << 18
} ArchDefineTypes;
-
ArchDefineTypes ArchDefs = ArchDefineNone;
static const Builtin::Info BuiltinInfo
[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm
lei updated this revision to Diff 264301.
lei added a comment.
Herald added subscribers: llvm-commits, hiraditya.
Herald added a project: LLVM.
Add support in llvm.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D80020/new/
https://reviews.llvm.org/D80020
Files:
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/lib/Driver/ToolChains/Arch/PPC.cpp
clang/test/Misc/target-invalid-cpu-note.c
clang/test/Preprocessor/init-ppc64.c
llvm/lib/Support/Host.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/test/CodeGen/PowerPC/check-cpu.ll
Index: llvm/test/CodeGen/PowerPC/check-cpu.ll
===
--- llvm/test/CodeGen/PowerPC/check-cpu.ll
+++ llvm/test/CodeGen/PowerPC/check-cpu.ll
@@ -2,6 +2,10 @@
; RUN: -mcpu=future < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=future < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=power10 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 < %s | FileCheck %s
; Test mcpu=future that should be recognized on PowerPC.
Index: llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
===
--- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -654,7 +654,8 @@
unsigned Directive = ST->getCPUDirective();
// Assume that Future CPU has the same cache line size as the others.
if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
- Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+ Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+ Directive == PPC::DIR_PWR_FUTURE)
return 128;
// On other processors return a default of 64 bytes.
@@ -688,7 +689,8 @@
// FIXME: the same for P9 as previous gen until POWER9 scheduling is ready
// Assume that future is the same as the others.
if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
- Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+ Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+ Directive == PPC::DIR_PWR_FUTURE)
return 12;
// For most things, modern systems have two execution units (and
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -57,6 +57,7 @@
DIR_PWR7,
DIR_PWR8,
DIR_PWR9,
+DIR_PWR10,
DIR_PWR_FUTURE,
DIR_64
};
@@ -138,6 +139,7 @@
bool HasAddiLoadFusion;
bool HasAddisLoadFusion;
bool IsISA3_0;
+ bool IsISA3_1;
bool UseLongCalls;
bool SecurePlt;
bool VectorsUseTwoUnits;
@@ -308,6 +310,7 @@
bool hasHTM() const { return HasHTM; }
bool hasFloat128() const { return HasFloat128; }
bool isISA3_0() const { return IsISA3_0; }
+ bool isISA3_1() const { return IsISA3_1; }
bool useLongCalls() const { return UseLongCalls; }
bool hasFusion() const { return HasFusion; }
bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1305,6 +1305,7 @@
case PPC::DIR_PWR7:
case PPC::DIR_PWR8:
case PPC::DIR_PWR9:
+ case PPC::DIR_PWR10:
case PPC::DIR_PWR_FUTURE:
setPrefLoopAlignment(Align(16));
setPrefFunctionAlignment(Align(16));
@@ -14896,6 +14897,7 @@
case PPC::DIR_PWR7:
case PPC::DIR_PWR8:
case PPC::DIR_PWR9:
+ case PPC::DIR_PWR10:
case PPC::DIR_PWR_FUTURE: {
if (!ML)
break;
@@ -16085,6 +16087,7 @@
// vector7 2 2
return true;
case PPC::DIR_PWR9:
+case PPC::DIR_PWR10:
case PPC::DIR_PWR_FUTURE:
// typemul addshl
// scalar5 2 2
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -51,6 +51,7 @@
def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">;
def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">;
def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">;
+def DirectivePwr10: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR10", "">;
def DirectivePwrFuture
: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">;
@@ -205,6 +206,9 @@
def FeatureISA3_0 : Subt
[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm
lei updated this revision to Diff 264303.
lei retitled this revision from " [PowerPC] Add support for -mcpu=pwr10 in both
clang and llvm" to "[PowerPC] Add support for -mcpu=pwr10 in both clang and
llvm".
lei added a comment.
missed a file
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D80020/new/
https://reviews.llvm.org/D80020
Files:
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/lib/Driver/ToolChains/Arch/PPC.cpp
clang/test/Misc/target-invalid-cpu-note.c
clang/test/Preprocessor/init-ppc64.c
llvm/lib/Support/Host.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/test/CodeGen/PowerPC/check-cpu.ll
Index: llvm/test/CodeGen/PowerPC/check-cpu.ll
===
--- llvm/test/CodeGen/PowerPC/check-cpu.ll
+++ llvm/test/CodeGen/PowerPC/check-cpu.ll
@@ -2,6 +2,10 @@
; RUN: -mcpu=future < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=future < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=power10 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 < %s | FileCheck %s
; Test mcpu=future that should be recognized on PowerPC.
Index: llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
===
--- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -654,7 +654,8 @@
unsigned Directive = ST->getCPUDirective();
// Assume that Future CPU has the same cache line size as the others.
if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
- Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+ Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+ Directive == PPC::DIR_PWR_FUTURE)
return 128;
// On other processors return a default of 64 bytes.
@@ -688,7 +689,8 @@
// FIXME: the same for P9 as previous gen until POWER9 scheduling is ready
// Assume that future is the same as the others.
if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
- Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR_FUTURE)
+ Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
+ Directive == PPC::DIR_PWR_FUTURE)
return 12;
// For most things, modern systems have two execution units (and
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -34,32 +34,33 @@
namespace PPC {
// -m directive values.
- enum {
-DIR_NONE,
-DIR_32,
-DIR_440,
-DIR_601,
-DIR_602,
-DIR_603,
-DIR_7400,
-DIR_750,
-DIR_970,
-DIR_A2,
-DIR_E500,
-DIR_E500mc,
-DIR_E5500,
-DIR_PWR3,
-DIR_PWR4,
-DIR_PWR5,
-DIR_PWR5X,
-DIR_PWR6,
-DIR_PWR6X,
-DIR_PWR7,
-DIR_PWR8,
-DIR_PWR9,
-DIR_PWR_FUTURE,
-DIR_64
- };
+enum {
+ DIR_NONE,
+ DIR_32,
+ DIR_440,
+ DIR_601,
+ DIR_602,
+ DIR_603,
+ DIR_7400,
+ DIR_750,
+ DIR_970,
+ DIR_A2,
+ DIR_E500,
+ DIR_E500mc,
+ DIR_E5500,
+ DIR_PWR3,
+ DIR_PWR4,
+ DIR_PWR5,
+ DIR_PWR5X,
+ DIR_PWR6,
+ DIR_PWR6X,
+ DIR_PWR7,
+ DIR_PWR8,
+ DIR_PWR9,
+ DIR_PWR10,
+ DIR_PWR_FUTURE,
+ DIR_64
+};
}
class GlobalValue;
@@ -138,6 +139,7 @@
bool HasAddiLoadFusion;
bool HasAddisLoadFusion;
bool IsISA3_0;
+ bool IsISA3_1;
bool UseLongCalls;
bool SecurePlt;
bool VectorsUseTwoUnits;
@@ -308,6 +310,7 @@
bool hasHTM() const { return HasHTM; }
bool hasFloat128() const { return HasFloat128; }
bool isISA3_0() const { return IsISA3_0; }
+ bool isISA3_1() const { return IsISA3_1; }
bool useLongCalls() const { return UseLongCalls; }
bool hasFusion() const { return HasFusion; }
bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1305,6 +1305,7 @@
case PPC::DIR_PWR7:
case PPC::DIR_PWR8:
case PPC::DIR_PWR9:
+ case PPC::DIR_PWR10:
case PPC::DIR_PWR_FUTURE:
setPrefLoopAlignment(Align(16));
setPrefFunctionAlignment(Align(16));
@@ -14896,6 +14897,7 @@
case PPC::DIR_PWR7:
case PPC::DIR_PWR8:
case PPC::DIR_PWR9:
+ case PPC::DIR_PWR10:
case PPC::DIR_PWR_FUTURE: {
if (!ML)
break;
@@ -16085,6 +16087,7 @@
// vector7 2 2
return true;
case PPC::DIR_PWR9:
+case PPC::DIR_PWR10:
case
[PATCH] D128288: [PowerPC] Fix signatures for vec_replace_unaligned builtin
This revision was automatically updated to reflect the committed changes.
Closed by commit rGcaf7243a6b53: [PowerPC] Fix signatures for
vec_replace_unaligned builtin (authored by lei).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D128288/new/
https://reviews.llvm.org/D128288
Files:
clang/lib/Headers/altivec.h
clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c
clang/test/CodeGen/PowerPC/builtins-ppc-vec-ins-error.c
Index: clang/test/CodeGen/PowerPC/builtins-ppc-vec-ins-error.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-vec-ins-error.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-vec-ins-error.c
@@ -49,12 +49,12 @@
}
#elif defined(__TEST_UNALIGNED_UI)
-vector unsigned int test_vec_replace_unaligned_ui(void) {
+vector unsigned char test_vec_replace_unaligned_ui(void) {
return vec_replace_unaligned(vuia, uia, 16); // expected-error {{byte number 16 is outside of the valid range [0, 12]}}
}
#else
-vector unsigned long long test_vec_replace_unaligned_ull(void) {
+vector unsigned char test_vec_replace_unaligned_ull(void) {
return vec_replace_unaligned(vulla, ulla, 12); // expected-error {{byte number 12 is outside of the valid range [0, 8]}}
}
#endif
Index: clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c
@@ -1183,8 +1183,7 @@
// CHECK-BE-NEXT:[[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
// CHECK-BE-NEXT:[[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 6)
// CHECK-BE-NEXT:[[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
-// CHECK-BE-NEXT:[[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>
-// CHECK-BE-NEXT:ret <4 x i32> [[TMP6]]
+// CHECK-BE-NEXT:ret <16 x i8> [[TMP5]]
//
// CHECK-LE-LABEL: @test_vec_replace_unaligned_si(
// CHECK-LE-NEXT: entry:
@@ -1194,10 +1193,9 @@
// CHECK-LE-NEXT:[[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
// CHECK-LE-NEXT:[[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 6)
// CHECK-LE-NEXT:[[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
-// CHECK-LE-NEXT:[[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>
-// CHECK-LE-NEXT:ret <4 x i32> [[TMP6]]
+// CHECK-LE-NEXT:ret <16 x i8> [[TMP5]]
//
-vector signed int test_vec_replace_unaligned_si(void) {
+vector unsigned char test_vec_replace_unaligned_si(void) {
return vec_replace_unaligned(vsia, sia, 6);
}
@@ -1209,8 +1207,7 @@
// CHECK-BE-NEXT:[[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
// CHECK-BE-NEXT:[[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 8)
// CHECK-BE-NEXT:[[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
-// CHECK-BE-NEXT:[[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>
-// CHECK-BE-NEXT:ret <4 x i32> [[TMP6]]
+// CHECK-BE-NEXT:ret <16 x i8> [[TMP5]]
//
// CHECK-LE-LABEL: @test_vec_replace_unaligned_ui(
// CHECK-LE-NEXT: entry:
@@ -1220,10 +1217,9 @@
// CHECK-LE-NEXT:[[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
// CHECK-LE-NEXT:[[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 8)
// CHECK-LE-NEXT:[[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
-// CHECK-LE-NEXT:[[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>
-// CHECK-LE-NEXT:ret <4 x i32> [[TMP6]]
+// CHECK-LE-NEXT:ret <16 x i8> [[TMP5]]
//
-vector unsigned int test_vec_replace_unaligned_ui(void) {
+vector unsigned char test_vec_replace_unaligned_ui(void) {
return vec_replace_unaligned(vuia, uia, 8);
}
@@ -1236,8 +1232,7 @@
// CHECK-BE-NEXT:[[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
// CHECK-BE-NEXT:[[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 12)
// CHECK-BE-NEXT:[[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
-// CHECK-BE-NEXT:[[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float>
-// CHECK-BE-NEXT:ret <4 x float> [[TMP6]]
+// CHECK-BE-NEXT:ret <16 x i8> [[TMP5]]
//
// CHECK-LE-LABEL: @test_vec_replace_unaligned_f(
// CHECK-LE-NEXT: entry:
@@ -1248,10 +1243,9 @@
// CHECK-LE-NEXT:[[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
// CHECK-LE-NEXT:[[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 12)
// CHECK-LE-NEXT:[[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
-// CHECK-LE-NEXT:[[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float>
-// CHECK-LE-NEXT:ret <4 x float> [[TMP6]]
+// CHECK-LE-NEXT:ret <16 x i8> [[TMP5]]
//
-vector float test_vec_replace_unaligned_f(void) {
+vector unsigned char test_vec_
[PATCH] D129016: [PowerPC] implemented @llvm.ppc.kill.canary to corrupt stack guard
lei added inline comments. Comment at: llvm/test/CodeGen/PowerPC/kill-canary-intrinsic.ll:4 +; RUN: --ppc-asm-full-reg-names < %s | FileCheck %s -check-prefix=AIX +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux \ +; RUN: --ppc-asm-full-reg-names < %s | FileCheck %s -check-prefix=LINUX missing LE run test line? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D129016/new/ https://reviews.llvm.org/D129016 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D131622: [NFC][PowerPC] Add missing NOCOMPAT checks for builtins-ppc-xlcompat.c
lei created this revision.
lei added reviewers: nemanjai, amyk, power-llvm-team.
Herald added a subscriber: shchenz.
Herald added a project: All.
lei requested review of this revision.
Herald added a project: clang.
Followup patch to address request from https://reviews.llvm.org/D124093
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D131622
Files:
clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
@@ -21,29 +21,38 @@
void test() {
// CHECK-LABEL: @test(
// CHECK-NEXT: entry:
-// CHECK-LE-LABEL: @test(
-// CHECK-LE-NEXT: entry:
+// NOCOMPAT-LABEL: @test(
+// NOCOMPAT-NEXT: entry:
res_vf = vec_ctf(vsll, 4);
// CHECK: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vsll, align 16
// CHECK-NEXT:[[TMP1:%.*]] = call <4 x float> @llvm.ppc.vsx.xvcvsxdsp(<2 x
i64> [[TMP0]])
// CHECK-NEXT:fmul <4 x float> [[TMP1]],
+// NOCOMPAT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vsll, align 16
+// NOCOMPAT-NEXT: [[CONV:%.*]] = sitofp <2 x i64> [[TMP0]] to <2 x double>
+// NOCOMPAT-NEXT: fmul <2 x double> [[CONV]],
res_vf = vec_ctf(vull, 4);
// CHECK: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* @vull, align 16
// CHECK-NEXT:[[TMP3:%.*]] = call <4 x float> @llvm.ppc.vsx.xvcvuxdsp(<2 x
i64> [[TMP2]])
// CHECK-NEXT:fmul <4 x float> [[TMP3]],
+// NOCOMPAT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* @vull, align 16
+// NOCOMPAT-NEXT: [[CONV1:%.*]] = uitofp <2 x i64> [[TMP2]] to <2 x double>
+// NOCOMPAT-NEXT: fmul <2 x double> [[CONV1]],
res_vsll = vec_cts(vd, 4);
// CHECK: [[TMP4:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
// CHECK-NEXT:fmul <2 x double> [[TMP4]],
// CHECK: call <4 x i32> @llvm.ppc.vsx.xvcvdpsxws(<2 x double>
+// NOCOMPAT: [[TMP4:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
+// NOCOMPAT-NEXT: fmul <2 x double> [[TMP4]],
res_vull = vec_ctu(vd, 4);
// CHECK: [[TMP8:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
// CHECK-NEXT:fmul <2 x double> [[TMP8]],
// CHECK: call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
-// NONCOMPAT: call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
+// NOCOMPAT: [[TMP7:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
+// NOCOMPAT-NEXT: fmul <2 x double> [[TMP7]],
res_vd = vec_round(vd);
// CHECK: call double @llvm.ppc.readflm()
Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
@@ -21,29 +21,38 @@
void test() {
// CHECK-LABEL: @test(
// CHECK-NEXT: entry:
-// CHECK-LE-LABEL: @test(
-// CHECK-LE-NEXT: entry:
+// NOCOMPAT-LABEL: @test(
+// NOCOMPAT-NEXT: entry:
res_vf = vec_ctf(vsll, 4);
// CHECK: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vsll, align 16
// CHECK-NEXT:[[TMP1:%.*]] = call <4 x float> @llvm.ppc.vsx.xvcvsxdsp(<2 x i64> [[TMP0]])
// CHECK-NEXT:fmul <4 x float> [[TMP1]],
+// NOCOMPAT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vsll, align 16
+// NOCOMPAT-NEXT: [[CONV:%.*]] = sitofp <2 x i64> [[TMP0]] to <2 x double>
+// NOCOMPAT-NEXT: fmul <2 x double> [[CONV]],
res_vf = vec_ctf(vull, 4);
// CHECK: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* @vull, align 16
// CHECK-NEXT:[[TMP3:%.*]] = call <4 x float> @llvm.ppc.vsx.xvcvuxdsp(<2 x i64> [[TMP2]])
// CHECK-NEXT:fmul <4 x float> [[TMP3]],
+// NOCOMPAT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* @vull, align 16
+// NOCOMPAT-NEXT: [[CONV1:%.*]] = uitofp <2 x i64> [[TMP2]] to <2 x double>
+// NOCOMPAT-NEXT: fmul <2 x double> [[CONV1]],
res_vsll = vec_cts(vd, 4);
// CHECK: [[TMP4:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
// CHECK-NEXT:fmul <2 x double> [[TMP4]],
// CHECK: call <4 x i32> @llvm.ppc.vsx.xvcvdpsxws(<2 x double>
+// NOCOMPAT: [[TMP4:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
+// NOCOMPAT-NEXT: fmul <2 x double> [[TMP4]],
res_vull = vec_ctu(vd, 4);
// CHECK: [[TMP8:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
// CHECK-NEXT:fmul <2 x double> [[TMP8]],
// CHECK: call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
-// NONCOMPAT: call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
+// NOCOMPAT: [[TMP7:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
+// NOCOMPAT-NEXT: fmul <2 x double> [[TMP7]],
res_vd = vec_round(vd);
// CHECK: call double @llvm.ppc.readflm()
___
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cfe-commits@lists.llvm.org
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[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
lei added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:1569 + def int_ppc_sthcx : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrWriteMem]>; + def int_ppc_lharx : GCCBuiltin<"__builtin_ppc_lharx">, + Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>; do these loads not need `IntrReadMem`? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105946/new/ https://reviews.llvm.org/D105946 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
lei added inline comments. Comment at: clang/lib/Sema/SemaChecking.cpp:3371 +return SemaFeatureCheck(*this, TheCall, "extdiv", +diag::err_ppc_builtin_only_on_arch, "8"); #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \ need tests for these. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105946/new/ https://reviews.llvm.org/D105946 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D105930: [PowerPC] Implement XL compact math builtins
lei updated this revision to Diff 359050.
lei marked 3 inline comments as done.
lei added a comment.
Address review comments to add/upate:
- builtin encoding for params that need to be folded into constant expr
- llvm intrinsic property for immediates
- test line for `-mattr=-vsx`
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105930/new/
https://reviews.llvm.org/D105930
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-error.c
clang/test/CodeGen/builtins-ppc-xlcompat-math.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrVSX.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+
+define dso_local zeroext i32 @extract_exp(double %d) {
+; CHECK-LABEL: extract_exp:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:xsxexpdp 3, 1
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: extract_exp:
+; CHECK-32BIT: # %bb.0: # %entry
+; CHECK-32BIT-NEXT:xsxexpdp 3, 1
+; CHECK-32BIT-NEXT:# kill: def $r3 killed $r3 killed $x3
+; CHECK-32BIT-NEXT:blr
+entry:
+ %0 = tail call i32 @llvm.ppc.extract.exp(double %d)
+ ret i32 %0
+}
+declare i32 @llvm.ppc.extract.exp(double)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
@@ -0,0 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s
+
+define dso_local i64 @extract_sig(double %d) {
+; CHECK-LABEL: extract_sig:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:xsxsigdp 3, 1
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call i64 @llvm.ppc.extract.sig(double %d)
+ ret i64 %0
+}
+declare i64 @llvm.ppc.extract.sig(double)
+
+define dso_local double @insert_exp(double %d, i64 %ull) {
+; CHECK-LABEL: insert_exp:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mffprd 3, 1
+; CHECK-NEXT:xsiexpdp 1, 3, 4
+; CHECK-NEXT:# kill: def $f1 killed $f1 killed $vsl1
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call double @llvm.ppc.insert.exp(double %d, i64 %ull)
+ ret double %0
+}
+declare double @llvm.ppc.insert.exp(double, i64)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
@@ -0,0 +1,231 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s |\
+; RUN: FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr7 \
+; RUN: < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix -mcpu=pwr8 < %s |\
+; RUN: FileCheck %s --check-prefix=CHECK-PWR8
+
+define dso_local void @mtfsb0() {
+; CHECK-PWR8-LABEL: mtfsb0:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT:mtfsb0 10
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: mtfsb0:
+; CHECK-NOVSX: # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:mtfsb0 10
+; CHECK-NOVSX-NEXT:
[PATCH] D105930: [PowerPC] Implement XL compact math builtins
lei added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.td:3650 +// XL Compat intrinsics. +def : Pat<(int_ppc_fmsub f64:$A, f64:$B, f64:$C), (FMSUB $A, $B, $C)>; +def : Pat<(int_ppc_fmsubs f32:$A, f32:$B, f32:$C), (FMSUBS $A, $B, $C)>; nemanjai wrote: > Please review the order of operands carefully here. I believe the order is > wrong either for this one or for the VSX version. Double-check all of the > others as well please. I double checked and both seem correct to me. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105930/new/ https://reviews.llvm.org/D105930 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D105930: [PowerPC] Implement XL compact math builtins
lei updated this revision to Diff 359070.
lei added a comment.
rebase to ToT
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105930/new/
https://reviews.llvm.org/D105930
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-error.c
clang/test/CodeGen/builtins-ppc-xlcompat-math.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrVSX.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+
+define dso_local zeroext i32 @extract_exp(double %d) {
+; CHECK-LABEL: extract_exp:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:xsxexpdp 3, 1
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: extract_exp:
+; CHECK-32BIT: # %bb.0: # %entry
+; CHECK-32BIT-NEXT:xsxexpdp 3, 1
+; CHECK-32BIT-NEXT:# kill: def $r3 killed $r3 killed $x3
+; CHECK-32BIT-NEXT:blr
+entry:
+ %0 = tail call i32 @llvm.ppc.extract.exp(double %d)
+ ret i32 %0
+}
+declare i32 @llvm.ppc.extract.exp(double)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
@@ -0,0 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s
+
+define dso_local i64 @extract_sig(double %d) {
+; CHECK-LABEL: extract_sig:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:xsxsigdp 3, 1
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call i64 @llvm.ppc.extract.sig(double %d)
+ ret i64 %0
+}
+declare i64 @llvm.ppc.extract.sig(double)
+
+define dso_local double @insert_exp(double %d, i64 %ull) {
+; CHECK-LABEL: insert_exp:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mffprd 3, 1
+; CHECK-NEXT:xsiexpdp 1, 3, 4
+; CHECK-NEXT:# kill: def $f1 killed $f1 killed $vsl1
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call double @llvm.ppc.insert.exp(double %d, i64 %ull)
+ ret double %0
+}
+declare double @llvm.ppc.insert.exp(double, i64)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
@@ -0,0 +1,231 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s |\
+; RUN: FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr7 \
+; RUN: < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix -mcpu=pwr8 < %s |\
+; RUN: FileCheck %s --check-prefix=CHECK-PWR8
+
+define dso_local void @mtfsb0() {
+; CHECK-PWR8-LABEL: mtfsb0:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT:mtfsb0 10
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: mtfsb0:
+; CHECK-NOVSX: # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:mtfsb0 10
+; CHECK-NOVSX-NEXT:blr
+;
+; CHECK-PWR7-LABEL: mtfsb0:
+; CHECK-PWR7: # %bb.0: # %entry
+; CHECK-PWR7-NEXT:mtfsb0 10
+; CHECK-PWR7-NEXT:blr
+entry:
+ tail call void @llvm.ppc.mtfsb0(i32 10)
+ ret void
+}
+
+d
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
lei added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:1569 } - nit: un-related line deletion Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.td:5449 + def : Pat<(int_ppc_sthcx xoaddr:$dst, gprc:$A), + (STHCX (EXTSH gprc:$A), xoaddr:$dst)>; +} `EXTSH` should not be needed and we should not be using `xoaddr` Comment at: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll:7 +; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \ +; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \ this is confusing... maybe this shouldjust be `CHECK-32BIT` Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105946/new/ https://reviews.llvm.org/D105946 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D105930: [PowerPC] Implement XL compact math builtins
lei added inline comments.
Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.td:3087
// RM should be set.
+let hasSideEffects = 1 in {
def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
nemanjai wrote:
> nemanjai wrote:
> > I think we should conservatively set RM as an implicit def here. @ZhangKang
> > you modified this code most recently, please provide your opinion here.
> This was not addressed. Will this be added in a follow-up patch?
Yes, sorry I will address this in a subsequent patch since adding RM will cause
unrelated LIT failures.
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[PATCH] D105930: [PowerPC] Implement XL compact math builtins
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGc8937b6cb975: [PowerPC] Implement XL compact math builtins
(authored by lei).
Changed prior to commit:
https://reviews.llvm.org/D105930?vs=359070&id=359397#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105930/new/
https://reviews.llvm.org/D105930
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-error.c
clang/test/CodeGen/builtins-ppc-xlcompat-math.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrVSX.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+
+define dso_local zeroext i32 @extract_exp(double %d) {
+; CHECK-LABEL: extract_exp:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:xsxexpdp 3, 1
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: extract_exp:
+; CHECK-32BIT: # %bb.0: # %entry
+; CHECK-32BIT-NEXT:xsxexpdp 3, 1
+; CHECK-32BIT-NEXT:# kill: def $r3 killed $r3 killed $x3
+; CHECK-32BIT-NEXT:blr
+entry:
+ %0 = tail call i32 @llvm.ppc.extract.exp(double %d)
+ ret i32 %0
+}
+declare i32 @llvm.ppc.extract.exp(double)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
@@ -0,0 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s
+
+define dso_local i64 @extract_sig(double %d) {
+; CHECK-LABEL: extract_sig:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:xsxsigdp 3, 1
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call i64 @llvm.ppc.extract.sig(double %d)
+ ret i64 %0
+}
+declare i64 @llvm.ppc.extract.sig(double)
+
+define dso_local double @insert_exp(double %d, i64 %ull) {
+; CHECK-LABEL: insert_exp:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mffprd 3, 1
+; CHECK-NEXT:xsiexpdp 1, 3, 4
+; CHECK-NEXT:# kill: def $f1 killed $f1 killed $vsl1
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call double @llvm.ppc.insert.exp(double %d, i64 %ull)
+ ret double %0
+}
+declare double @llvm.ppc.insert.exp(double, i64)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
@@ -0,0 +1,231 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s |\
+; RUN: FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr7 \
+; RUN: < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix -mcpu=pwr8 < %s |\
+; RUN: FileCheck %s --check-prefix=CHECK-PWR8
+
+define dso_local void @mtfsb0() {
+; CHECK-PWR8-LABEL: mtfsb0:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT:mtfsb0 10
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: mtfsb0:
+; CHECK-NOVSX: # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:mtfsb
[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins
lei added inline comments.
Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c:15
+ // CHECK-LABEL: @test_lwarx
// CHECK: %0 = tail call i32 asm sideeffect "lwarx $0, ${1:y}",
"=r,*Z,~{memory}"(i32* %a)
return __lwarx(a);
where is the check for `CHECK-NON-PWR8-ERR:`?
Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c:36
// CHECK: %0 = bitcast i32* %a to i8*
// CHECK: %1 = tail call i32 @llvm.ppc.stwcx(i8* %0, i32 %val)
return __stwcx(a, val);
`CHECK-NON-PWR8-ERR:` check?
Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-stfiw.c:2
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN: -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc64le-unknown-unknown \
why are we only testing this for pwr9 vs pwr7/8 similar to other tests added?
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[PATCH] D105957: [PowerPC] Implement intrinsics for mtfsf[i]
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG35a18a981f6b: [PowerPC] Implement intrinsics for mtfsf[i]
(authored by nemanjai, committed by lei).
Changed prior to commit:
https://reviews.llvm.org/D105957?vs=358491&id=359451#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105957/new/
https://reviews.llvm.org/D105957
Files:
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-math.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/P9InstrResources.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
llvm/test/CodeGen/PowerPC/fpscr-intrinsics.ll
Index: llvm/test/CodeGen/PowerPC/fpscr-intrinsics.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/fpscr-intrinsics.ll
@@ -0,0 +1,121 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | \
+; RUN: FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr7 \
+; RUN: < %s | FileCheck %s --check-prefix=CHECK-AIX64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix -mcpu=pwr8 < %s | \
+; RUN: FileCheck %s --check-prefix=CHECK-AIX32
+
+define dso_local void @mtfsb0() local_unnamed_addr #0 {
+; CHECK-PWR8-LABEL: mtfsb0:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT:mtfsb0 10
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-PWR7-LABEL: mtfsb0:
+; CHECK-PWR7: # %bb.0: # %entry
+; CHECK-PWR7-NEXT:mtfsb0 10
+; CHECK-PWR7-NEXT:blr
+; CHECK-LABEL: mtfsb0:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mtfsb0 10
+; CHECK-NEXT:blr
+;
+; CHECK-AIX64-LABEL: mtfsb0:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:mtfsb0 10
+; CHECK-AIX64-NEXT:blr
+;
+; CHECK-AIX32-LABEL: mtfsb0:
+; CHECK-AIX32: # %bb.0: # %entry
+; CHECK-AIX32-NEXT:mtfsb0 10
+; CHECK-AIX32-NEXT:blr
+entry:
+ tail call void @llvm.ppc.mtfsb0(i32 10)
+ ret void
+}
+
+define dso_local void @mtfsb1() local_unnamed_addr #0 {
+; CHECK-PWR8-LABEL: mtfsb1:
+; CHECK-PWR8: # %bb.0: # %entry
+; CHECK-PWR8-NEXT:mtfsb1 0
+; CHECK-PWR8-NEXT:blr
+;
+; CHECK-PWR7-LABEL: mtfsb1:
+; CHECK-PWR7: # %bb.0: # %entry
+; CHECK-PWR7-NEXT:mtfsb1 0
+; CHECK-PWR7-NEXT:blr
+; CHECK-LABEL: mtfsb1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mtfsb1 0
+; CHECK-NEXT:blr
+;
+; CHECK-AIX64-LABEL: mtfsb1:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:mtfsb1 0
+; CHECK-AIX64-NEXT:blr
+;
+; CHECK-AIX32-LABEL: mtfsb1:
+; CHECK-AIX32: # %bb.0: # %entry
+; CHECK-AIX32-NEXT:mtfsb1 0
+; CHECK-AIX32-NEXT:blr
+entry:
+ tail call void @llvm.ppc.mtfsb1(i32 0)
+ ret void
+}
+
+define dso_local void @callmtfsf(i32 zeroext %a) local_unnamed_addr {
+; CHECK-LABEL: callmtfsf:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mtfprwz 0, 3
+; CHECK-NEXT:xscvuxddp 0, 0
+; CHECK-NEXT:mtfsf 7, 0
+; CHECK-NEXT:blr
+;
+; CHECK-AIX64-LABEL: callmtfsf:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:addi 4, 1, -4
+; CHECK-AIX64-NEXT:stw 3, -4(1)
+; CHECK-AIX64-NEXT:lfiwzx 0, 0, 4
+; CHECK-AIX64-NEXT:xscvuxddp 0, 0
+; CHECK-AIX64-NEXT:mtfsf 7, 0
+; CHECK-AIX64-NEXT:blr
+;
+; CHECK-AIX32-LABEL: callmtfsf:
+; CHECK-AIX32: # %bb.0: # %entry
+; CHECK-AIX32-NEXT:addi 4, 1, -4
+; CHECK-AIX32-NEXT:stw 3, -4(1)
+; CHECK-AIX32-NEXT:lfiwzx 0, 0, 4
+; CHECK-AIX32-NEXT:xscvuxddp 0, 0
+; CHECK-AIX32-NEXT:mtfsf 7, 0
+; CHECK-AIX32-NEXT:blr
+entry:
+ %0 = uitofp i32 %a to double
+ tail call void @llvm.ppc.mtfsf(i32 7, double %0)
+ ret void
+}
+
+define dso_local void @callmtfsfi(i32 zeroext %a) local_unnamed_addr {
+; CHECK-LABEL: callmtfsfi:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:mtfsfi 1, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX64-LABEL: callmtfsfi:
+; CHECK-AIX64: # %bb.0: # %entry
+; CHECK-AIX64-NEXT:mtfsfi 1, 3
+; CHECK-AIX64-NEXT:blr
+;
+; CHECK-AIX32-LABEL: callmtfsfi:
+; CHECK-AIX32: # %bb.0: # %entry
+; CHECK-AIX32-NEXT:mtfsfi 1, 3
+; CHECK-AIX32-NEXT:blr
+entry:
+ tail call void @llvm.ppc.mtfsfi(i32 1, i32 3)
+ ret void
+}
+
+declare void @llvm.ppc.mtfsb0(i32)
+declare void @llvm.ppc.mtfsb1(i32)
+declare void @llvm.ppc.mtfsfi(i32, i32)
+declare void @llvm.ppc.mtfsf(i32, double)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
@@ -10,50 +10,6 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix -mcpu=pwr8 < %s |\
; RUN: FileCheck %s --che
[PATCH] D106130: [PowerPC] Implemented mtmsr, mfspr, mtspr Builtins
lei added inline comments. Comment at: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll:3 +; NOTE: Had to manually modify the last test case (mtmsr) to allow the +; NOTE: common check of mtmsr instead of 4 different check prefixes ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ No need to add this `NOTE`. Just remove the atuo generate line above. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106130/new/ https://reviews.llvm.org/D106130 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.
lei added a comment. please rebase to ToT Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D103986/new/ https://reviews.llvm.org/D103986 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D106484: [PowerPC] Add PowerPC "__stbcx" builtin and intrinsic for XL compatibility
lei added inline comments. Comment at: clang/include/clang/Basic/BuiltinsPPC.def:116 BUILTIN(__builtin_ppc_fres, "ff", "") +BUILTIN(__builtin_ppc_stbcx, "icD*i", "") maybe move this up to where `__builtin_ppc_stdcx` is defined. To match what you did in `PPC.cpp` Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c:31 + return __builtin_ppc_stbcx(c_addr, c); +} Why not just add this tc to `clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c`? The other related store functions are tested there. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106484/new/ https://reviews.llvm.org/D106484 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D106757: [PowerPC] Implement partial vector ld/st builtins for XL compatibility
lei added inline comments.
Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15133
+bool IsLE = getTarget().isLittleEndian();
+auto StoreSubVec = [&](unsigned Width, unsigned Offset, unsigned EltNo) {
+ switch (Width) {
I find the nested switch to be a bit confusing at first. Maybe it can be done
a bit diff?
```
auto StoreSubVec ...
if (Width==16) {
}
switch (Width) {
default: ...
case :
//set the ConvTy, NumElts for non-16byte widths
}
// code to handle non-16 byte stores
}
```
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D106757/new/
https://reviews.llvm.org/D106757
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D106757: [PowerPC] Implement partial vector ld/st builtins for XL compatibility
lei accepted this revision. lei added a comment. thx for the update! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106757/new/ https://reviews.llvm.org/D106757 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D107002: [PowerPC] Implement XL compatibility builtin __addex
lei created this revision.
lei added reviewers: stefanp, nemanjai, NeHuang, power-llvm-team.
Herald added subscribers: shchenz, hiraditya.
lei requested review of this revision.
Herald added projects: clang, LLVM.
Add builtin and intrinsic for `__addex`.
This patch is part of a series of patches to provide builtins for
compatibility with the XL compiler.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D107002
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/P9InstrResources.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
@@ -29,3 +29,25 @@
ret double %0
}
declare double @llvm.ppc.insert.exp(double, i64)
+
+
+declare i64 @llvm.ppc.addex(i64, i64, i32 immarg)
+define dso_local i64 @call_addex_0(i64 %a, i64 %b) {
+; CHECK-LABEL: call_addex_0:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addex 3, 3, 4, 0
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call i64 @llvm.ppc.addex(i64 %a, i64 %b, i32 0)
+ ret i64 %0
+}
+
+define dso_local i64 @call_addex_1(i64 %a, i64 %b) {
+; CHECK-LABEL: call_addex_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addex 3, 3, 4, 0
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call i64 @llvm.ppc.addex(i64 %a, i64 %b, i32 0)
+ ret i64 %0
+}
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1670,6 +1670,13 @@
"hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>;
}
+let Interpretation64Bit = 1, isCodeGenOnly = 1, hasSideEffects = 1 in
+def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$rT),
+ (ins g8rc:$rA, g8rc:$rB, u2imm:$CY),
+ "addex $rT, $rA, $rB, $CY", IIC_IntGeneral,
+ [(set i64:$rT, (int_ppc_addex i64:$rA, i64:$rB,
+timm:$CY))]>;
+
//===--===//
// Instruction Patterns
//
@@ -1828,7 +1835,6 @@
"slbieg $RS, $RB", IIC_SprSLBIEG, []>;
// SLB Synchronize
def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>;
-
} // IsISA3_0
def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
Index: llvm/lib/Target/PowerPC/P9InstrResources.td
===
--- llvm/lib/Target/PowerPC/P9InstrResources.td
+++ llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -1430,5 +1430,6 @@
DCBI,
DCCCI,
ICCCI,
- ADDEX
+ ADDEX,
+ ADDEX8
)> { let Unsupported = 1; }
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1706,7 +1706,10 @@
def int_ppc_fres
: GCCBuiltin<"__builtin_ppc_fres">,
Intrinsic <[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
-
+ def int_ppc_addex
+ : GCCBuiltin<"__builtin_ppc_addex">,
+Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty],
+ [IntrNoMem, IntrHasSideEffects, ImmArg>]>;
def int_ppc_fsel : GCCBuiltin<"__builtin_ppc_fsel">,
Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty,
llvm_double_ty], [IntrNoMem]>;
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
@@ -0,0 +1,11 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr9 \
+// RUN: -verify %s
+
+extern unsigned long long ull;
+extern long long ll;
+
+void test_builtin_ppc_addex() {
+ long long res = __builtin_ppc_addex(ll, ll, 1); // expected-warning {{argument value 1 will resullt in undefined behaviour}}
+ unsigned long long res2 = __builtin_ppc_addex(ull, ull, 3); // expected-warning {{argument value 3 will resullt in undefined behaviour}}
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
===
--- clang/test/Cod
[PATCH] D107002: [PowerPC] Implement XL compatibility builtin __addex
lei updated this revision to Diff 362535.
lei added a comment.
fix minor wording and spelling mistakes.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D107002/new/
https://reviews.llvm.org/D107002
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/P9InstrResources.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
@@ -29,3 +29,25 @@
ret double %0
}
declare double @llvm.ppc.insert.exp(double, i64)
+
+
+declare i64 @llvm.ppc.addex(i64, i64, i32 immarg)
+define dso_local i64 @call_addex_0(i64 %a, i64 %b) {
+; CHECK-LABEL: call_addex_0:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addex 3, 3, 4, 0
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call i64 @llvm.ppc.addex(i64 %a, i64 %b, i32 0)
+ ret i64 %0
+}
+
+define dso_local i64 @call_addex_1(i64 %a, i64 %b) {
+; CHECK-LABEL: call_addex_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addex 3, 3, 4, 0
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call i64 @llvm.ppc.addex(i64 %a, i64 %b, i32 0)
+ ret i64 %0
+}
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1670,6 +1670,13 @@
"hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>;
}
+let Interpretation64Bit = 1, isCodeGenOnly = 1, hasSideEffects = 1 in
+def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$rT),
+ (ins g8rc:$rA, g8rc:$rB, u2imm:$CY),
+ "addex $rT, $rA, $rB, $CY", IIC_IntGeneral,
+ [(set i64:$rT, (int_ppc_addex i64:$rA, i64:$rB,
+timm:$CY))]>;
+
//===--===//
// Instruction Patterns
//
@@ -1821,6 +1828,7 @@
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
def CP_COPY8 : X_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>;
def CP_PASTE8_rec : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isRecordForm;
+
}
// SLB Invalidate Entry Global
@@ -1828,7 +1836,6 @@
"slbieg $RS, $RB", IIC_SprSLBIEG, []>;
// SLB Synchronize
def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>;
-
} // IsISA3_0
def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
Index: llvm/lib/Target/PowerPC/P9InstrResources.td
===
--- llvm/lib/Target/PowerPC/P9InstrResources.td
+++ llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -1430,5 +1430,6 @@
DCBI,
DCCCI,
ICCCI,
- ADDEX
+ ADDEX,
+ ADDEX8
)> { let Unsupported = 1; }
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1706,7 +1706,10 @@
def int_ppc_fres
: GCCBuiltin<"__builtin_ppc_fres">,
Intrinsic <[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
-
+ def int_ppc_addex
+ : GCCBuiltin<"__builtin_ppc_addex">,
+Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty],
+ [IntrNoMem, IntrHasSideEffects, ImmArg>]>;
def int_ppc_fsel : GCCBuiltin<"__builtin_ppc_fsel">,
Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty,
llvm_double_ty], [IntrNoMem]>;
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
@@ -0,0 +1,11 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr9 \
+// RUN: -verify %s
+
+extern unsigned long long ull;
+extern long long ll;
+
+void test_builtin_ppc_addex() {
+ long long res = __builtin_ppc_addex(ll, ll, 1); // expected-warning {{argument value 1 will resullt in undefined behaviour}}
+ unsigned long long res2 = __builtin_ppc_addex(ull, ull, 3); // expected-warning {{argument value 3 will resullt in undefined behaviour}}
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-err
[PATCH] D107002: [PowerPC] Implement XL compatibility builtin __addex
lei updated this revision to Diff 362536.
lei added a comment.
remove extra space
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D107002/new/
https://reviews.llvm.org/D107002
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/P9InstrResources.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
@@ -29,3 +29,24 @@
ret double %0
}
declare double @llvm.ppc.insert.exp(double, i64)
+
+declare i64 @llvm.ppc.addex(i64, i64, i32 immarg)
+define dso_local i64 @call_addex_0(i64 %a, i64 %b) {
+; CHECK-LABEL: call_addex_0:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addex 3, 3, 4, 0
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call i64 @llvm.ppc.addex(i64 %a, i64 %b, i32 0)
+ ret i64 %0
+}
+
+define dso_local i64 @call_addex_1(i64 %a, i64 %b) {
+; CHECK-LABEL: call_addex_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addex 3, 3, 4, 0
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call i64 @llvm.ppc.addex(i64 %a, i64 %b, i32 0)
+ ret i64 %0
+}
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1670,6 +1670,13 @@
"hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>;
}
+let Interpretation64Bit = 1, isCodeGenOnly = 1, hasSideEffects = 1 in
+def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$rT),
+ (ins g8rc:$rA, g8rc:$rB, u2imm:$CY),
+ "addex $rT, $rA, $rB, $CY", IIC_IntGeneral,
+ [(set i64:$rT, (int_ppc_addex i64:$rA, i64:$rB,
+timm:$CY))]>;
+
//===--===//
// Instruction Patterns
//
@@ -1821,6 +1828,7 @@
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
def CP_COPY8 : X_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>;
def CP_PASTE8_rec : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isRecordForm;
+
}
// SLB Invalidate Entry Global
@@ -1828,7 +1836,6 @@
"slbieg $RS, $RB", IIC_SprSLBIEG, []>;
// SLB Synchronize
def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>;
-
} // IsISA3_0
def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
Index: llvm/lib/Target/PowerPC/P9InstrResources.td
===
--- llvm/lib/Target/PowerPC/P9InstrResources.td
+++ llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -1430,5 +1430,6 @@
DCBI,
DCCCI,
ICCCI,
- ADDEX
+ ADDEX,
+ ADDEX8
)> { let Unsupported = 1; }
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1706,7 +1706,10 @@
def int_ppc_fres
: GCCBuiltin<"__builtin_ppc_fres">,
Intrinsic <[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
-
+ def int_ppc_addex
+ : GCCBuiltin<"__builtin_ppc_addex">,
+Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty],
+ [IntrNoMem, IntrHasSideEffects, ImmArg>]>;
def int_ppc_fsel : GCCBuiltin<"__builtin_ppc_fsel">,
Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty,
llvm_double_ty], [IntrNoMem]>;
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
@@ -0,0 +1,11 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr9 \
+// RUN: -verify %s
+
+extern unsigned long long ull;
+extern long long ll;
+
+void test_builtin_ppc_addex() {
+ long long res = __builtin_ppc_addex(ll, ll, 1); // expected-warning {{argument value 1 will resullt in undefined behaviour}}
+ unsigned long long res2 = __builtin_ppc_addex(ull, ull, 3); // expected-warning {{argument value 3 will resullt in undefined behaviour}}
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
===
[PATCH] D107002: [PowerPC] Implement XL compatibility builtin __addex
lei updated this revision to Diff 362734.
lei added a comment.
put back unintentional space change
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D107002/new/
https://reviews.llvm.org/D107002
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/P9InstrResources.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
@@ -29,3 +29,24 @@
ret double %0
}
declare double @llvm.ppc.insert.exp(double, i64)
+
+declare i64 @llvm.ppc.addex(i64, i64, i32 immarg)
+define dso_local i64 @call_addex_0(i64 %a, i64 %b) {
+; CHECK-LABEL: call_addex_0:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addex 3, 3, 4, 0
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call i64 @llvm.ppc.addex(i64 %a, i64 %b, i32 0)
+ ret i64 %0
+}
+
+define dso_local i64 @call_addex_1(i64 %a, i64 %b) {
+; CHECK-LABEL: call_addex_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:addex 3, 3, 4, 0
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call i64 @llvm.ppc.addex(i64 %a, i64 %b, i32 0)
+ ret i64 %0
+}
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1670,6 +1670,13 @@
"hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>;
}
+let Interpretation64Bit = 1, isCodeGenOnly = 1, hasSideEffects = 1 in
+def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$rT),
+ (ins g8rc:$rA, g8rc:$rB, u2imm:$CY),
+ "addex $rT, $rA, $rB, $CY", IIC_IntGeneral,
+ [(set i64:$rT, (int_ppc_addex i64:$rA, i64:$rB,
+timm:$CY))]>;
+
//===--===//
// Instruction Patterns
//
Index: llvm/lib/Target/PowerPC/P9InstrResources.td
===
--- llvm/lib/Target/PowerPC/P9InstrResources.td
+++ llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -1430,5 +1430,6 @@
DCBI,
DCCCI,
ICCCI,
- ADDEX
+ ADDEX,
+ ADDEX8
)> { let Unsupported = 1; }
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1706,7 +1706,10 @@
def int_ppc_fres
: GCCBuiltin<"__builtin_ppc_fres">,
Intrinsic <[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
-
+ def int_ppc_addex
+ : GCCBuiltin<"__builtin_ppc_addex">,
+Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty],
+ [IntrNoMem, IntrHasSideEffects, ImmArg>]>;
def int_ppc_fsel : GCCBuiltin<"__builtin_ppc_fsel">,
Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty,
llvm_double_ty], [IntrNoMem]>;
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
@@ -0,0 +1,11 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr9 \
+// RUN: -verify %s
+
+extern unsigned long long ull;
+extern long long ll;
+
+void test_builtin_ppc_addex() {
+ long long res = __builtin_ppc_addex(ll, ll, 1); // expected-warning {{argument value 1 will resullt in undefined behaviour}}
+ unsigned long long res2 = __builtin_ppc_addex(ull, ull, 3); // expected-warning {{argument value 3 will resullt in undefined behaviour}}
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
@@ -9,7 +9,18 @@
// RUN: -fsyntax-only -Wall -Werror -verify %s
extern unsigned int ui;
+extern unsigned long long ull;
+extern long long ll;
void test_builtin_ppc_cmprb() {
int res = __builtin_ppc_cmprb(3, ui, ui); // expected-error {{argument value 3 is outside the valid range [0, 1]}}
}
+
+#ifdef __PPC64__
+
+void test_builtin_ppc_ad
[PATCH] D125506: [PowerPC] Implement XL compat __fnabs and __fnabss builtins.
lei accepted this revision. lei added a comment. This revision is now accepted and ready to land. LGTM with minor updates before commit. Comment at: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.c:25 +// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc-unknown-aix \ +// RUN: -emit-llvm %s -target-cpu pwr6 -o - | FileCheck %s + Since we emit `xsnabsdp` for pwr7 and above I don't think it's necessary to have all combination tested on both pwr7 and pwr8. Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.ll:24 + +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX I think the default pwr level is lower then pwr6 which means it's no vsx by default. Maybe add `pwr[7|8]` to these test lines to test the `-vsx` attr? Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.ll:45 +; CHECK-PWR6-NEXT:fnabs 1, 1 +; CHECK-PWR6-NEXT:blr +; probably don't need both NOVSX and PWR6 checks since they are the same. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125506/new/ https://reviews.llvm.org/D125506 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D125506: [PowerPC] Implement XL compat __fnabs and __fnabss builtins.
lei added inline comments. Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.ll:46 +; RUN: -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX + +declare double @llvm.ppc.fnabs(double) nit: same as before no need to test all combination for both pwr7 and pwr8. Just a mix of the 2 like in the clang test. What happens if we do pwr6 with `+vsx`? Is this a possible combination? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125506/new/ https://reviews.llvm.org/D125506 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D84968: [PowerPC] Legalize v256i1 and v512i1 and implement load and store of these types
lei accepted this revision.
lei added a comment.
This revision is now accepted and ready to land.
Just some minor comments. Please address them prior to commit.
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10519
+ // 2 or 4 vsx registers.
+ if (VT == MVT::v256i1 || VT == MVT::v512i1) {
+assert((VT != MVT::v512i1 || Subtarget.hasMMA()) &&
Maybe we can do an early exit instead of this if stmt here
```
if (VT != MVT::v256i1 && VT != MVT::v512i1)
return Op;
assert(Subtarget.pairedVectorMemops()) &&
"Type unsupported without paired vector support");
```
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10522
+ "Type unsupported without MMA");
+assert((VT != MVT::v256i1 || Subtarget.pairedVectorMemops()) &&
+ "Type unsupported without paired vector support");
I believe the ck for v256i1 here is redundant cause MMA should also set
pairedVectorMemops
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10566
+ // underlying registers individually.
+ if (StoreVT == MVT::v256i1 || StoreVT == MVT::v512i1) {
+assert((StoreVT != MVT::v512i1 || Subtarget.hasMMA()) &&
same comment as above... early exit.
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[PATCH] D87804: [PowerPC][Power10] Implement Vector signed/unsigned __int128 overloads for the comparison builtins
lei added a comment. please fix the clang format issues. Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:365 + def int_ppc_altivec_vcmpequq : GCCBuiltin<"__builtin_altivec_vcmpequq">, + Intrinsic<[llvm_v1i128_ty], [llvm_v1i128_ty, llvm_v1i128_ty], + [IntrNoMem]>; nit: indentation Comment at: llvm/test/CodeGen/PowerPC/vec_cmpq.ll:14 +; CHECK-LABEL: v1si128_cmp: +; CHECK: vcmpequq 2, 2, 3 +} please add the check for end of function.. eg `// CHECK: ret <1 x i128>` Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D87804/new/ https://reviews.llvm.org/D87804 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D82609: [PowerPC] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang
lei accepted this revision as: lei. lei added a comment. This revision is now accepted and ready to land. LGTM Thx! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82609/new/ https://reviews.llvm.org/D82609 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D90799: [PowerPC] Add paired vector load and store builtins and intrinsics
lei added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:2658 + return false; +} + There's alot of nested `if`s, would it be possible to refactor to have some early exits instead? Comment at: llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll:2 +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -mcpu=pwr10 < %s | FileCheck %s + BE test? Can we add `-ppc-asm-full-reg-names` and update the checks to also ensure the reg info is accurate? Comment at: llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll:4 + +target datalayout = "e-m:e-i64:64-p:64:64-n32:64-v256:256:256-v512:512:512" + is this needed since we have the triple on the run line? Comment at: llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll:3 +; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs -disable-lsr \ +; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr10 < %s | FileCheck %s + BE test? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D90799/new/ https://reviews.llvm.org/D90799 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D102191: [PowerPC] Add clang option -m[no-]prefixed
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG9469ff15b779: [PowerPC] Add clang option -m[no-]prefixed
(authored by lei).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
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https://reviews.llvm.org/D102191
Files:
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/test/Driver/ppc-prefixed.cpp
Index: clang/test/Driver/ppc-prefixed.cpp
===
--- /dev/null
+++ clang/test/Driver/ppc-prefixed.cpp
@@ -0,0 +1,12 @@
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10
-mprefixed -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-PREFIXED %s
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10
-mno-prefixed -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOPREFIXED %s
+// CHECK-NOPREFIXED: "-target-feature" "-prefixed"
+// CHECK-PREFIXED: "-target-feature" "+prefixed"
+
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -emit-llvm -S
%s -o - | grep "attributes.*+prefix-instrs"
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -mprefixed
-emit-llvm -S %s -o - | grep "attributes.*+prefix-instrs"
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -mno-prefixed
-emit-llvm -S %s -o - | grep "attributes.*\-prefix-instrs"
+
+int main(int argc, char *argv[]) {
+ return 0;
+}
Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -73,6 +73,7 @@
bool PairedVectorMemops = false;
bool HasP10Vector = false;
bool HasPCRelativeMemops = false;
+ bool HasPrefixInstrs = false;
protected:
std::string ABI;
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -56,6 +56,8 @@
HasP10Vector = true;
} else if (Feature == "+pcrelative-memops") {
HasPCRelativeMemops = true;
+} else if (Feature == "+prefix-instrs") {
+ HasPrefixInstrs = true;
} else if (Feature == "+spe" || Feature == "+efpu2") {
HasSPE = true;
LongDoubleWidth = LongDoubleAlign = 64;
@@ -394,6 +396,7 @@
Features["mma"] = true;
Features["power10-vector"] = true;
Features["pcrelative-memops"] = true;
+ Features["prefix-instrs"] = true;
return;
}
@@ -419,6 +422,7 @@
.Case("paired-vector-memops", PairedVectorMemops)
.Case("power10-vector", HasP10Vector)
.Case("pcrelative-memops", HasPCRelativeMemops)
+ .Case("prefix-instrs", HasPrefixInstrs)
.Case("spe", HasSPE)
.Case("mma", HasMMA)
.Case("rop-protect", HasROPProtect)
@@ -451,6 +455,8 @@
Features["power8-vector"] = Features["power9-vector"] = true;
if (Name == "pcrel")
Features["pcrelative-memops"] = true;
+else if (Name == "prefixed")
+ Features["prefix-instrs"] = true;
else
Features[Name] = true;
} else {
@@ -471,6 +477,8 @@
Features["power10-vector"] = false;
if (Name == "pcrel")
Features["pcrelative-memops"] = false;
+else if (Name == "prefixed")
+ Features["prefix-instrs"] = false;
else
Features[Name] = false;
}
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -3254,6 +3254,8 @@
def mno_altivec : Flag<["-"], "mno-altivec">, Group;
def mpcrel: Flag<["-"], "mpcrel">, Group;
def mno_pcrel: Flag<["-"], "mno-pcrel">, Group;
+def mprefixed: Flag<["-"], "mprefixed">, Group;
+def mno_prefixed: Flag<["-"], "mno-prefixed">, Group;
def mspe : Flag<["-"], "mspe">, Group;
def mno_spe : Flag<["-"], "mno-spe">, Group;
def mefpu2 : Flag<["-"], "mefpu2">, Group;
Index: clang/test/Driver/ppc-prefixed.cpp
===
--- /dev/null
+++ clang/test/Driver/ppc-prefixed.cpp
@@ -0,0 +1,12 @@
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10 -mprefixed -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-PREFIXED %s
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10 -mno-prefixed -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOPREFIXED %s
+// CHECK-NOPREFIXED: "-target-feature" "-prefixed"
+// CHECK-PREFIXED: "-target-feature" "+prefixed"
+
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -emit-llvm -S %s -o - | grep "attributes.*+prefix-instrs"
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -mprefixed -emit-llvm -S %s -o - | grep "attributes.*+prefix-instrs"
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -mno-prefixed -emit-llvm -S %s -o - | grep
[PATCH] D95634: [PowerPC][Power10] Fix XXSPLI32DX not correctly exploiting specific cases
lei accepted this revision. lei added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95634/new/ https://reviews.llvm.org/D95634 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D109652: [PowerPC] Restrict various P10 options to P10 only.
lei added inline comments.
Comment at: clang/lib/Basic/Targets/PPC.cpp:566-569
+ if (llvm::find(FeaturesVec, "+pcrel") != FeaturesVec.end()) {
+Diags.Report(diag::err_opt_not_valid_without_opt) << "-mpcrel"
+ << "-mprefixed";
+ }
I think this need more thought:
```
$ clang -mcpu=pwr9 -mprefixed -mpcrel test.c -o test
error: option '-mpcrel' cannot be specified without '-mprefixed'
error: option '-mprefixed' cannot be specified without '-mcpu=pwr10'
$ clang -mcpu=pwr9 -mpcrel test.c -o test
error: option '-mpcrel' cannot be specified without '-mprefixed'
```
For this, the first err makes not sense since both `-mprefixed` and `-mpcrel`
is specified:
```
$ clang -mcpu=pwr9 -mprefixed -mpcrel test.c -o test
error: option '-mpcrel' cannot be specified without '-mprefixed'
error: option '-mprefixed' cannot be specified without '-mcpu=pwr10'
```
Shouldn't it just give:
```
$ clang -mcpu=pwr9 -mprefixed -mpcrel test.c -o test
error: option '-mpcrel' cannot be specified without '-mcpu=pwr10 -mprefixed'
```
For this:
```
$ clang -mcpu=pwr9 -mpcrel test.c -o test
error: option '-mpcrel' cannot be specified without '-mprefixed'
```
I think it's better if it says:
```
$ clang -mcpu=pwr9 -mpcrel test.c -o test
error: option '-mpcrel' cannot be specified without '-mcpu=pwr10 -mprefixed'
```
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[PATCH] D109996: [PowerPC] Fix signature of lxvp and stxvp builtins
lei accepted this revision as: lei. lei added a comment. LTGM Thx! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109996/new/ https://reviews.llvm.org/D109996 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D109780: [PowerPC] Add range check for vec_genpcvm builtins
lei accepted this revision. lei added a comment. LGTM. Thx! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109780/new/ https://reviews.llvm.org/D109780 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D108823: [PowerPC] Mark splat immediate instructions as rematerializable
lei accepted this revision as: lei. lei added a comment. This revision is now accepted and ready to land. LGTM Thx. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D108823/new/ https://reviews.llvm.org/D108823 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
