lei added inline comments.
================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13791
+ // Ensure that the load from the narrow width is being zero extended to i128.
+ if ((!ValidLDType) || (LD->getValueType(0) != MVT::i128) ||
+ (LD->getExtensionType() != ISD::ZEXTLOAD))
----------------
nit: don't need `()` aroud `!ValidLDType`
================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13797
+ // we are creating in order to pattern match to the appropriate instruction
+ // in the backend.
+ SDValue Width = DAG.getIntPtrConstant(MemoryType.getScalarSizeInBits(), dl);
----------------
I don't think we need to explicitly say this sine everything we do here is for
pattern matching to appropriate instructions in the backend...
================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13798
+ // in the backend.
+ SDValue Width = DAG.getIntPtrConstant(MemoryType.getScalarSizeInBits(), dl);
+ SDValue LoadOps[] = {LD->getChain(), LD->getBasePtr(), Width};
----------------
Can just merge this into the next line and remove this tmp value.
================
Comment at: llvm/test/CodeGen/PowerPC/p10-vsx-builtins.ll:6
+; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN: FileCheck %s
+
----------------
Please add tests for BE.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82502/new/
https://reviews.llvm.org/D82502
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