lei added a comment.
Please move encoding tests to `ppc64-encoding-ISA31.[txt|s]`.
================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13792
+ if ((LD->getValueType(0) != MVT::i128) ||
+ (LD->getExtensionType() != ISD::ZEXTLOAD) || (!ValidLDType))
+ return SDValue();
----------------
nit: check ValidLDType first:
```
if (! ValidLDType || (LD->getValueType(0) != MVT::i128) ||
(LD->getExtensionType() != ISD::ZEXTLOAD) ||)
```
================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.h:528
+ /// Allows utilization of the Load VSX Vector Rightmost Instructions.
+ LXVRZX
};
----------------
nit: This shouldn't matter to code gen, but it would be nice to have this
defined closer to other similar instructions. Maybe after `LXVD2X`?
================
Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:225
+def PPClxvrzx : SDNode<"PPCISD::LXVRZX", SDT_PPCLXVRZX,
+ [SDNPHasChain, SDNPMayLoad]>;
+
----------------
nit: indentation
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82502/new/
https://reviews.llvm.org/D82502
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
