[PATCH] D50043: [RISCV] RISC-V using -fuse-init-array by default

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 161990.
kito-cheng added a comment.
Herald added subscribers: jocewei, the_o, brucehoult, MartinMosbeck, mgrang, 
edward-jones, zzheng, niosHD, sabuasal, simoncook, johnrusso, rbar.

Changes:

- Add test.


https://reviews.llvm.org/D50043

Files:
  lib/Driver/ToolChains/Gnu.cpp
  test/Driver/riscv32-toolchain.c


Index: test/Driver/riscv32-toolchain.c
===
--- test/Driver/riscv32-toolchain.c
+++ test/Driver/riscv32-toolchain.c
@@ -9,6 +9,7 @@
 // RUN:   --sysroot=%S/Inputs/basic_riscv32_tree/riscv32-unknown-elf 2>&1 \
 // RUN:   | FileCheck -check-prefix=C-RV32-BAREMETAL-ILP32 %s
 
+// C-RV32-BAREMETAL-ILP32: "-fuse-init-array"
 // C-RV32-BAREMETAL-ILP32: 
"{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../bin{{/|}}riscv32-unknown-elf-ld"
 // C-RV32-BAREMETAL-ILP32: 
"--sysroot={{.*}}/Inputs/basic_riscv32_tree/riscv32-unknown-elf"
 // C-RV32-BAREMETAL-ILP32: 
"{{.*}}/Inputs/basic_riscv32_tree/riscv32-unknown-elf/lib{{/|}}crt0.o"
@@ -24,6 +25,7 @@
 // RUN:   --sysroot=%S/Inputs/basic_riscv32_tree/riscv32-unknown-elf 2>&1 \
 // RUN:   | FileCheck -check-prefix=CXX-RV32-BAREMETAL-ILP32 %s
 
+// CXX-RV32-BAREMETAL-ILP32: "-fuse-init-array"
 // CXX-RV32-BAREMETAL-ILP32: "-internal-isystem" 
"{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../riscv32-unknown-elf/include/c++{{/|}}8.0.1"
 // CXX-RV32-BAREMETAL-ILP32: 
"{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../bin{{/|}}riscv32-unknown-elf-ld"
 // CXX-RV32-BAREMETAL-ILP32: 
"--sysroot={{.*}}/Inputs/basic_riscv32_tree/riscv32-unknown-elf"
@@ -40,6 +42,7 @@
 // RUN:   --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \
 // RUN:   | FileCheck -check-prefix=C-RV32-LINUX-MULTI-ILP32 %s
 
+// C-RV32-LINUX-MULTI-ILP32: "-fuse-init-array"
 // C-RV32-LINUX-MULTI-ILP32: 
"{{.*}}/Inputs/multilib_riscv_linux_sdk/lib/gcc/riscv64-unknown-linux-gnu/7.2.0/../../../../riscv64-unknown-linux-gnu/bin{{/|}}ld"
 // C-RV32-LINUX-MULTI-ILP32: 
"--sysroot={{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot"
 // C-RV32-LINUX-MULTI-ILP32: "-m" "elf32lriscv"
@@ -55,6 +58,7 @@
 // RUN:   --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \
 // RUN:   | FileCheck -check-prefix=C-RV32-LINUX-MULTI-ILP32D %s
 
+// C-RV32-LINUX-MULTI-ILP32D: "-fuse-init-array"
 // C-RV32-LINUX-MULTI-ILP32D: 
"{{.*}}/Inputs/multilib_riscv_linux_sdk/lib/gcc/riscv64-unknown-linux-gnu/7.2.0/../../../../riscv64-unknown-linux-gnu/bin{{/|}}ld"
 // C-RV32-LINUX-MULTI-ILP32D: 
"--sysroot={{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot"
 // C-RV32-LINUX-MULTI-ILP32D: "-m" "elf32lriscv"
Index: lib/Driver/ToolChains/Gnu.cpp
===
--- lib/Driver/ToolChains/Gnu.cpp
+++ lib/Driver/ToolChains/Gnu.cpp
@@ -2554,7 +2554,9 @@
   getTriple().getOS() == llvm::Triple::NaCl ||
   (getTriple().getVendor() == llvm::Triple::MipsTechnologies &&
!getTriple().hasEnvironment()) ||
-  getTriple().getOS() == llvm::Triple::Solaris;
+  getTriple().getOS() == llvm::Triple::Solaris ||
+  getTriple().getArch() == llvm::Triple::riscv32 ||
+  getTriple().getArch() == llvm::Triple::riscv64;
 
   if (DriverArgs.hasFlag(options::OPT_fuse_init_array,
  options::OPT_fno_use_init_array, UseInitArrayDefault))


Index: test/Driver/riscv32-toolchain.c
===
--- test/Driver/riscv32-toolchain.c
+++ test/Driver/riscv32-toolchain.c
@@ -9,6 +9,7 @@
 // RUN:   --sysroot=%S/Inputs/basic_riscv32_tree/riscv32-unknown-elf 2>&1 \
 // RUN:   | FileCheck -check-prefix=C-RV32-BAREMETAL-ILP32 %s
 
+// C-RV32-BAREMETAL-ILP32: "-fuse-init-array"
 // C-RV32-BAREMETAL-ILP32: "{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../bin{{/|}}riscv32-unknown-elf-ld"
 // C-RV32-BAREMETAL-ILP32: "--sysroot={{.*}}/Inputs/basic_riscv32_tree/riscv32-unknown-elf"
 // C-RV32-BAREMETAL-ILP32: "{{.*}}/Inputs/basic_riscv32_tree/riscv32-unknown-elf/lib{{/|}}crt0.o"
@@ -24,6 +25,7 @@
 // RUN:   --sysroot=%S/Inputs/basic_riscv32_tree/riscv32-unknown-elf 2>&1 \
 // RUN:   | FileCheck -check-prefix=CXX-RV32-BAREMETAL-ILP32 %s
 
+// CXX-RV32-BAREMETAL-ILP32: "-fuse-init-array"
 // CXX-RV32-BAREMETAL-ILP32: "-internal-isystem" "{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../riscv32-unknown-elf/include/c++{{/|}}8.0.1"
 // CXX-RV32-BAREMETAL-ILP32: "{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../bin{{/|}}riscv32-unknown-elf-ld"
 // CXX-RV32-BAREMETAL-ILP32: "--sysroot={{.*}}/Inputs/basic_riscv32_tree/riscv32-unknown-elf"
@@ -40,6 +42,7 @@
 // RUN:   --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \
 // RUN:   | FileCheck -check-prefix=C-RV32-LINUX-MULTI-ILP32 %s
 
+// C-RV32-LINUX-MULTI-ILP32: "

[PATCH] D44888: [RISCV] Default enable linker relaxation and add -mrelax, -mno-relax flags

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added inline comments.



Comment at: lib/Driver/ToolChains/Arch/RISCV.cpp:130
+  // which may override the defaults.
+  handleTargetFeaturesGroup(Args, Features, 
options::OPT_m_riscv_Features_Group);
 }

This part should  move to the begin of the function, otherwise it never 
executed if `Exts` is empty string.



Repository:
  rL LLVM

https://reviews.llvm.org/D44888



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[PATCH] D46822: [RISCV] Add driver for riscv32-unknown-elf baremetal target

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.
Herald added subscribers: rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, 
jrtc27.

ping, Alex, could you commit that?


Repository:
  rC Clang

https://reviews.llvm.org/D46822



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[PATCH] D50043: [RISCV] RISC-V using -fuse-init-array by default

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng created this revision.
kito-cheng added reviewers: asb, apazos.
Herald added subscribers: cfe-commits, rkruppe, rogfer01, shiva0217, 
fedor.sergeev.

RISC-V target using -fuse-init-array even for bare-mental target.


Repository:
  rC Clang

https://reviews.llvm.org/D50043

Files:
  lib/Driver/ToolChains/Gnu.cpp


Index: lib/Driver/ToolChains/Gnu.cpp
===
--- lib/Driver/ToolChains/Gnu.cpp
+++ lib/Driver/ToolChains/Gnu.cpp
@@ -2553,7 +2553,9 @@
   getTriple().getOS() == llvm::Triple::NaCl ||
   (getTriple().getVendor() == llvm::Triple::MipsTechnologies &&
!getTriple().hasEnvironment()) ||
-  getTriple().getOS() == llvm::Triple::Solaris;
+  getTriple().getOS() == llvm::Triple::Solaris ||
+  getTriple().getArch() == llvm::Triple::riscv32 ||
+  getTriple().getArch() == llvm::Triple::riscv64;
 
   if (DriverArgs.hasFlag(options::OPT_fuse_init_array,
  options::OPT_fno_use_init_array, UseInitArrayDefault))


Index: lib/Driver/ToolChains/Gnu.cpp
===
--- lib/Driver/ToolChains/Gnu.cpp
+++ lib/Driver/ToolChains/Gnu.cpp
@@ -2553,7 +2553,9 @@
   getTriple().getOS() == llvm::Triple::NaCl ||
   (getTriple().getVendor() == llvm::Triple::MipsTechnologies &&
!getTriple().hasEnvironment()) ||
-  getTriple().getOS() == llvm::Triple::Solaris;
+  getTriple().getOS() == llvm::Triple::Solaris ||
+  getTriple().getArch() == llvm::Triple::riscv32 ||
+  getTriple().getArch() == llvm::Triple::riscv64;
 
   if (DriverArgs.hasFlag(options::OPT_fuse_init_array,
  options::OPT_fno_use_init_array, UseInitArrayDefault))
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[PATCH] D43105: [RISCV] Enable __int128_t and uint128_t through clang flag

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

Hi Eli:

We need that because compiler-rt implement 128 bits soft floating point with 
int128_t, and RISC-V need that but RV32 doesn't support int128_t, we know it's 
can be just return true to support that. but we don't want to bring any ABI 
contemptible issue between GCC and Clang/LLVM. Here is another direction is 
make GCC support int128_t for RV32, but it's hard to support that in GCC for 
all 32 bits target[1].

[1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=60846


Repository:
  rC Clang

https://reviews.llvm.org/D43105



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[PATCH] D43105: [RISCV] Enable __int128_t and uint128_t through clang flag

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

Hi Eli:

> but you want to make int128_t opt-in to avoid the possibility of someone 
> getting a link error trying to link code built with clang against libgcc.a?

Yes, that's the problem we want to avoid, and we actually get the problem if we 
built libc (newlib) with clang/llvm and used by GCC.


Repository:
  rC Clang

https://reviews.llvm.org/D43105



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[PATCH] D43105: [RISCV] Enable __int128_t and uint128_t through clang flag

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added inline comments.



Comment at: lib/Basic/Targets/RISCV.h:85
+  bool hasInt128Type(const LangOptions &Opts) const override {
+return Opts.UseInt128;
+  }

efriedma wrote:
> Maybe make this a cross-platform flag, rather than riscv-specific?
+1, then we can make all other 32 bits target to able easier support float128 
too :)


Repository:
  rC Clang

https://reviews.llvm.org/D43105



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[PATCH] D44189: [RISCV] Verify the input value of -march=

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng created this revision.
kito-cheng added reviewers: asb, apazos.
Herald added subscribers: cfe-commits, shiva0217, niosHD, sabuasal, 
jordy.potman.lists, simoncook, johnrusso, rbar.

This patch doing more check and verify the -march= string and will issue and 
error if it's a invalid combination.


Repository:
  rC Clang

https://reviews.llvm.org/D44189

Files:
  lib/Driver/ToolChains/Arch/RISCV.cpp
  test/Driver/riscv-arch.c

Index: test/Driver/riscv-arch.c
===
--- /dev/null
+++ test/Driver/riscv-arch.c
@@ -0,0 +1,23 @@
+// RUN: %clang -target riscv32-unknown-elf -march=rv32 -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32 %s
+// RV32: error: invalid arch name 'rv32'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32m -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32M %s
+// RV32M: error: invalid arch name 'rv32m'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32id -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32ID %s
+// RV32ID: error: invalid arch name 'rv32id'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32l -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32L %s
+// RV32L: error: invalid arch name 'rv32l'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64 -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64 %s
+// RV64: error: invalid arch name 'rv64'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64m -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64M %s
+// RV64M: error: invalid arch name 'rv64m'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64id -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64ID %s
+// RV64ID: error: invalid arch name 'rv64id'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64l -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64L %s
+// RV64L: error: invalid arch name 'rv64l'
Index: lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- lib/Driver/ToolChains/Arch/RISCV.cpp
+++ lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -23,33 +23,65 @@
 void riscv::getRISCVTargetFeatures(const Driver &D, const ArgList &Args,
std::vector &Features) {
   if (const Arg *A = Args.getLastArg(options::OPT_march_EQ)) {
-StringRef MArch = A->getValue();
-// TODO: handle rv64
-std::pair MArchSplit = StringRef(MArch).split("rv32");
-if (!MArchSplit.second.size())
+StringRef March = A->getValue();
+if (!(March.startswith("rv32") || March.startswith("rv64")) ||
+(March.size() < 5)) {
+  // ISA string must begin with rv32 or rv64.
+  D.Diag(diag::err_drv_invalid_arch_name) << March;
   return;
+}
+
+bool hasF = false, hasD = false;
+char baseline = March[4];
+
+switch (baseline) {
+case 'i':
+  break;
+case 'g':
+  Features.push_back("+m");
+  Features.push_back("+a");
+  Features.push_back("+f");
+  Features.push_back("+d");
+  hasF = true;
+  hasD = true;
+  break;
+default:
+  // First letter should be 'i' or 'g'.
+  D.Diag(diag::err_drv_invalid_arch_name) << March;
+  break;
+}
 
-for (char c : MArchSplit.second) {
+// Skip rvxxx
+StringRef Exts = March.substr(5);
+
+for (char c : Exts) {
   switch (c) {
-  case 'i':
-break;
   case 'm':
 Features.push_back("+m");
 break;
   case 'a':
 Features.push_back("+a");
 break;
   case 'f':
 Features.push_back("+f");
+hasF = true;
 break;
   case 'd':
 Features.push_back("+d");
+hasD = true;
 break;
   case 'c':
 Features.push_back("+c");
 break;
+  default:
+D.Diag(diag::err_drv_invalid_arch_name) << March;
+break;
   }
 }
+
+// Dependency check
+if (hasD && !hasF)
+  D.Diag(diag::err_drv_invalid_arch_name) << March;
   }
 }
 
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[PATCH] D44189: [RISCV] Verify the input value of -march=

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 137547.

Repository:
  rC Clang

https://reviews.llvm.org/D44189

Files:
  lib/Driver/ToolChains/Arch/RISCV.cpp
  test/Driver/riscv-arch.c

Index: test/Driver/riscv-arch.c
===
--- /dev/null
+++ test/Driver/riscv-arch.c
@@ -0,0 +1,29 @@
+// RUN: %clang -target riscv32-unknown-elf -march=rv32 -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32 %s
+// RV32: error: invalid arch name 'rv32'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32m -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32M %s
+// RV32M: error: invalid arch name 'rv32m'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32id -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32ID %s
+// RV32ID: error: invalid arch name 'rv32id'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32l -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32L %s
+// RV32L: error: invalid arch name 'rv32l'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imadf -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMADF %s
+// RV32IMADF: error: invalid arch name 'rv32imadf'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64 -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64 %s
+// RV64: error: invalid arch name 'rv64'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64m -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64M %s
+// RV64M: error: invalid arch name 'rv64m'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64id -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64ID %s
+// RV64ID: error: invalid arch name 'rv64id'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64l -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64L %s
+// RV64L: error: invalid arch name 'rv64l'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64imadf -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64IMADF %s
+// RV64IMADF: error: invalid arch name 'rv64imadf'
Index: lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- lib/Driver/ToolChains/Arch/RISCV.cpp
+++ lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -23,33 +23,82 @@
 void riscv::getRISCVTargetFeatures(const Driver &D, const ArgList &Args,
std::vector &Features) {
   if (const Arg *A = Args.getLastArg(options::OPT_march_EQ)) {
-StringRef MArch = A->getValue();
-// TODO: handle rv64
-std::pair MArchSplit = StringRef(MArch).split("rv32");
-if (!MArchSplit.second.size())
+StringRef March = A->getValue();
+if (!(March.startswith("rv32") || March.startswith("rv64")) ||
+(March.size() < 5)) {
+  // ISA string must begin with rv32 or rv64.
+  D.Diag(diag::err_drv_invalid_arch_name) << March;
   return;
+}
+
+// The canonical order specified in ISA manual.
+StringRef StdExts = "mafdc";
+
+bool hasF = false, hasD = false;
+char baseline = March[4];
+
+// TODO: Handle 'e' once backend supported.
+switch (baseline) {
+default:
+  // First letter should be 'e', 'i' or 'g'.
+  D.Diag(diag::err_drv_invalid_arch_name) << March;
+  return;
+case 'i':
+  break;
+case 'g':
+  // g = imafd
+  StdExts = StdExts.drop_front(4);
+  Features.push_back("+m");
+  Features.push_back("+a");
+  Features.push_back("+f");
+  Features.push_back("+d");
+  hasF = true;
+  hasD = true;
+  break;
+}
 
-for (char c : MArchSplit.second) {
+auto StdExtsItr = StdExts.begin();
+// Skip rvxxx
+StringRef Exts = March.substr(5);
+
+for (char c : Exts) {
+  // Check march is satisfied the canonical order.
+  while (StdExtsItr != StdExts.end() && *StdExtsItr != c)
+ ++StdExtsItr;
+
+  if (StdExtsItr == StdExts.end()) {
+D.Diag(diag::err_drv_invalid_arch_name) << March;
+return;
+  }
+
+  // The order is OK, then push it into features.
   switch (c) {
-  case 'i':
-break;
+  default:
+D.Diag(diag::err_drv_invalid_arch_name) << March;
+return;
   case 'm':
 Features.push_back("+m");
 break;
   case 'a':
 Features.push_back("+a");
 break;
   case 'f':
 Features.push_back("+f");
+hasF = true;
 break;
   case 'd':
 Features.push_back("+d");
+hasD = true;
 break;
   case 'c':
 Features.push_back("+c");
 break;
   }
 }
+
+// Dependency check
+if (hasD && !hasF)
+  D.Diag(diag::err_drv_invalid_arch_name) << March;
   }
 }
 
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[PATCH] D44189: [RISCV] Verify the input value of -march=

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng marked 2 inline comments as done.
kito-cheng added inline comments.



Comment at: lib/Driver/ToolChains/Arch/RISCV.cpp:48
+  break;
+default:
+  // First letter should be 'i' or 'g'.

apazos wrote:
> In the switch cases move default to first position.
Done :)



Comment at: lib/Driver/ToolChains/Arch/RISCV.cpp:60
   case 'm':
 Features.push_back("+m");
 break;

apazos wrote:
> So the subsequent features can appear in any order?
Yeah, here is a canonical order specified in ISA manual, I've check the order 
now.


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[PATCH] D44189: [RISCV] Verify the input value of -march=

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 137687.
kito-cheng added a comment.

This version only update variable name which changed in last version by 
accident.


https://reviews.llvm.org/D44189

Files:
  lib/Driver/ToolChains/Arch/RISCV.cpp
  test/Driver/riscv-arch.c

Index: test/Driver/riscv-arch.c
===
--- /dev/null
+++ test/Driver/riscv-arch.c
@@ -0,0 +1,29 @@
+// RUN: %clang -target riscv32-unknown-elf -march=rv32 -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32 %s
+// RV32: error: invalid arch name 'rv32'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32m -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32M %s
+// RV32M: error: invalid arch name 'rv32m'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32id -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32ID %s
+// RV32ID: error: invalid arch name 'rv32id'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32l -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32L %s
+// RV32L: error: invalid arch name 'rv32l'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imadf -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMADF %s
+// RV32IMADF: error: invalid arch name 'rv32imadf'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64 -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64 %s
+// RV64: error: invalid arch name 'rv64'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64m -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64M %s
+// RV64M: error: invalid arch name 'rv64m'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64id -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64ID %s
+// RV64ID: error: invalid arch name 'rv64id'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64l -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64L %s
+// RV64L: error: invalid arch name 'rv64l'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64imadf -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64IMADF %s
+// RV64IMADF: error: invalid arch name 'rv64imadf'
Index: lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- lib/Driver/ToolChains/Arch/RISCV.cpp
+++ lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -24,32 +24,81 @@
std::vector &Features) {
   if (const Arg *A = Args.getLastArg(options::OPT_march_EQ)) {
 StringRef MArch = A->getValue();
-// TODO: handle rv64
-std::pair MArchSplit = StringRef(MArch).split("rv32");
-if (!MArchSplit.second.size())
+if (!(MArch.startswith("rv32") || MArch.startswith("rv64")) ||
+(MArch.size() < 5)) {
+  // ISA string must begin with rv32 or rv64.
+  D.Diag(diag::err_drv_invalid_arch_name) << MArch;
   return;
+}
+
+// The canonical order specified in ISA manual.
+StringRef StdExts = "mafdc";
+
+bool hasF = false, hasD = false;
+char baseline = MArch[4];
+
+// TODO: Add 'e' once backend supported.
+switch (baseline) {
+default:
+  // First letter should be 'e', 'i' or 'g'.
+  D.Diag(diag::err_drv_invalid_arch_name) << MArch;
+  return;
+case 'i':
+  break;
+case 'g':
+  // g = imafd
+  StdExts = StdExts.drop_front(4);
+  Features.push_back("+m");
+  Features.push_back("+a");
+  Features.push_back("+f");
+  Features.push_back("+d");
+  hasF = true;
+  hasD = true;
+  break;
+}
 
-for (char c : MArchSplit.second) {
+auto StdExtsItr = StdExts.begin();
+// Skip rvxxx
+StringRef Exts = MArch.substr(5);
+
+for (char c : Exts) {
+  // Check march is satisfied the canonical order.
+  while (StdExtsItr != StdExts.end() && *StdExtsItr != c)
+ ++StdExtsItr;
+
+  if (StdExtsItr == StdExts.end()) {
+D.Diag(diag::err_drv_invalid_arch_name) << MArch;
+return;
+  }
+
+  // The order is OK, then push it into features.
   switch (c) {
-  case 'i':
-break;
+  default:
+D.Diag(diag::err_drv_invalid_arch_name) << MArch;
+return;
   case 'm':
 Features.push_back("+m");
 break;
   case 'a':
 Features.push_back("+a");
 break;
   case 'f':
 Features.push_back("+f");
+hasF = true;
 break;
   case 'd':
 Features.push_back("+d");
+hasD = true;
 break;
   case 'c':
 Features.push_back("+c");
 break;
   }
 }
+
+// Dependency check
+if (hasD && !hasF)
+  D.Diag(diag::err_drv_invalid_arch_name) << MArch;
   }
 }
 
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[PATCH] D44189: [RISCV] Verify the input value of -march=

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 137970.
kito-cheng added a comment.

Add test cases for the correct inputs.


https://reviews.llvm.org/D44189

Files:
  lib/Driver/ToolChains/Arch/RISCV.cpp
  test/Driver/riscv-arch.c

Index: test/Driver/riscv-arch.c
===
--- /dev/null
+++ test/Driver/riscv-arch.c
@@ -0,0 +1,77 @@
+// RUN: %clang -target riscv32-unknown-elf -march=rv32i -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32im -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ima -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imaf -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imafd -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ic -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imc -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imac -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imafc -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imafdc -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ia -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iaf -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iafd -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iac -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iafc -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iafdc -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32g -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32gc -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64i -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64im -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64ima -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64imaf -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64imafd -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64ic -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64imc -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64imac -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64imafc -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64imafdc -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64ia -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64iaf -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64iafd -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64iac -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64iafc -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64iafdc -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64g -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64gc -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// CHECK-NOT: error: invalid arch name '
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32 -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32 %s
+// RV32: error: invalid arch name 'rv32'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32m -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32M %s
+// RV32M: error: invalid arch name 'rv32m'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32id -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32ID %s
+// RV32ID: error: invalid arch name 'rv32id'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32l -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32L %s
+// RV32L: error: invalid arch name 'rv32l'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imadf -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMADF %s
+// RV32IMADF: error: invalid arch name 'rv32imadf'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64 -### %

[PATCH] D67409: [RISCV] enable LTO support, pass some options to linker.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added inline comments.



Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:387
+
+void riscv::addGoldOptions(const ToolChain &ToolChain,
+   const llvm::opt::ArgList &Args,

MaskRay wrote:
> gold doesn't support RISC-V, does it?
Gold doesn't support RISC-V , but ld.bfd supported same plugin API, so this 
made clang can run LTO with ld.bfd.


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[PATCH] D67508: [RISCV] support mutilib in baremetal environment

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added inline comments.



Comment at: clang/lib/Driver/ToolChains/Gnu.cpp:1548
+{M.gccSuffix(),
+ "/../../../../riscv64-unknown-elf/lib" + M.gccSuffix()});
+  });

It could be "riscv32-unknown-elf" other than "riscv64-unknown-elf".



Comment at: clang/lib/Driver/ToolChains/RISCVToolchain.cpp:129
+  }
+
   std::string Linker = getToolChain().GetProgramPath(getShortName());

This change seems like unrelated to multi-lib, could you split this change into 
new patch and add a test for that?



Comment at: clang/lib/Driver/ToolChains/RISCVToolchain.cpp:132
 
   if (D.isUsingLTO()) {
 assert(!Inputs.empty() && "Must have at least one input.");

This part will conflict when apply patch, you might generate patch with 
https://reviews.llvm.org/D67409, could you rebase the patch with current trunk?


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[PATCH] D71124: [RISCV] support clang driver to select cpu

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

Another proposal for -mcpu and -mtune:

Decoupling the -mcpu and -mtune option, -mcpu only accept concrete CPU, and 
-mtune for micro-arch/pipeline model, they accept different option set.

e.g.
-mcpu=sifive-e24 # Imply -march=rv32imafc -mtune=sifive-2-series
-mtune=sifive-2-series # no effect on arch
-mtune=rocket # no effect on arch

So -mcpu=rocket is invalid, since it's micro-arch/pipeline model only,
and -mtune=sifive-e24 is invalid too, because it's CPU not a micro-arch.


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[PATCH] D71124: [RISCV] support clang driver to select cpu

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added inline comments.



Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:478
   // 1. Explicit choices using `--with-abi=`
-  // 2. A default based on `--with-arch=`, if provided
-  // 3. A default based on the target triple's arch
+  // 2. A default based on arch
   //

I think it worth to keep this comment untouched, since it describing GCC's 
behavior.



Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:531
+  // 3. A default based on `--with-abi=`, if provided
+  // 4. A default based on the target triple's arch
   //

This part seems like is describing about GCC's behavior, so it should not 
change unless GCC changed?


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[PATCH] D132843: [RISCV] Ensure target features get passed to the LTO linker for RISC-V

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a subscriber: khchen.
kito-cheng added a comment.

This is dump from my mailbox, few month ago I written a offlist mail to 
describe about RISC-V LTO status:

---

LTO for RISC-V is really kind of a long long story. @khchen has been fighting 
for that for a long time, but he is no longer focusing on RISC-V.

A short summary is we still have issues with dealing with ABI, target features, 
and datalayout,

Datalayout is determined by target triple in most other targets, but RISC-V 
can't only use target triple to determine the datalayout.

So we need to keep ABI in somewhere and read that at LTO phase, the most ideal 
place is the module flags. We already did that[6], but that comes with a 
problem is it's too late to update datalayout when we start to read a module, 
because LLVM will use datalayout to infer some info like the alignment of 
loads[7], and that means we might re-read the whole LLVM IR again to get the IR 
with the right info, and that requires fixing multiple places in LLVM (see[2]. 
Still, I am not sure it's enough or not).

There is also an issue with how to store and determine the final LTO target 
features. For example, A object built with -march=rv64g and B object built with 
-march=rv64gc, so which arch should we use in the LTO code generation stage? 
see [5] for more discussion around this issue.

Currently, our downstream work-around is passing `-march` and `-mabi` into LTO 
by `-Wl,-plugin-opt=`, and ABI and ISA are determined by the linking stage to 
avoid (or work-around) the above issues.

Related open revision:
[1] https://reviews.llvm.org/D71387
[2] https://reviews.llvm.org/D72624 (This one is abandoned, but it
still necessary if we need store ABI info in module flags)
[3] https://reviews.llvm.org/D72245
[4] https://reviews.llvm.org/D102582
[5] https://reviews.llvm.org/D106347
[6] https://reviews.llvm.org/D72755

Other revision for ref.
---

[7] https://reviews.llvm.org/D78403


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[PATCH] D132843: [RISCV] Ensure target features get passed to the LTO linker for RISC-V

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

> I'm not sure how the issues with datalayout in particular end up being an 
> issue in practice.
>
> clang shouldn't be writing out object files without a datalayout.
> The code to infer alignment on load/store/etc. only exists for compatibility 
> with old bitcode/IR; current LLVM bitcode always marks up alignment for all 
> operations.
> Or do you mean something else when you say "datalayout"?

ilp32/ilp32f/ilp32d and ilp32e(D70401 ) having 
different data layout, so when we try to merge those stuffs will run into 
trouble, although I admit build object file with ilp32/ilp32f/ilp32d then LTO 
with ilp32e is generally a bad idea.

Another issue is the LLVM isn't compatible between different ABI, e.g. ilp32 
and ilp32f having different LLVM IR when passing a struct with a int and a 
float[2].

[1] https://reviews.llvm.org/D71387#1792169

---

> On other targets, the instruction set used is encoded at a per-function 
> level. So on x86, for example, you can have an "AVX" codepath and an "SSE" 
> codepath, and use runtime CPU detection to figure out which to use.

Give an example to explain what problem we have now and what option we have:

  $ clang -target riscv64-elf -flto a.c -o a.o -march=rv64gc# a.o 
build with -march=rv64gc
  $ clang -target riscv64-elf -flto b.c -o b.o -march=rv64g # b.o 
build with -march=rv64g
  $ clang -target riscv64-elf  a.o b.o -o a.out -flto -march=rv64gc_zba # and 
LTO phase use -march=rv64gc_zba, what target feature (or ISA extensions) should 
be used for all function 

Possible solution/results:

1. All functions in `a.o` and `b.o` using same target features during the first 
build stage, `-march=rv64gc` for a.o, `-march=rv64g` for `b.o`, and `-march` 
option given in LTO CodeGen stage is ignored, it only used for ELF attribute 
use (this revision).
2. All functions in `a.o` and `b.o` using same target features during the first 
build stage, `-march=rv64gc` for a.o, `-march=rv64g` for `b.o`, and deduced 
arch info from those `.o` for ELF attribute use (D106347 
), `-march`
3. All functions in `a.o` and `b.o` re-compile with `-march=rv64gc_zba` and ELF 
attribute use `rv64gc_zba`.

Option 1: Require user use right `-march` option during LTO stage, and might 
fill wrong/unexpected ELF attribute if give wrong `-march` or not even not 
given in LTO stage.
Option 2: Should be more ideal, but D106347  
seems no progress for a while.
Option 3: This option will break IFUNC usage.


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[PATCH] D132192: [RISCV] Add '32bit' feature to rv32 only builtins.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng accepted this revision.
kito-cheng added a comment.
This revision is now accepted and ready to land.

LGTM, and +1 for the error message improvement, but could be separated patch.


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[PATCH] D128726: [RISCV][NFC] Move static global variables into static variable in function.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng created this revision.
Herald added subscribers: sunshaoce, VincentWu, luke957, vkmr, frasercrmck, 
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jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
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Herald added a project: clang.

It's violate coding guideline in LLVM coding standard[1], and the
variable seems only used to cache the query result, so this could be
just a static variable within function.

[1] https://llvm.org/docs/CodingStandards.html#do-not-use-static-constructors


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Files:
  clang/lib/Support/RISCVVIntrinsicUtils.cpp


Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -31,10 +31,6 @@
 const PrototypeDescriptor PrototypeDescriptor::Vector =
 PrototypeDescriptor(BaseTypeModifier::Vector);
 
-// Concat BasicType, LMUL and Proto as key
-static std::unordered_map LegalTypes;
-static std::set IllegalTypes;
-
 
//===--===//
 // Type implementation
 
//===--===//
@@ -822,6 +818,9 @@
 
 Optional RVVType::computeType(BasicType BT, int Log2LMUL,
   PrototypeDescriptor Proto) {
+  // Concat BasicType, LMUL and Proto as key
+  static std::unordered_map LegalTypes;
+  static std::set IllegalTypes;
   uint64_t Idx = computeRVVTypeHashValue(BT, Log2LMUL, Proto);
   // Search first
   auto It = LegalTypes.find(Idx);


Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -31,10 +31,6 @@
 const PrototypeDescriptor PrototypeDescriptor::Vector =
 PrototypeDescriptor(BaseTypeModifier::Vector);
 
-// Concat BasicType, LMUL and Proto as key
-static std::unordered_map LegalTypes;
-static std::set IllegalTypes;
-
 //===--===//
 // Type implementation
 //===--===//
@@ -822,6 +818,9 @@
 
 Optional RVVType::computeType(BasicType BT, int Log2LMUL,
   PrototypeDescriptor Proto) {
+  // Concat BasicType, LMUL and Proto as key
+  static std::unordered_map LegalTypes;
+  static std::set IllegalTypes;
   uint64_t Idx = computeRVVTypeHashValue(BT, Log2LMUL, Proto);
   // Search first
   auto It = LegalTypes.find(Idx);
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[PATCH] D128726: [RISCV][NFC] Move static global variables into static variable in function.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

My understanding is the reason why no global variable is because 1. the 
initialization order and 2. might increase the launch time of programs, moving 
that into function scope could resolve both issue: 1. initialized in 
deterministic order[1], 2. Initialized that when the first time used.

[1] 
https://stackoverflow.com/questions/49856152/static-function-variable-initialization-order-in-the-same-function
[2] 
https://en.cppreference.com/w/cpp/language/storage_duration#Static_local_variables

- stackoverflow and cppreference might not formal source, but should be enough 
here.


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[PATCH] D128625: [RISCV][Driver] Fix baremetal `GCCInstallation` paths

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng accepted this revision.
kito-cheng added a comment.
This revision is now accepted and ready to land.

LGTM, `riscv*-unknown-unknown` match `riscv*-unknown-elf` sound make more sense 
than `riscv*-unknown-linux-gnu` :)


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[PATCH] D128726: [RISCV][NFC] Move static global variables into static variable in function.

[Kito Cheng via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG1b8cde9b6338: [RISCV][NFC] Move static global variables into 
static variable in function. (authored by kito-cheng).

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Files:
  clang/lib/Support/RISCVVIntrinsicUtils.cpp


Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -31,10 +31,6 @@
 const PrototypeDescriptor PrototypeDescriptor::Vector =
 PrototypeDescriptor(BaseTypeModifier::Vector);
 
-// Concat BasicType, LMUL and Proto as key
-static std::unordered_map LegalTypes;
-static std::set IllegalTypes;
-
 
//===--===//
 // Type implementation
 
//===--===//
@@ -822,6 +818,9 @@
 
 Optional RVVType::computeType(BasicType BT, int Log2LMUL,
   PrototypeDescriptor Proto) {
+  // Concat BasicType, LMUL and Proto as key
+  static std::unordered_map LegalTypes;
+  static std::set IllegalTypes;
   uint64_t Idx = computeRVVTypeHashValue(BT, Log2LMUL, Proto);
   // Search first
   auto It = LegalTypes.find(Idx);


Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -31,10 +31,6 @@
 const PrototypeDescriptor PrototypeDescriptor::Vector =
 PrototypeDescriptor(BaseTypeModifier::Vector);
 
-// Concat BasicType, LMUL and Proto as key
-static std::unordered_map LegalTypes;
-static std::set IllegalTypes;
-
 //===--===//
 // Type implementation
 //===--===//
@@ -822,6 +818,9 @@
 
 Optional RVVType::computeType(BasicType BT, int Log2LMUL,
   PrototypeDescriptor Proto) {
+  // Concat BasicType, LMUL and Proto as key
+  static std::unordered_map LegalTypes;
+  static std::set IllegalTypes;
   uint64_t Idx = computeRVVTypeHashValue(BT, Log2LMUL, Proto);
   // Search first
   auto It = LegalTypes.find(Idx);
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[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 441320.
kito-cheng added a comment.

Changes:

- Rebase
- Address @khchen's comment


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Files:
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TokenKinds.def
  clang/include/clang/Parse/Parser.h
  clang/include/clang/Sema/Sema.h
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Parse/ParsePragma.cpp
  clang/lib/Sema/CMakeLists.txt
  clang/lib/Sema/SemaLookup.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -110,6 +110,7 @@
 void EmitRVVHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltins(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltinCG(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitRVVBuiltinSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 
 void EmitCdeHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitCdeBuiltinDef(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -88,6 +88,7 @@
   GenRISCVVectorHeader,
   GenRISCVVectorBuiltins,
   GenRISCVVectorBuiltinCG,
+  GenRISCVVectorBuiltinSema,
   GenAttrDocs,
   GenDiagDocs,
   GenOptDocs,
@@ -243,6 +244,8 @@
"Generate riscv_vector_builtins.inc for clang"),
 clEnumValN(GenRISCVVectorBuiltinCG, "gen-riscv-vector-builtin-codegen",
"Generate riscv_vector_builtin_cg.inc for clang"),
+clEnumValN(GenRISCVVectorBuiltinSema, "gen-riscv-vector-builtin-sema",
+   "Generate riscv_vector_builtin_sema.inc for clang"),
 clEnumValN(GenAttrDocs, "gen-attr-docs",
"Generate attribute documentation"),
 clEnumValN(GenDiagDocs, "gen-diag-docs",
@@ -458,6 +461,9 @@
   case GenRISCVVectorBuiltinCG:
 EmitRVVBuiltinCG(Records, OS);
 break;
+  case GenRISCVVectorBuiltinSema:
+EmitRVVBuiltinSema(Records, OS);
+break;
   case GenAttrDocs:
 EmitClangAttrDocs(Records, OS);
 break;
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -20,6 +20,7 @@
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/StringSet.h"
+#include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
@@ -29,6 +30,59 @@
 using namespace clang::RISCV;
 
 namespace {
+struct SemaRecord {
+  // Intrinsic name, e.g. vadd_vv
+  std::string Name;
+
+  // Overloaded intrinsic name, could be empty if can be computed from Name
+  // e.g. vadd
+  std::string OverloadedName;
+
+  // Supported type, mask of BasicType
+  unsigned TypeRangeMask;
+
+  // Supported LMUL.
+  unsigned Log2LMULMask;
+
+  // Required extensions for this intrinsic.
+  unsigned RequiredExtension;
+
+  // Prototype for this intrinsic.
+  SmallVector Prototype;
+
+  // Prototype for masked intrinsic.
+  SmallVector MaskedPrototype;
+
+  // Suffix of intrinsic name.
+  SmallVector Suffix;
+
+  // Suffix of overloaded intrinsic name.
+  SmallVector OverloadedSuffix;
+
+  // Number of field, large than 1 if it's segment load/store.
+  unsigned NF;
+};
+
+// Compressed function signature table.
+class SemaSignatureTable {
+private:
+  std::vector SignatureTable;
+
+  void insert(ArrayRef Signature);
+
+public:
+  static constexpr unsigned INVALID_INDEX = (unsigned)-1;
+
+  // Create compressed hsignature table from SemaRecords.
+  void init(const std::vector &SemaRecords);
+
+  // Query the Signature, return INVALID_INDEX if not found.
+  unsigned getIndex(ArrayRef Signature);
+
+  /// Print signature table in RVVHeader Record to \p OS
+  void print(raw_ostream &OS);
+};
+
 class RVVEmitter {
 private:
   RecordKeeper &Records;
@@ -45,22 +99,22 @@
   /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
   void createCodeGen(raw_ostream &o);
 
+  /// Emit all the information needed by SemaRISCVVectorLookup.cpp.
+  /// We've large number of intrinsic function for RVV, creating a customized
+  /// could speed up the compilation time.
+  void createSema(raw_ostream &o);
+
 private:
-  /// Create all intrinsics and add them to \p Out
-  void createRVVIntrinsics(std::vector> &Out);
+  /// Create all intrin

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 441610.
kito-cheng marked 24 inline comments as done.
kito-cheng added a comment.

Changes:

- Address @craig.topper's comment
- Address @khchen's comment


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Files:
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TokenKinds.def
  clang/include/clang/Parse/Parser.h
  clang/include/clang/Sema/Sema.h
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Parse/ParsePragma.cpp
  clang/lib/Sema/CMakeLists.txt
  clang/lib/Sema/SemaLookup.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -110,6 +110,7 @@
 void EmitRVVHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltins(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltinCG(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitRVVBuiltinSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 
 void EmitCdeHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitCdeBuiltinDef(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -88,6 +88,7 @@
   GenRISCVVectorHeader,
   GenRISCVVectorBuiltins,
   GenRISCVVectorBuiltinCG,
+  GenRISCVVectorBuiltinSema,
   GenAttrDocs,
   GenDiagDocs,
   GenOptDocs,
@@ -243,6 +244,8 @@
"Generate riscv_vector_builtins.inc for clang"),
 clEnumValN(GenRISCVVectorBuiltinCG, "gen-riscv-vector-builtin-codegen",
"Generate riscv_vector_builtin_cg.inc for clang"),
+clEnumValN(GenRISCVVectorBuiltinSema, "gen-riscv-vector-builtin-sema",
+   "Generate riscv_vector_builtin_sema.inc for clang"),
 clEnumValN(GenAttrDocs, "gen-attr-docs",
"Generate attribute documentation"),
 clEnumValN(GenDiagDocs, "gen-diag-docs",
@@ -458,6 +461,9 @@
   case GenRISCVVectorBuiltinCG:
 EmitRVVBuiltinCG(Records, OS);
 break;
+  case GenRISCVVectorBuiltinSema:
+EmitRVVBuiltinSema(Records, OS);
+break;
   case GenAttrDocs:
 EmitClangAttrDocs(Records, OS);
 break;
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -20,6 +20,7 @@
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/StringSet.h"
+#include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
@@ -29,6 +30,59 @@
 using namespace clang::RISCV;
 
 namespace {
+struct SemaRecord {
+  // Intrinsic name, e.g. vadd_vv
+  std::string Name;
+
+  // Overloaded intrinsic name, could be empty if can be computed from Name
+  // e.g. vadd
+  std::string OverloadedName;
+
+  // Supported type, mask of BasicType
+  unsigned TypeRangeMask;
+
+  // Supported LMUL.
+  unsigned Log2LMULMask;
+
+  // Required extensions for this intrinsic.
+  unsigned RequiredExtension;
+
+  // Prototype for this intrinsic.
+  SmallVector Prototype;
+
+  // Prototype for masked intrinsic.
+  SmallVector MaskedPrototype;
+
+  // Suffix of intrinsic name.
+  SmallVector Suffix;
+
+  // Suffix of overloaded intrinsic name.
+  SmallVector OverloadedSuffix;
+
+  // Number of field, large than 1 if it's segment load/store.
+  unsigned NF;
+};
+
+// Compressed function signature table.
+class SemaSignatureTable {
+private:
+  std::vector SignatureTable;
+
+  void insert(ArrayRef Signature);
+
+public:
+  static constexpr unsigned INVALID_INDEX = (unsigned)-1;
+
+  // Create compressed signature table from SemaRecords.
+  void init(ArrayRef SemaRecords);
+
+  // Query the Signature, return INVALID_INDEX if not found.
+  unsigned getIndex(ArrayRef Signature);
+
+  /// Print signature table in RVVHeader Record to \p OS
+  void print(raw_ostream &OS);
+};
+
 class RVVEmitter {
 private:
   RecordKeeper &Records;
@@ -45,22 +99,22 @@
   /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
   void createCodeGen(raw_ostream &o);
 
+  /// Emit all the information needed by SemaRISCVVectorLookup.cpp.
+  /// We've large number of intrinsic function for RVV, creating a customized
+  /// could speed up the compilation time.
+  void createSema(raw_ostream &o);
+
 private:
-  /// Create all intrinsics and add them to \p Out
-  void crea

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added inline comments.



Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:114
   bool operator>(const PrototypeDescriptor &PD) const {
-return !(PD.PT <= PT && PD.VTM <= VTM && PD.TM <= TM);
+if (PD.PT != PT)
+  return PD.PT > PT;

craig.topper wrote:
> This can be written as
> 
> `return std::tie(PD.PT, PD.VTM, PD.TM) > std::tie(PT, VTM, TM);`
> 
> Though it's still surprising that PD is on the left. This is operator> but 
> the implementation looks more like operator<.
Rewrite as `operator>` and updated the use site, thank!



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:254
+  if (Signature.empty())
+return 0;
+

khchen wrote:
> Does it mean empty Signature always at 0?
> If yes,  maybe we could check the table from Index = 1 in below loop?
Actually empty signature could be indicate into any index, we have hold length 
when we emit the index. 

Add comment to mention that.


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[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng marked an inline comment as done.
kito-cheng added a comment.

Oh, have one comment not address yet


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[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 441684.
kito-cheng added a comment.

Changes:

- Address @craig.topper's comment
  - Introduce RISCVIntrinsicManager.h and let it become member of Sema, that 
make sure the it won't outlive than Sema.


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Files:
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TokenKinds.def
  clang/include/clang/Parse/Parser.h
  clang/include/clang/Sema/RISCVIntrinsicManager.h
  clang/include/clang/Sema/Sema.h
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Parse/ParsePragma.cpp
  clang/lib/Sema/CMakeLists.txt
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaLookup.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -110,6 +110,7 @@
 void EmitRVVHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltins(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltinCG(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitRVVBuiltinSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 
 void EmitCdeHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitCdeBuiltinDef(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -88,6 +88,7 @@
   GenRISCVVectorHeader,
   GenRISCVVectorBuiltins,
   GenRISCVVectorBuiltinCG,
+  GenRISCVVectorBuiltinSema,
   GenAttrDocs,
   GenDiagDocs,
   GenOptDocs,
@@ -243,6 +244,8 @@
"Generate riscv_vector_builtins.inc for clang"),
 clEnumValN(GenRISCVVectorBuiltinCG, "gen-riscv-vector-builtin-codegen",
"Generate riscv_vector_builtin_cg.inc for clang"),
+clEnumValN(GenRISCVVectorBuiltinSema, "gen-riscv-vector-builtin-sema",
+   "Generate riscv_vector_builtin_sema.inc for clang"),
 clEnumValN(GenAttrDocs, "gen-attr-docs",
"Generate attribute documentation"),
 clEnumValN(GenDiagDocs, "gen-diag-docs",
@@ -458,6 +461,9 @@
   case GenRISCVVectorBuiltinCG:
 EmitRVVBuiltinCG(Records, OS);
 break;
+  case GenRISCVVectorBuiltinSema:
+EmitRVVBuiltinSema(Records, OS);
+break;
   case GenAttrDocs:
 EmitClangAttrDocs(Records, OS);
 break;
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -20,6 +20,7 @@
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/StringSet.h"
+#include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
@@ -29,6 +30,59 @@
 using namespace clang::RISCV;
 
 namespace {
+struct SemaRecord {
+  // Intrinsic name, e.g. vadd_vv
+  std::string Name;
+
+  // Overloaded intrinsic name, could be empty if can be computed from Name
+  // e.g. vadd
+  std::string OverloadedName;
+
+  // Supported type, mask of BasicType
+  unsigned TypeRangeMask;
+
+  // Supported LMUL.
+  unsigned Log2LMULMask;
+
+  // Required extensions for this intrinsic.
+  unsigned RequiredExtension;
+
+  // Prototype for this intrinsic.
+  SmallVector Prototype;
+
+  // Prototype for masked intrinsic.
+  SmallVector MaskedPrototype;
+
+  // Suffix of intrinsic name.
+  SmallVector Suffix;
+
+  // Suffix of overloaded intrinsic name.
+  SmallVector OverloadedSuffix;
+
+  // Number of field, large than 1 if it's segment load/store.
+  unsigned NF;
+};
+
+// Compressed function signature table.
+class SemaSignatureTable {
+private:
+  std::vector SignatureTable;
+
+  void insert(ArrayRef Signature);
+
+public:
+  static constexpr unsigned INVALID_INDEX = (unsigned)-1;
+
+  // Create compressed signature table from SemaRecords.
+  void init(ArrayRef SemaRecords);
+
+  // Query the Signature, return INVALID_INDEX if not found.
+  unsigned getIndex(ArrayRef Signature);
+
+  /// Print signature table in RVVHeader Record to \p OS
+  void print(raw_ostream &OS);
+};
+
 class RVVEmitter {
 private:
   RecordKeeper &Records;
@@ -45,22 +99,22 @@
   /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
   void createCodeGen(raw_ostream &o);
 
+  /// Emit all the information needed by SemaRISCVVectorLookup.cpp.
+  /// We've large number of intrinsic function for RVV, creating a customized
+  /// could speed up the compila

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 441692.
kito-cheng marked 18 inline comments as done.
kito-cheng added a comment.

Changes:

- Address @aaron.ballman’s comment
  - Add 2 new testcase:
- riscv-bad-intrnisic-pragma.c
- riscv-intrnisic-pragma.c


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Files:
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TokenKinds.def
  clang/include/clang/Parse/Parser.h
  clang/include/clang/Sema/RISCVIntrinsicManager.h
  clang/include/clang/Sema/Sema.h
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Parse/ParsePragma.cpp
  clang/lib/Sema/CMakeLists.txt
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaLookup.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/test/Sema/riscv-bad-intrnisic-pragma.c
  clang/test/Sema/riscv-intrnisic-pragma.c
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -110,6 +110,7 @@
 void EmitRVVHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltins(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltinCG(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitRVVBuiltinSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 
 void EmitCdeHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitCdeBuiltinDef(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -88,6 +88,7 @@
   GenRISCVVectorHeader,
   GenRISCVVectorBuiltins,
   GenRISCVVectorBuiltinCG,
+  GenRISCVVectorBuiltinSema,
   GenAttrDocs,
   GenDiagDocs,
   GenOptDocs,
@@ -243,6 +244,8 @@
"Generate riscv_vector_builtins.inc for clang"),
 clEnumValN(GenRISCVVectorBuiltinCG, "gen-riscv-vector-builtin-codegen",
"Generate riscv_vector_builtin_cg.inc for clang"),
+clEnumValN(GenRISCVVectorBuiltinSema, "gen-riscv-vector-builtin-sema",
+   "Generate riscv_vector_builtin_sema.inc for clang"),
 clEnumValN(GenAttrDocs, "gen-attr-docs",
"Generate attribute documentation"),
 clEnumValN(GenDiagDocs, "gen-diag-docs",
@@ -458,6 +461,9 @@
   case GenRISCVVectorBuiltinCG:
 EmitRVVBuiltinCG(Records, OS);
 break;
+  case GenRISCVVectorBuiltinSema:
+EmitRVVBuiltinSema(Records, OS);
+break;
   case GenAttrDocs:
 EmitClangAttrDocs(Records, OS);
 break;
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -20,6 +20,7 @@
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/StringSet.h"
+#include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
@@ -29,6 +30,59 @@
 using namespace clang::RISCV;
 
 namespace {
+struct SemaRecord {
+  // Intrinsic name, e.g. vadd_vv
+  std::string Name;
+
+  // Overloaded intrinsic name, could be empty if can be computed from Name
+  // e.g. vadd
+  std::string OverloadedName;
+
+  // Supported type, mask of BasicType.
+  unsigned TypeRangeMask;
+
+  // Supported LMUL.
+  unsigned Log2LMULMask;
+
+  // Required extensions for this intrinsic.
+  unsigned RequiredExtension;
+
+  // Prototype for this intrinsic.
+  SmallVector Prototype;
+
+  // Prototype for masked intrinsic.
+  SmallVector MaskedPrototype;
+
+  // Suffix of intrinsic name.
+  SmallVector Suffix;
+
+  // Suffix of overloaded intrinsic name.
+  SmallVector OverloadedSuffix;
+
+  // Number of field, large than 1 if it's segment load/store.
+  unsigned NF;
+};
+
+// Compressed function signature table.
+class SemaSignatureTable {
+private:
+  std::vector SignatureTable;
+
+  void insert(ArrayRef Signature);
+
+public:
+  static constexpr unsigned INVALID_INDEX = ~0U;
+
+  // Create compressed signature table from SemaRecords.
+  void init(ArrayRef SemaRecords);
+
+  // Query the Signature, return INVALID_INDEX if not found.
+  unsigned getIndex(ArrayRef Signature);
+
+  /// Print signature table in RVVHeader Record to \p OS
+  void print(raw_ostream &OS);
+};
+
 class RVVEmitter {
 private:
   RecordKeeper &Records;
@@ -45,22 +99,22 @@
   /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
   void createCodeGen(raw_ostream &o);
 
+  /// Emit all the information needed by SemaRISCVVectorLookup.cpp.
+  /// We've 

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added inline comments.



Comment at: clang/lib/Parse/ParsePragma.cpp:3963
+<< PP.getSpelling(Tok) << "riscv" << /*Expected=*/true << 
"'intrinsic'";
+return;
+  }

aaron.ballman wrote:
> It's fine to warn on this, but then you need to eat tokens until the end of 
> directive is found so that parsing recovery is correct. e.g.,
> ```
> #pragma clang riscv int i = 12;
> ```
> See `HandlePragmaAttribute()` for an example (though you'll look for `eod` 
> instead of `eof`).
Seems like it already work correctly, and I saw other HandlePragma also just 
return? I add a testcase to make sure it work.



Comment at: clang/lib/Sema/SemaRISCVVectorLookup.cpp:100
+switch (Type->getElementBitwidth()) {
+case 64:
+  QT = Context.DoubleTy;

aaron.ballman wrote:
> I almost hate to ask, but... `long double`? Any of the 16-bit float types?
Have 16 bit floating below, but we don't support long double in our intrinsic 
for now, add an assertion to make sure.



Comment at: clang/lib/Sema/SemaRISCVVectorLookup.cpp:121
+  // Transform the type to a pointer as the last step, if necessary.
+  if (Type->isPointer())
+QT = Context.getPointerType(QT);

aaron.ballman wrote:
> Double-checking -- do you have to care about references as well?
We don't have any references type in argument type, so we don't care about that.


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[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 442025.
kito-cheng marked 9 inline comments as done.
kito-cheng added a comment.

Changes:

- Address @frasercrmck's comment


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Files:
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TokenKinds.def
  clang/include/clang/Parse/Parser.h
  clang/include/clang/Sema/RISCVIntrinsicManager.h
  clang/include/clang/Sema/Sema.h
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Parse/ParsePragma.cpp
  clang/lib/Sema/CMakeLists.txt
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaLookup.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/test/Sema/riscv-bad-intrnisic-pragma.c
  clang/test/Sema/riscv-intrnisic-pragma.c
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -110,6 +110,7 @@
 void EmitRVVHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltins(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltinCG(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitRVVBuiltinSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 
 void EmitCdeHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitCdeBuiltinDef(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -88,6 +88,7 @@
   GenRISCVVectorHeader,
   GenRISCVVectorBuiltins,
   GenRISCVVectorBuiltinCG,
+  GenRISCVVectorBuiltinSema,
   GenAttrDocs,
   GenDiagDocs,
   GenOptDocs,
@@ -243,6 +244,8 @@
"Generate riscv_vector_builtins.inc for clang"),
 clEnumValN(GenRISCVVectorBuiltinCG, "gen-riscv-vector-builtin-codegen",
"Generate riscv_vector_builtin_cg.inc for clang"),
+clEnumValN(GenRISCVVectorBuiltinSema, "gen-riscv-vector-builtin-sema",
+   "Generate riscv_vector_builtin_sema.inc for clang"),
 clEnumValN(GenAttrDocs, "gen-attr-docs",
"Generate attribute documentation"),
 clEnumValN(GenDiagDocs, "gen-diag-docs",
@@ -458,6 +461,9 @@
   case GenRISCVVectorBuiltinCG:
 EmitRVVBuiltinCG(Records, OS);
 break;
+  case GenRISCVVectorBuiltinSema:
+EmitRVVBuiltinSema(Records, OS);
+break;
   case GenAttrDocs:
 EmitClangAttrDocs(Records, OS);
 break;
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -20,6 +20,7 @@
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/StringSet.h"
+#include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
@@ -29,6 +30,59 @@
 using namespace clang::RISCV;
 
 namespace {
+struct SemaRecord {
+  // Intrinsic name, e.g. vadd_vv
+  std::string Name;
+
+  // Overloaded intrinsic name, could be empty if can be computed from Name
+  // e.g. vadd
+  std::string OverloadedName;
+
+  // Supported type, mask of BasicType.
+  unsigned TypeRangeMask;
+
+  // Supported LMUL.
+  unsigned Log2LMULMask;
+
+  // Required extensions for this intrinsic.
+  unsigned RequiredExtensions;
+
+  // Prototype for this intrinsic.
+  SmallVector Prototype;
+
+  // Prototype for masked intrinsic.
+  SmallVector MaskedPrototype;
+
+  // Suffix of intrinsic name.
+  SmallVector Suffix;
+
+  // Suffix of overloaded intrinsic name.
+  SmallVector OverloadedSuffix;
+
+  // Number of field, large than 1 if it's segment load/store.
+  unsigned NF;
+};
+
+// Compressed function signature table.
+class SemaSignatureTable {
+private:
+  std::vector SignatureTable;
+
+  void insert(ArrayRef Signature);
+
+public:
+  static constexpr unsigned INVALID_INDEX = ~0U;
+
+  // Create compressed signature table from SemaRecords.
+  void init(ArrayRef SemaRecords);
+
+  // Query the Signature, return INVALID_INDEX if not found.
+  unsigned getIndex(ArrayRef Signature);
+
+  /// Print signature table in RVVHeader Record to \p OS
+  void print(raw_ostream &OS);
+};
+
 class RVVEmitter {
 private:
   RecordKeeper &Records;
@@ -45,22 +99,22 @@
   /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
   void createCodeGen(raw_ostream &o);
 
+  /// Emit all the information needed by SemaRISCVVectorLookup.cpp.
+  /// We've large number of intrinsic function for RVV, creating a customized
+  /// could speed up the 

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added inline comments.



Comment at: clang/lib/Sema/SemaRISCVVectorLookup.cpp:100
+switch (Type->getElementBitwidth()) {
+case 64:
+  QT = Context.DoubleTy;

aaron.ballman wrote:
> kito-cheng wrote:
> > aaron.ballman wrote:
> > > I almost hate to ask, but... `long double`? Any of the 16-bit float types?
> > Have 16 bit floating below, but we don't support long double in our 
> > intrinsic for now, add an assertion to make sure.
> Very glad to hear about `long double`, but I was unclear on the 16-bit float, 
> I was more wondering if you need to differentiate between `Float16Ty`, 
> `BFloat16Ty`, and `HalfTy` since those will all have the same bit widths but 
> be different types.
RISC-V vector intrinsic only support `_Float16`(`Float16Ty`) for now, 
`__fp16`(`HalfTy`, `half` in OpenCL) won't support, `BFloat16Ty` will be 
another `ScalarTypeKind` like `ScalarTypeKind::BFloat`, we didn't add yet since 
we don't have any `bfloat16` instruction  in RISC-V extension now.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:637
+Out.emplace_back(Record);
+Out.back().Name = SR.Name.c_str();
+Out.back().OverloadedName = SR.OverloadedName.c_str();

frasercrmck wrote:
> I assume the compiler's able to avoid recomputing `Out.back()` multiple 
> times? We could take a reference to `Out.back()` and use that, just in case?
Checked code gen with following program, got almost same code gen:

```
#include 
struct X{
int a;
int b;
int c;
};

#ifdef BACK
void foo(std::vector &Out){
X x;
Out.emplace_back(x);
Out.back().a =12;
Out.back().b =23;
Out.back().c =30;
}
#else
void foo2(std::vector &Out){
Out.emplace_back(X());
X &x = Out.back();
x.a =12;
x.b =23;
x.c =30;
}
#endif
```

But I think later one might be more readable, let me tweak that.


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[PATCH] D129043: [RISCV][Clang] Teach RISCVEmitter to generate BitCast for pointer operands.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng accepted this revision.
kito-cheng added a comment.
This revision is now accepted and ready to land.

LGTM, thanks for clean this up :)


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[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 442429.
kito-cheng added a comment.

Changes:

- Less invasive way to fix this issue.


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Files:
  llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
  llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir


Index: llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir
===
--- llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir
+++ llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir
@@ -33,7 +33,7 @@
 ; CHECK-NEXT: renamable $x11 = ADDI $x0, 1
 ; CHECK-NEXT: $x12 = ADDI $x10, 768
 ; CHECK-NEXT: SD killed renamable $x11, $x12, 32 :: (store (s64) into 
%ir.1)
-; CHECK-NEXT: SD $x12, $x12, 40 :: (store (s64) into %ir.2)
+; CHECK-NEXT: SD renamable $x10, $x12, 40 :: (store (s64) into %ir.2)
 ; CHECK-NEXT: renamable $x11 = ADDI $x0, 2
 ; CHECK-NEXT: SD killed renamable $x11, killed $x12, 48 :: (store (s64) 
into %ir.3)
 ; CHECK-NEXT: PseudoRET
Index: llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
===
--- llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+++ llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
@@ -293,8 +293,15 @@
   assert((isCompressibleLoad(MI) || isCompressibleStore(MI)) &&
  "Unsupported instruction for this optimization.");
 
+  int SkipN = 0;
+
+  // Skip first operand for store instruction, it's operand for store value,
+  // it's unsafe to rename if offset is non-zero.
+  if (isCompressibleStore(MI) && OldRegImm.Imm != 0)
+SkipN = 1;
+
   // Update registers
-  for (MachineOperand &MO : MI.operands())
+  for (MachineOperand &MO : drop_begin(MI.operands(), SkipN))
 if (MO.isReg() && MO.getReg() == OldRegImm.Reg) {
   // Do not update operands that define the old register.
   //


Index: llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir
===
--- llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir
+++ llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir
@@ -33,7 +33,7 @@
 ; CHECK-NEXT: renamable $x11 = ADDI $x0, 1
 ; CHECK-NEXT: $x12 = ADDI $x10, 768
 ; CHECK-NEXT: SD killed renamable $x11, $x12, 32 :: (store (s64) into %ir.1)
-; CHECK-NEXT: SD $x12, $x12, 40 :: (store (s64) into %ir.2)
+; CHECK-NEXT: SD renamable $x10, $x12, 40 :: (store (s64) into %ir.2)
 ; CHECK-NEXT: renamable $x11 = ADDI $x0, 2
 ; CHECK-NEXT: SD killed renamable $x11, killed $x12, 48 :: (store (s64) into %ir.3)
 ; CHECK-NEXT: PseudoRET
Index: llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
===
--- llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+++ llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
@@ -293,8 +293,15 @@
   assert((isCompressibleLoad(MI) || isCompressibleStore(MI)) &&
  "Unsupported instruction for this optimization.");
 
+  int SkipN = 0;
+
+  // Skip first operand for store instruction, it's operand for store value,
+  // it's unsafe to rename if offset is non-zero.
+  if (isCompressibleStore(MI) && OldRegImm.Imm != 0)
+SkipN = 1;
+
   // Update registers
-  for (MachineOperand &MO : MI.operands())
+  for (MachineOperand &MO : drop_begin(MI.operands(), SkipN))
 if (MO.isReg() && MO.getReg() == OldRegImm.Reg) {
   // Do not update operands that define the old register.
   //
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[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 442431.
kito-cheng added a comment.

Changes:

Restore the patch, I just accidentally updated wrong revision here...


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Files:
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TokenKinds.def
  clang/include/clang/Parse/Parser.h
  clang/include/clang/Sema/RISCVIntrinsicManager.h
  clang/include/clang/Sema/Sema.h
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Parse/ParsePragma.cpp
  clang/lib/Sema/CMakeLists.txt
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaLookup.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/test/Sema/riscv-bad-intrnisic-pragma.c
  clang/test/Sema/riscv-intrnisic-pragma.c
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -110,6 +110,7 @@
 void EmitRVVHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltins(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltinCG(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitRVVBuiltinSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 
 void EmitCdeHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitCdeBuiltinDef(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -88,6 +88,7 @@
   GenRISCVVectorHeader,
   GenRISCVVectorBuiltins,
   GenRISCVVectorBuiltinCG,
+  GenRISCVVectorBuiltinSema,
   GenAttrDocs,
   GenDiagDocs,
   GenOptDocs,
@@ -243,6 +244,8 @@
"Generate riscv_vector_builtins.inc for clang"),
 clEnumValN(GenRISCVVectorBuiltinCG, "gen-riscv-vector-builtin-codegen",
"Generate riscv_vector_builtin_cg.inc for clang"),
+clEnumValN(GenRISCVVectorBuiltinSema, "gen-riscv-vector-builtin-sema",
+   "Generate riscv_vector_builtin_sema.inc for clang"),
 clEnumValN(GenAttrDocs, "gen-attr-docs",
"Generate attribute documentation"),
 clEnumValN(GenDiagDocs, "gen-diag-docs",
@@ -458,6 +461,9 @@
   case GenRISCVVectorBuiltinCG:
 EmitRVVBuiltinCG(Records, OS);
 break;
+  case GenRISCVVectorBuiltinSema:
+EmitRVVBuiltinSema(Records, OS);
+break;
   case GenAttrDocs:
 EmitClangAttrDocs(Records, OS);
 break;
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -20,6 +20,7 @@
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/StringSet.h"
+#include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
@@ -29,6 +30,59 @@
 using namespace clang::RISCV;
 
 namespace {
+struct SemaRecord {
+  // Intrinsic name, e.g. vadd_vv
+  std::string Name;
+
+  // Overloaded intrinsic name, could be empty if can be computed from Name
+  // e.g. vadd
+  std::string OverloadedName;
+
+  // Supported type, mask of BasicType.
+  unsigned TypeRangeMask;
+
+  // Supported LMUL.
+  unsigned Log2LMULMask;
+
+  // Required extensions for this intrinsic.
+  unsigned RequiredExtensions;
+
+  // Prototype for this intrinsic.
+  SmallVector Prototype;
+
+  // Prototype for masked intrinsic.
+  SmallVector MaskedPrototype;
+
+  // Suffix of intrinsic name.
+  SmallVector Suffix;
+
+  // Suffix of overloaded intrinsic name.
+  SmallVector OverloadedSuffix;
+
+  // Number of field, large than 1 if it's segment load/store.
+  unsigned NF;
+};
+
+// Compressed function signature table.
+class SemaSignatureTable {
+private:
+  std::vector SignatureTable;
+
+  void insert(ArrayRef Signature);
+
+public:
+  static constexpr unsigned INVALID_INDEX = ~0U;
+
+  // Create compressed signature table from SemaRecords.
+  void init(ArrayRef SemaRecords);
+
+  // Query the Signature, return INVALID_INDEX if not found.
+  unsigned getIndex(ArrayRef Signature);
+
+  /// Print signature table in RVVHeader Record to \p OS
+  void print(raw_ostream &OS);
+};
+
 class RVVEmitter {
 private:
   RecordKeeper &Records;
@@ -45,22 +99,22 @@
   /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
   void createCodeGen(raw_ostream &o);
 
+  /// Emit all the information needed by SemaRISCVVectorLookup.cpp.
+  /// We've large number of intrinsic function for RVV, creating a customized
+  /// could speed up the compilat

[PATCH] D121984: [RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support

[Kito Cheng via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGad57e10dbca2: [RISCV][NFC] Moving RVV intrinsic type related 
util to llvm/Support (authored by kito-cheng).

Changed prior to commit:
  https://reviews.llvm.org/D121984?vs=416414&id=418496#toc

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Files:
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/include/llvm/Support/RISCVVIntrinsicUtils.h
  llvm/lib/Support/CMakeLists.txt
  llvm/lib/Support/RISCVVIntrinsicUtils.cpp

Index: llvm/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- /dev/null
+++ llvm/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -0,0 +1,668 @@
+//===- RISCVVIntrinsicUtils.cpp - RISC-V Vector Intrinsic Utils -*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "llvm/Support/RISCVVIntrinsicUtils.h"
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/SmallSet.h"
+#include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/StringMap.h"
+#include "llvm/ADT/StringSet.h"
+#include "llvm/ADT/Twine.h"
+#include "llvm/TableGen/Error.h"
+#include "llvm/TableGen/Record.h"
+#include 
+
+namespace llvm {
+namespace RISCV {
+
+//===--===//
+// Type implementation
+//===--===//
+
+LMULType::LMULType(int NewLog2LMUL) {
+  // Check Log2LMUL is -3, -2, -1, 0, 1, 2, 3
+  assert(NewLog2LMUL <= 3 && NewLog2LMUL >= -3 && "Bad LMUL number!");
+  Log2LMUL = NewLog2LMUL;
+}
+
+std::string LMULType::str() const {
+  if (Log2LMUL < 0)
+return "mf" + utostr(1ULL << (-Log2LMUL));
+  return "m" + utostr(1ULL << Log2LMUL);
+}
+
+VScaleVal LMULType::getScale(unsigned ElementBitwidth) const {
+  int Log2ScaleResult = 0;
+  switch (ElementBitwidth) {
+  default:
+break;
+  case 8:
+Log2ScaleResult = Log2LMUL + 3;
+break;
+  case 16:
+Log2ScaleResult = Log2LMUL + 2;
+break;
+  case 32:
+Log2ScaleResult = Log2LMUL + 1;
+break;
+  case 64:
+Log2ScaleResult = Log2LMUL;
+break;
+  }
+  // Illegal vscale result would be less than 1
+  if (Log2ScaleResult < 0)
+return llvm::None;
+  return 1 << Log2ScaleResult;
+}
+
+void LMULType::MulLog2LMUL(int log2LMUL) { Log2LMUL += log2LMUL; }
+
+LMULType &LMULType::operator*=(uint32_t RHS) {
+  assert(isPowerOf2_32(RHS));
+  this->Log2LMUL = this->Log2LMUL + Log2_32(RHS);
+  return *this;
+}
+
+RVVType::RVVType(BasicType BT, int Log2LMUL, StringRef prototype)
+: BT(BT), LMUL(LMULType(Log2LMUL)) {
+  applyBasicType();
+  applyModifier(prototype);
+  Valid = verifyType();
+  if (Valid) {
+initBuiltinStr();
+initTypeStr();
+if (isVector()) {
+  initClangBuiltinStr();
+}
+  }
+}
+
+// clang-format off
+// boolean type are encoded the ratio of n (SEW/LMUL)
+// SEW/LMUL | 1 | 2 | 4 | 8| 16| 32| 64
+// c type   | vbool64_t | vbool32_t | vbool16_t | vbool8_t | vbool4_t  | vbool2_t  | vbool1_t
+// IR type  | nxv1i1| nxv2i1| nxv4i1| nxv8i1   | nxv16i1   | nxv32i1   | nxv64i1
+
+// type\lmul | 1/8| 1/4  | 1/2 | 1   | 2| 4| 8
+//   |--  |  | --- | --- |  |  | 
+// i64   | N/A| N/A  | N/A | nxv1i64 | nxv2i64  | nxv4i64  | nxv8i64
+// i32   | N/A| N/A  | nxv1i32 | nxv2i32 | nxv4i32  | nxv8i32  | nxv16i32
+// i16   | N/A| nxv1i16  | nxv2i16 | nxv4i16 | nxv8i16  | nxv16i16 | nxv32i16
+// i8| nxv1i8 | nxv2i8   | nxv4i8  | nxv8i8  | nxv16i8  | nxv32i8  | nxv64i8
+// double| N/A| N/A  | N/A | nxv1f64 | nxv2f64  | nxv4f64  | nxv8f64
+// float | N/A| N/A  | nxv1f32 | nxv2f32 | nxv4f32  | nxv8f32  | nxv16f32
+// half  | N/A| nxv1f16  | nxv2f16 | nxv4f16 | nxv8f16  | nxv16f16 | nxv32f16
+// clang-format on
+
+bool RVVType::verifyType() const {
+  if (ScalarType == Invalid)
+return false;
+  if (isScalar())
+return true;
+  if (!Scale.hasValue())
+return false;
+  if (isFloat() && ElementBitwidth == 8)
+return false;
+  unsigned V = Scale.getValue();
+  switch (ElementBitwidth) {
+  case 1:
+  case 8:
+// Check Scale is 1,2,4,8,16,32,64
+return (V <= 64 && isPowerOf2_32(V));
+  case 16:
+// Check Scale is 1,2,4,8,16,32
+return (V <= 32 && isPowerOf2_32(V));
+  case 32:
+// Check Scale is 1,2,4,8,16
+return (V <= 16 && isPowerOf2_32(V));
+  case 64:
+// Check Scale is 1,2,4,8
+return (V <= 8 && isPowerOf

[PATCH] D121984: [RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a subscriber: akuegel.
kito-cheng added a comment.

Hi @MaskRay, @akuegel has removed the `llvm/TableGen/*`, so I guess the issue 
you mentioned in 
https://github.com/llvm/llvm-project/commit/c0eb9b4cdef6049ebabb4018d3c9dcb0dc699868
 is resolved by 
https://github.com/llvm/llvm-project/commit/268f24d2ea6ae92853c68c4614722d9e769a9408

Are you happy if I recommit that with @akuegel's fix again?


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[PATCH] D122629: [RISCV] Add index check for vset/vget

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng accepted this revision.
kito-cheng added a comment.
This revision is now accepted and ready to land.

LGTM, thanks :)


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[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng marked 9 inline comments as done.
kito-cheng added a comment.

@aaron.ballman thanks for your review!




Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:400
+  // Number of fields, greater than 1 if it's segment load/store.
+  uint8_t NF;
+};

aaron.ballman wrote:
> 
That the term used in RVV spec, so I keep this as `NF` :)


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[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

[Kito Cheng via Phabricator via cfe-commits]

This revision was not accepted when it landed; it landed in state "Needs 
Review".
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
kito-cheng marked an inline comment as done.
Closed by commit rG7a5cb15ea6fa: [RISCV] Lazily add RVV C intrinsics. (authored 
by kito-cheng).

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  https://reviews.llvm.org/D111617?vs=444188&id=447601#toc

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Files:
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TokenKinds.def
  clang/include/clang/Parse/Parser.h
  clang/include/clang/Sema/RISCVIntrinsicManager.h
  clang/include/clang/Sema/Sema.h
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Parse/ParsePragma.cpp
  clang/lib/Sema/CMakeLists.txt
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaLookup.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/test/Sema/riscv-bad-intrinsic-pragma.c
  clang/test/Sema/riscv-intrinsic-pragma.c
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -110,6 +110,7 @@
 void EmitRVVHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltins(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltinCG(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitRVVBuiltinSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 
 void EmitCdeHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitCdeBuiltinDef(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -88,6 +88,7 @@
   GenRISCVVectorHeader,
   GenRISCVVectorBuiltins,
   GenRISCVVectorBuiltinCG,
+  GenRISCVVectorBuiltinSema,
   GenAttrDocs,
   GenDiagDocs,
   GenOptDocs,
@@ -243,6 +244,8 @@
"Generate riscv_vector_builtins.inc for clang"),
 clEnumValN(GenRISCVVectorBuiltinCG, "gen-riscv-vector-builtin-codegen",
"Generate riscv_vector_builtin_cg.inc for clang"),
+clEnumValN(GenRISCVVectorBuiltinSema, "gen-riscv-vector-builtin-sema",
+   "Generate riscv_vector_builtin_sema.inc for clang"),
 clEnumValN(GenAttrDocs, "gen-attr-docs",
"Generate attribute documentation"),
 clEnumValN(GenDiagDocs, "gen-diag-docs",
@@ -458,6 +461,9 @@
   case GenRISCVVectorBuiltinCG:
 EmitRVVBuiltinCG(Records, OS);
 break;
+  case GenRISCVVectorBuiltinSema:
+EmitRVVBuiltinSema(Records, OS);
+break;
   case GenAttrDocs:
 EmitClangAttrDocs(Records, OS);
 break;
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -20,6 +20,7 @@
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/StringSet.h"
+#include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
@@ -29,6 +30,59 @@
 using namespace clang::RISCV;
 
 namespace {
+struct SemaRecord {
+  // Intrinsic name, e.g. vadd_vv
+  std::string Name;
+
+  // Overloaded intrinsic name, could be empty if can be computed from Name
+  // e.g. vadd
+  std::string OverloadedName;
+
+  // Supported type, mask of BasicType.
+  unsigned TypeRangeMask;
+
+  // Supported LMUL.
+  unsigned Log2LMULMask;
+
+  // Required extensions for this intrinsic.
+  unsigned RequiredExtensions;
+
+  // Prototype for this intrinsic.
+  SmallVector Prototype;
+
+  // Prototype for masked intrinsic.
+  SmallVector MaskedPrototype;
+
+  // Suffix of intrinsic name.
+  SmallVector Suffix;
+
+  // Suffix of overloaded intrinsic name.
+  SmallVector OverloadedSuffix;
+
+  // Number of field, large than 1 if it's segment load/store.
+  unsigned NF;
+};
+
+// Compressed function signature table.
+class SemaSignatureTable {
+private:
+  std::vector SignatureTable;
+
+  void insert(ArrayRef Signature);
+
+public:
+  static constexpr unsigned INVALID_INDEX = ~0U;
+
+  // Create compressed signature table from SemaRecords.
+  void init(ArrayRef SemaRecords);
+
+  // Query the Signature, return INVALID_INDEX if not found.
+  unsigned getIndex(ArrayRef Signature);
+
+  /// Print signature table in RVVHeader Record to \p OS
+  void print(raw_ostream &OS);
+};
+
 class RVVEmitter {
 private:
   RecordKeeper &Records;
@@ -45,22 +99,22 @@
   /// Emit all th

[PATCH] D126744: [RISCV][Clang] Support policy functions for vneg, vnot, vncvt, vwcvt, vwcvtu, vfabs and vfneg.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng accepted this revision.
kito-cheng added a comment.
This revision is now accepted and ready to land.

LGTM, and verified with internal testsuite :)


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[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng accepted this revision.
kito-cheng added a comment.
This revision is now accepted and ready to land.
Herald added a subscriber: nlopes.

LGTM, and verified with internal testsuite :)


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[PATCH] D126748: [RISCV][Clang] Support policy functions for Vector Reduction Instructions.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng accepted this revision.
kito-cheng added a comment.
This revision is now accepted and ready to land.
Herald added a subscriber: nlopes.

LGTM, and verified with internal testsuite :)


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[PATCH] D126750: [RISCV][Clang] Support policy function for all vector segment load.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng accepted this revision.
kito-cheng added a comment.
This revision is now accepted and ready to land.
Herald added a subscriber: nlopes.

LGTM, and verified with internal testsuite :)


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[PATCH] D126742: [RISCV][Clang] Support RVV policy functions.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng accepted this revision.
kito-cheng added a comment.
This revision is now accepted and ready to land.

LGTM, and verified with internal testsuite :)


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[PATCH] D130311: [RISCV] Enable strict FP in clang as long as Zve* or V are not enabled.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added inline comments.



Comment at: clang/lib/Basic/Targets/RISCV.cpp:286
+  // StrictFP support for vectors is incomplete.
+  if (ISAInfo->hasExtension("zve32x"))
+HasStrictFP = false;

craig.topper wrote:
> reames wrote:
> > craig.topper wrote:
> > > reames wrote:
> > > > craig.topper wrote:
> > > > > reames wrote:
> > > > > > asb wrote:
> > > > > > > There's also code in RISCVISAInfo.cpp that does `HasVector = 
> > > > > > > Exts.count("zve32x") != 0`. It's probably worth adding a helper 
> > > > > > > (`hasVInstructions`?) that encapsulates this, and use it from 
> > > > > > > both places.
> > > > > > It's not clear to me why this condition is specific to embedded 
> > > > > > vector variants.  Do we have strict FP with +V?  Either you need to 
> > > > > > fix a comment here, or the condition.  One or the other.  
> > > > > V implies Zve64d implies Zve64f implies Zve32f and Zve64x. Zve32f 
> > > > > implies Zve32x. Zve32x is the root of the vector inheritance tree.
> > > > So, I went digging.  I agree that our *implementation* treats V as 
> > > > implying Zve64d, but I can find anything in the *specification* to that 
> > > > effect.  The feature set seems like it might be identical between the 
> > > > two, but I don't see anything in the spec which requires a +V 
> > > > implementation to claim support for Zve64d.  Do you have particular 
> > > > wording in mind I'm missing?  
> > > > 
> > > > (Regardless, the fact we assume this elsewhere means this is a 
> > > > non-blocking comment for this review.  At the very least, this isn't 
> > > > introducing a new problem.)
> > > We removed the implication for a brief period but Krste and Andrew 
> > > disagreed. I believe this is now covered by the note at the end of 
> > > https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#183-v-vector-extension-for-application-processors
> > > 
> > > "As is the case with other RISC-V extensions, it is valid to include 
> > > overlapping extensions in the same ISA string. For example, RV64GCV and 
> > > RV64GCV_Zve64f are both valid and equivalent ISA strings, as is 
> > > RV64GCV_Zve64f_Zve32x_Zvl128b."
> > Er, yuck that's subtle.  Not quite sure I'd read it the way you do, but 
> > your read is at least easily defensible.  We can wait until someone has a 
> > concrete case where they aren't implied before figuring out if that case is 
> > disallowed per the spec.  :)
> Maybe their biggest issue with the split we had was that we made them mutex 
> and issued an error.
> 
> I'm going to add the wrapper that Alex suggested so that this is more 
> centralized.
I think check `zve32f` would be better? `zve32x` means we have integer vector 
instruction but might not have any floating point vector instructions. 


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[PATCH] D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

Just realized the problem is trying to fixed the default value of `-mabi=`, 
currently `clang -target riscv32-elf -march=rv64gc 
-mabi=lp64d`/`riscv32-elf-clang -march=rv64gc -mabi=lp64d` is work, and match 
the behavior of GCC did, `riscv32-elf-gcc -march=rv64gc -mabi=lp64d`.

And this patch is trying to make following two command work: `clang -target 
riscv32-elf -march=rv64gc`/`riscv32-elf-clang -march=rv64gc`, specify `-march` 
and `-target` but no `-mabi`.

That is different story now, GCC isn't deduce the default abi from either 
target triple or abi, so if you invoke gcc with `riscv32-elf-gcc -march=rv64gc` 
or `riscv64-elf-gcc -march=rv32gc`, you will got error message like that: `cc1: 
error: ABI requires '-march=rv32'` or `cc1: error: ABI requires '-march=rv64'`.

So that's not compatible issue with GCC, that's sort of clang driver specify 
issue, and I don't have strong opinion on this.

---

As a GNU toolchain developer, I would say, we are not intend to change the 
behavior of default value of `-mabi` or `-march`, the consensus among RISC-V 
GNU toolchain maintainer is user should explicitly specify the `-march` and 
`-mabi` if you are not using default `-march` and `-mabi`.


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[PATCH] D131345: [RISC-V][HWASAN] Enable HWASAN for RISC-V architecture

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

I guess we should checking `J` extension is enabled somewhere when user trying 
to enable HWASAN? or checking that at HWASAN library at run-time? otherwise my 
understanding is user will get crash when enabling HWASAN if linux and/or HW 
don't support that?


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[PATCH] D105690: [RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added inline comments.



Comment at: llvm/test/MC/RISCV/rvv/aliases.s:86
+# NO-ALIAS: vfwredusum.vs v8, v4, v20, v0.t  # encoding: [0x57,0x14,0x4a,0xc4]
+vfwredusum.vs v8, v4, v20, v0.t

I guess you want to verify `vfredsum.vs`  and `vfwredsum.vs` here?


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[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng marked 2 inline comments as done.
kito-cheng added inline comments.



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:460
+
+addExtension("e");
+  }

khchen wrote:
> nit: add `break;` to avoid the implicit-fallthrough warning.
Oh, thanks, it seems like more than nit :p


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[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 360842.
kito-cheng marked an inline comment as done.
kito-cheng added a comment.

Changes:

- Address @khchen's comment.


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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-abi.c
  clang/test/Driver/riscv-arch.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/CMakeLists.txt
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/attribute-with-insts.s
  llvm/test/MC/RISCV/invalid-attribute.s

Index: llvm/test/MC/RISCV/invalid-attribute.s
===
--- llvm/test/MC/RISCV/invalid-attribute.s
+++ llvm/test/MC/RISCV/invalid-attribute.s
@@ -7,10 +7,10 @@
 # RUN: not llvm-mc %s -triple=riscv64 -filetype=asm 2>&1 | FileCheck %s
 
 .attribute arch, "foo"
-# CHECK: [[@LINE-1]]:18: error: bad arch string foo
+# CHECK: [[@LINE-1]]:18: error: invalid arch name 'foo', string must begin with rv32{i,e,g} or rv64{i,g}
 
 .attribute arch, "rv32i2p0_y2p0"
-# CHECK: [[@LINE-1]]:18: error: bad arch string y2p0
+# CHECK: [[@LINE-1]]:18: error: invalid arch name 'rv32i2p0_y2p0', invalid standard user-level extension 'y'
 
 .attribute stack_align, "16"
 # CHECK: [[@LINE-1]]:25: error: expected numeric constant
Index: llvm/test/MC/RISCV/attribute-with-insts.s
===
--- llvm/test/MC/RISCV/attribute-with-insts.s
+++ llvm/test/MC/RISCV/attribute-with-insts.s
@@ -10,7 +10,7 @@
 # RUN:   | llvm-objdump --triple=riscv64 -d -M no-aliases - \
 # RUN:   | FileCheck -check-prefix=CHECK-INST %s
 
-.attribute arch, "rv64i2p0_m2p0_a2p0_d2p0_c2p0"
+.attribute arch, "rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 # CHECK-INST: lr.w t0, (t1)
 lr.w t0, (t1)
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -9,9 +9,6 @@
 .attribute arch, "rv32i2"
 # CHECK: attribute  5, "rv32i2p0"
 
-.attribute arch, "rv32i2p"
-# CHECK: attribute  5, "rv32i2p0"
-
 .attribute arch, "rv32i2p0"
 # CHECK: attribute  5, "rv32i2p0"
 
@@ -33,14 +30,14 @@
 .attribute arch, "rv32ima2p0_fdc"
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
-.attribute arch, "rv32ima2p_fdc"
+.attribute arch, "rv32ima2p0_fdc"
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32ib"
 # CHECK: attribute  5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_v0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba"
 # CHECK: attribute  5, "rv32i2p0_zba0p93"
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
===
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -11,9 +11,11 @@
 //===--===//
 
 #include "RISCVTargetStreamer.h"
+#include "RISCVBaseInfo.h"
 #include "RISCVMCTargetDesc.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/RISCVAttributes.h"
+#include "llvm/Support/RISCVISAInfo.h"
 
 using namespace llvm;
 
@@ -43,57 +45,14 @@
   else
 emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16);
 
-  std::string Arch = "rv32";
-  if (STI.hasFeature(RISCV::Feature64Bit))
-Arch = "rv64";
-  if (STI.hasFeature(RISCV::FeatureRV32E))
-Arch += "e1p9";
-  else
-Arch += "i2p0";
-  if (STI.hasFeature(RISCV::FeatureStdExtM))
-Arch += "_m2p0";
-  if (STI.hasFeature(RISCV::FeatureStdExtA))
-Arch += "_a2p0";
-  if (STI.hasFeature(RISCV::FeatureStdExtF))
-Arch += "_f2p0";
-  if (STI.hasFeature(RISCV::FeatureStdExtD))
-Arch += "_d2p0";
-  if (STI.hasFeature(RISCV::FeatureStdExtC))
-Arch += "_c2p0";
-  if (STI.hasFeature(RISCV::FeatureStdExtB))
-Arch += "_b0p93";
-  if (STI.hasFeature(RISCV::FeatureStdExtV))
-Arch += "_v0p10";
-  if (STI.hasFeature(RISCV::FeatureExtZfh))
-Arch += "_zfh0p1";
-  if (STI.hasFeature(RISCV::FeatureExtZba))
-Arch += "_zba0p93";
-  if (STI.hasFeature(RISCV::FeatureExtZbb))
-Arch += "_zbb0p93";
-  if (STI.hasFeature(RISCV::FeatureExtZbc))
-Arch += "_zbc0p93";
-  if (STI.hasFeature(RISCV::FeatureExtZbe))
-Arch += "_zbe0p93";
-  if (STI.hasFeature(RISCV::FeatureEx

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 361137.
kito-cheng added a comment.

Changes:

- New function RISCVISAInfo::isSupportedExtensionFeature
- Remove parameter CheckExperimental from RISCVISAInfo::isSupportedExtension
- Clean up obvious comments
- Address @jrtc27's and @craig.topper's comments


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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-abi.c
  clang/test/Driver/riscv-arch.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/CMakeLists.txt
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/attribute-with-insts.s
  llvm/test/MC/RISCV/invalid-attribute.s

Index: llvm/test/MC/RISCV/invalid-attribute.s
===
--- llvm/test/MC/RISCV/invalid-attribute.s
+++ llvm/test/MC/RISCV/invalid-attribute.s
@@ -7,10 +7,10 @@
 # RUN: not llvm-mc %s -triple=riscv64 -filetype=asm 2>&1 | FileCheck %s
 
 .attribute arch, "foo"
-# CHECK: [[@LINE-1]]:18: error: bad arch string foo
+# CHECK: [[@LINE-1]]:18: error: invalid arch name 'foo', string must begin with rv32{i,e,g} or rv64{i,g}
 
 .attribute arch, "rv32i2p0_y2p0"
-# CHECK: [[@LINE-1]]:18: error: bad arch string y2p0
+# CHECK: [[@LINE-1]]:18: error: invalid arch name 'rv32i2p0_y2p0', invalid standard user-level extension 'y'
 
 .attribute stack_align, "16"
 # CHECK: [[@LINE-1]]:25: error: expected numeric constant
Index: llvm/test/MC/RISCV/attribute-with-insts.s
===
--- llvm/test/MC/RISCV/attribute-with-insts.s
+++ llvm/test/MC/RISCV/attribute-with-insts.s
@@ -10,7 +10,7 @@
 # RUN:   | llvm-objdump --triple=riscv64 -d -M no-aliases - \
 # RUN:   | FileCheck -check-prefix=CHECK-INST %s
 
-.attribute arch, "rv64i2p0_m2p0_a2p0_d2p0_c2p0"
+.attribute arch, "rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 # CHECK-INST: lr.w t0, (t1)
 lr.w t0, (t1)
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -9,9 +9,6 @@
 .attribute arch, "rv32i2"
 # CHECK: attribute  5, "rv32i2p0"
 
-.attribute arch, "rv32i2p"
-# CHECK: attribute  5, "rv32i2p0"
-
 .attribute arch, "rv32i2p0"
 # CHECK: attribute  5, "rv32i2p0"
 
@@ -33,14 +30,14 @@
 .attribute arch, "rv32ima2p0_fdc"
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
-.attribute arch, "rv32ima2p_fdc"
+.attribute arch, "rv32ima2p0_fdc"
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32ib"
 # CHECK: attribute  5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_v0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba"
 # CHECK: attribute  5, "rv32i2p0_zba0p93"
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
===
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -11,9 +11,11 @@
 //===--===//
 
 #include "RISCVTargetStreamer.h"
+#include "RISCVBaseInfo.h"
 #include "RISCVMCTargetDesc.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/RISCVAttributes.h"
+#include "llvm/Support/RISCVISAInfo.h"
 
 using namespace llvm;
 
@@ -43,57 +45,14 @@
   else
 emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16);
 
-  std::string Arch = "rv32";
-  if (STI.hasFeature(RISCV::Feature64Bit))
-Arch = "rv64";
-  if (STI.hasFeature(RISCV::FeatureRV32E))
-Arch += "e1p9";
-  else
-Arch += "i2p0";
-  if (STI.hasFeature(RISCV::FeatureStdExtM))
-Arch += "_m2p0";
-  if (STI.hasFeature(RISCV::FeatureStdExtA))
-Arch += "_a2p0";
-  if (STI.hasFeature(RISCV::FeatureStdExtF))
-Arch += "_f2p0";
-  if (STI.hasFeature(RISCV::FeatureStdExtD))
-Arch += "_d2p0";
-  if (STI.hasFeature(RISCV::FeatureStdExtC))
-Arch += "_c2p0";
-  if (STI.hasFeature(RISCV::FeatureStdExtB))
-Arch += "_b0p93";
-  if (STI.hasFeature(RISCV::FeatureStdExtV))
-Arch += "_v0p10";
-  if (STI.hasFeature(RISCV::FeatureExtZfh))
-Arch += "_zfh0p1";
-  if (STI.hasFeature(RISCV::FeatureExtZba))
-Arch += "_zba0p93";
-  if (STI.hasFeature(RISCV::FeatureExtZbb))
-Arch += "_zbb0p93";
-  if (STI.hasFeature(RISCV::FeatureExtZb

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng marked 8 inline comments as done.
kito-cheng added inline comments.



Comment at: clang/test/Driver/riscv-arch.c:198-201
-// RUN: %clang -target riscv32-unknown-elf -march=rv32e -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32E %s
-// RV32E: error: invalid arch name 'rv32e',
-// RV32E: standard user-level extension 'e'

jrtc27 wrote:
> Hm, given we don't currently support RV32E properly this should probably be 
> an error still, but could be a "nicer" error than a generic "invalid arch 
> name" (which is technically wrong)
We support E-extension on MC-layer...but not support `ilp32e`.

This patch unify the ISA stuffs, so either I need to remove that from MC, or I 
need to made rv32e supported on driver...

https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp#L50
https://github.com/llvm/llvm-project/blob/main/llvm/test/MC/RISCV/rv32e-valid.s
https://github.com/llvm/llvm-project/blob/main/llvm/test/MC/RISCV/rv32e-invalid.s



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:40
+
+static const StringRef AllStdExts = "mafdqlcbjtpvn";
+

jrtc27 wrote:
> craig.topper wrote:
> > Make this `static constexpr StringLiteral AllStdExts = "mafdqlcbjtpvn";`
> I can't help but feel this is really an array of chars, not a string. We 
> don't even need the trailing NUL, though double quote syntax is simpler than 
> curly braces and a bunch of single-quote chars just to save a byte.
Yeah, it's actually just an array of chars, but we have use find function from 
StringRef :p



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:135
+  if (CheckExperimental)
+IsExperimental = stripExperimentalPrefix(Ext);
+

jrtc27 wrote:
> *Extensions* don't have an experimental- prefix, *internal target features* 
> do, so something strange is going on here. This feels like we're confusing 
> several things:
> 1. Whether or not Ext is a feature or an extension
> 2. Whether or not Ext is experimental
> 3. Whether we want to look at experimental extensions
> Some of those are somewhat necessarily interwoven, but the naming does not 
> currently accurately reflect what these things mean, and I would argue we 
> should be very explicit and keep features and extensions separate, never 
> using the same thing to represent both.
Good point, CheckExperimental is kind of ambiguous,  new function: 
isSupportedExtensionFeature added.


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[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 361141.
kito-cheng marked an inline comment as done.
kito-cheng added a comment.

Changes:

- Rename RISCVISAInfo::parse to 
RISCVISAInfo::parseFeatures/RISCVISAInfo::parseArchString


Repository:
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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-abi.c
  clang/test/Driver/riscv-arch.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/CMakeLists.txt
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/attribute-with-insts.s
  llvm/test/MC/RISCV/invalid-attribute.s

Index: llvm/test/MC/RISCV/invalid-attribute.s
===
--- llvm/test/MC/RISCV/invalid-attribute.s
+++ llvm/test/MC/RISCV/invalid-attribute.s
@@ -7,10 +7,10 @@
 # RUN: not llvm-mc %s -triple=riscv64 -filetype=asm 2>&1 | FileCheck %s
 
 .attribute arch, "foo"
-# CHECK: [[@LINE-1]]:18: error: bad arch string foo
+# CHECK: [[@LINE-1]]:18: error: invalid arch name 'foo', string must begin with rv32{i,e,g} or rv64{i,g}
 
 .attribute arch, "rv32i2p0_y2p0"
-# CHECK: [[@LINE-1]]:18: error: bad arch string y2p0
+# CHECK: [[@LINE-1]]:18: error: invalid arch name 'rv32i2p0_y2p0', invalid standard user-level extension 'y'
 
 .attribute stack_align, "16"
 # CHECK: [[@LINE-1]]:25: error: expected numeric constant
Index: llvm/test/MC/RISCV/attribute-with-insts.s
===
--- llvm/test/MC/RISCV/attribute-with-insts.s
+++ llvm/test/MC/RISCV/attribute-with-insts.s
@@ -10,7 +10,7 @@
 # RUN:   | llvm-objdump --triple=riscv64 -d -M no-aliases - \
 # RUN:   | FileCheck -check-prefix=CHECK-INST %s
 
-.attribute arch, "rv64i2p0_m2p0_a2p0_d2p0_c2p0"
+.attribute arch, "rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 # CHECK-INST: lr.w t0, (t1)
 lr.w t0, (t1)
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -9,9 +9,6 @@
 .attribute arch, "rv32i2"
 # CHECK: attribute  5, "rv32i2p0"
 
-.attribute arch, "rv32i2p"
-# CHECK: attribute  5, "rv32i2p0"
-
 .attribute arch, "rv32i2p0"
 # CHECK: attribute  5, "rv32i2p0"
 
@@ -33,14 +30,14 @@
 .attribute arch, "rv32ima2p0_fdc"
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
-.attribute arch, "rv32ima2p_fdc"
+.attribute arch, "rv32ima2p0_fdc"
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32ib"
 # CHECK: attribute  5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_v0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba"
 # CHECK: attribute  5, "rv32i2p0_zba0p93"
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
===
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -11,9 +11,11 @@
 //===--===//
 
 #include "RISCVTargetStreamer.h"
+#include "RISCVBaseInfo.h"
 #include "RISCVMCTargetDesc.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/RISCVAttributes.h"
+#include "llvm/Support/RISCVISAInfo.h"
 
 using namespace llvm;
 
@@ -43,57 +45,14 @@
   else
 emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16);
 
-  std::string Arch = "rv32";
-  if (STI.hasFeature(RISCV::Feature64Bit))
-Arch = "rv64";
-  if (STI.hasFeature(RISCV::FeatureRV32E))
-Arch += "e1p9";
-  else
-Arch += "i2p0";
-  if (STI.hasFeature(RISCV::FeatureStdExtM))
-Arch += "_m2p0";
-  if (STI.hasFeature(RISCV::FeatureStdExtA))
-Arch += "_a2p0";
-  if (STI.hasFeature(RISCV::FeatureStdExtF))
-Arch += "_f2p0";
-  if (STI.hasFeature(RISCV::FeatureStdExtD))
-Arch += "_d2p0";
-  if (STI.hasFeature(RISCV::FeatureStdExtC))
-Arch += "_c2p0";
-  if (STI.hasFeature(RISCV::FeatureStdExtB))
-Arch += "_b0p93";
-  if (STI.hasFeature(RISCV::FeatureStdExtV))
-Arch += "_v0p10";
-  if (STI.hasFeature(RISCV::FeatureExtZfh))
-Arch += "_zfh0p1";
-  if (STI.hasFeature(RISCV::FeatureExtZba))
-Arch += "_zba0p93";
-  if (STI.hasFeature(RISCV::FeatureExtZbb))
-Arch += "_zbb0p93";
-  if (STI.hasFeature(RISCV::FeatureExtZbc))
-Arch += "_zbc0p93";
-  if (STI.hasFeature(RISCV::FeatureExtZbe))
-

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng marked an inline comment as done.
kito-cheng added inline comments.



Comment at: llvm/include/llvm/Support/RISCVISAInfo.h:45
+
+  // Parse RISCV ISA info from arch string.
+  Error parse(StringRef Arch, bool EnableExperimentalExtension,

jrtc27 wrote:
> These comments aren't helpful. If you want to write full doxygen then you 
> can, but a one-line comment that won't appear in documentation and is obvious 
> from the function name and signature is just clutter.
Rename RISCVISAInfo::parse to 
RISCVISAInfo::parseFeatures/RISCVISAInfo::parseArchString, I guess it should be 
more clear.


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[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 361915.
kito-cheng marked an inline comment as done.
kito-cheng added a comment.

Changes:

- Address @frasercrmck's comment


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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-abi.c
  clang/test/Driver/riscv-arch.c
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/CMakeLists.txt
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/attribute-with-insts.s
  llvm/test/MC/RISCV/invalid-attribute.s

Index: llvm/test/MC/RISCV/invalid-attribute.s
===
--- llvm/test/MC/RISCV/invalid-attribute.s
+++ llvm/test/MC/RISCV/invalid-attribute.s
@@ -7,10 +7,10 @@
 # RUN: not llvm-mc %s -triple=riscv64 -filetype=asm 2>&1 | FileCheck %s
 
 .attribute arch, "foo"
-# CHECK: [[@LINE-1]]:18: error: bad arch string foo
+# CHECK: [[@LINE-1]]:18: error: invalid arch name 'foo', string must begin with rv32{i,e,g} or rv64{i,g}
 
 .attribute arch, "rv32i2p0_y2p0"
-# CHECK: [[@LINE-1]]:18: error: bad arch string y2p0
+# CHECK: [[@LINE-1]]:18: error: invalid arch name 'rv32i2p0_y2p0', invalid standard user-level extension 'y'
 
 .attribute stack_align, "16"
 # CHECK: [[@LINE-1]]:25: error: expected numeric constant
Index: llvm/test/MC/RISCV/attribute-with-insts.s
===
--- llvm/test/MC/RISCV/attribute-with-insts.s
+++ llvm/test/MC/RISCV/attribute-with-insts.s
@@ -10,7 +10,7 @@
 # RUN:   | llvm-objdump --triple=riscv64 -d -M no-aliases - \
 # RUN:   | FileCheck -check-prefix=CHECK-INST %s
 
-.attribute arch, "rv64i2p0_m2p0_a2p0_d2p0_c2p0"
+.attribute arch, "rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 # CHECK-INST: lr.w t0, (t1)
 lr.w t0, (t1)
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -9,9 +9,6 @@
 .attribute arch, "rv32i2"
 # CHECK: attribute  5, "rv32i2p0"
 
-.attribute arch, "rv32i2p"
-# CHECK: attribute  5, "rv32i2p0"
-
 .attribute arch, "rv32i2p0"
 # CHECK: attribute  5, "rv32i2p0"
 
@@ -33,14 +30,14 @@
 .attribute arch, "rv32ima2p0_fdc"
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
-.attribute arch, "rv32ima2p_fdc"
+.attribute arch, "rv32ima2p0_fdc"
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32ib"
 # CHECK: attribute  5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_v0p10"
+# CHECK: attribute  5, "rv32i2p0_v0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba"
 # CHECK: attribute  5, "rv32i2p0_zba0p93"
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
===
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -11,9 +11,11 @@
 //===--===//
 
 #include "RISCVTargetStreamer.h"
+#include "RISCVBaseInfo.h"
 #include "RISCVMCTargetDesc.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/RISCVAttributes.h"
+#include "llvm/Support/RISCVISAInfo.h"
 
 using namespace llvm;
 
@@ -43,57 +45,14 @@
   else
 emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16);
 
-  std::string Arch = "rv32";
-  if (STI.hasFeature(RISCV::Feature64Bit))
-Arch = "rv64";
-  if (STI.hasFeature(RISCV::FeatureRV32E))
-Arch += "e1p9";
-  else
-Arch += "i2p0";
-  if (STI.hasFeature(RISCV::FeatureStdExtM))
-Arch += "_m2p0";
-  if (STI.hasFeature(RISCV::FeatureStdExtA))
-Arch += "_a2p0";
-  if (STI.hasFeature(RISCV::FeatureStdExtF))
-Arch += "_f2p0";
-  if (STI.hasFeature(RISCV::FeatureStdExtD))
-Arch += "_d2p0";
-  if (STI.hasFeature(RISCV::FeatureStdExtC))
-Arch += "_c2p0";
-  if (STI.hasFeature(RISCV::FeatureStdExtB))
-Arch += "_b0p93";
-  if (STI.hasFeature(RISCV::FeatureStdExtV))
-Arch += "_v0p10";
-  if (STI.hasFeature(RISCV::FeatureExtZfh))
-Arch += "_zfh0p1";
-  if (STI.hasFeature(RISCV::FeatureExtZba))
-Arch += "_zba0p93";
-  if (STI.hasFeature(RISCV::FeatureExtZbb))
-Arch += "_zbb0p93";
-  if (STI.hasFeature(RISCV::FeatureExtZbc))
-Arch += "_zbc0p93";
-  if (STI.hasFeature(RISCV::FeatureExtZbe))
-Arch += "_zbe0p93";
-  if (STI.hasFeature(RISCV::Featu

[PATCH] D121431: Split up large test files(over 10k lines) under clang/test/CodeGen/RISCV including:

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng accepted this revision.
kito-cheng added a comment.
This revision is now accepted and ready to land.

LGTM, thanks!


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[PATCH] D121345: [RISCV] Add +experimental-zvfh extension to cover half types in vectors.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added inline comments.



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:727
 
+  if (Exts.count("zvfh") && !Exts.count("zfh") && !Exts.count("zhinx"))
+return createStringError(

Zvfh require `Zfhmin` rather than `Zfh`

Spec: `The Zvfh extension additionally requires the Zfhmin extension.`
https://github.com/riscv/riscv-v-spec/pull/780/files#diff-ea57dd7a8daf0aa62f553688c1970c8e6608945d25597f8661c5ea6670fb509cR5182



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[PATCH] D121345: [RISCV] Add +experimental-zvfh extension to cover half types in vectors.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng accepted this revision.
kito-cheng added a comment.
This revision is now accepted and ready to land.
Herald added subscribers: s, arichardson.

LGTM


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[PATCH] D121984: [RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng created this revision.
Herald added subscribers: s, VincentWu, luke957, vkmr, frasercrmck, evandro, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya, arichardson, 
mgorny.
Herald added a project: All.
kito-cheng requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, eopXD, 
MaskRay.
Herald added projects: clang, LLVM.

This patch is split from https://reviews.llvm.org/D111617, we need those
stuffs on clang, so must moving those stuff to llvm/Support.


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Files:
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/include/llvm/Support/RISCVVIntrinsicUtils.h
  llvm/lib/Support/CMakeLists.txt
  llvm/lib/Support/RISCVVIntrinsicUtils.cpp

Index: llvm/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- /dev/null
+++ llvm/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -0,0 +1,668 @@
+//===- RISCVVIntrinsicUtils.cpp - RISC-V Vector Intrinsic Utils -*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "llvm/Support/RISCVVIntrinsicUtils.h"
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/SmallSet.h"
+#include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/StringMap.h"
+#include "llvm/ADT/StringSet.h"
+#include "llvm/ADT/Twine.h"
+#include "llvm/TableGen/Error.h"
+#include "llvm/TableGen/Record.h"
+#include 
+
+namespace llvm {
+namespace RISCV {
+
+//===--===//
+// Type implementation
+//===--===//
+
+LMULType::LMULType(int NewLog2LMUL) {
+  // Check Log2LMUL is -3, -2, -1, 0, 1, 2, 3
+  assert(NewLog2LMUL <= 3 && NewLog2LMUL >= -3 && "Bad LMUL number!");
+  Log2LMUL = NewLog2LMUL;
+}
+
+std::string LMULType::str() const {
+  if (Log2LMUL < 0)
+return "mf" + utostr(1ULL << (-Log2LMUL));
+  return "m" + utostr(1ULL << Log2LMUL);
+}
+
+VScaleVal LMULType::getScale(unsigned ElementBitwidth) const {
+  int Log2ScaleResult = 0;
+  switch (ElementBitwidth) {
+  default:
+break;
+  case 8:
+Log2ScaleResult = Log2LMUL + 3;
+break;
+  case 16:
+Log2ScaleResult = Log2LMUL + 2;
+break;
+  case 32:
+Log2ScaleResult = Log2LMUL + 1;
+break;
+  case 64:
+Log2ScaleResult = Log2LMUL;
+break;
+  }
+  // Illegal vscale result would be less than 1
+  if (Log2ScaleResult < 0)
+return llvm::None;
+  return 1 << Log2ScaleResult;
+}
+
+void LMULType::MulLog2LMUL(int log2LMUL) { Log2LMUL += log2LMUL; }
+
+LMULType &LMULType::operator*=(uint32_t RHS) {
+  assert(isPowerOf2_32(RHS));
+  this->Log2LMUL = this->Log2LMUL + Log2_32(RHS);
+  return *this;
+}
+
+RVVType::RVVType(BasicType BT, int Log2LMUL, StringRef prototype)
+: BT(BT), LMUL(LMULType(Log2LMUL)) {
+  applyBasicType();
+  applyModifier(prototype);
+  Valid = verifyType();
+  if (Valid) {
+initBuiltinStr();
+initTypeStr();
+if (isVector()) {
+  initClangBuiltinStr();
+}
+  }
+}
+
+// clang-format off
+// boolean type are encoded the ratio of n (SEW/LMUL)
+// SEW/LMUL | 1 | 2 | 4 | 8| 16| 32| 64
+// c type   | vbool64_t | vbool32_t | vbool16_t | vbool8_t | vbool4_t  | vbool2_t  | vbool1_t
+// IR type  | nxv1i1| nxv2i1| nxv4i1| nxv8i1   | nxv16i1   | nxv32i1   | nxv64i1
+
+// type\lmul | 1/8| 1/4  | 1/2 | 1   | 2| 4| 8
+//   |--  |  | --- | --- |  |  | 
+// i64   | N/A| N/A  | N/A | nxv1i64 | nxv2i64  | nxv4i64  | nxv8i64
+// i32   | N/A| N/A  | nxv1i32 | nxv2i32 | nxv4i32  | nxv8i32  | nxv16i32
+// i16   | N/A| nxv1i16  | nxv2i16 | nxv4i16 | nxv8i16  | nxv16i16 | nxv32i16
+// i8| nxv1i8 | nxv2i8   | nxv4i8  | nxv8i8  | nxv16i8  | nxv32i8  | nxv64i8
+// double| N/A| N/A  | N/A | nxv1f64 | nxv2f64  | nxv4f64  | nxv8f64
+// float | N/A| N/A  | nxv1f32 | nxv2f32 | nxv4f32  | nxv8f32  | nxv16f32
+// half  | N/A| nxv1f16  | nxv2f16 | nxv4f16 | nxv8f16  | nxv16f16 | nxv32f16
+// clang-format on
+
+bool RVVType::verifyType() const {
+  if (ScalarType == Invalid)
+return false;
+  if (isScalar())
+return true;
+  if (!Scale.hasValue())
+return false;
+  if (isFloat() && ElementBitwidth == 8)
+return false;
+  unsigned V = Scale.getValue();
+  switch (ElementBitwidth) {
+  case 1:
+  case 8:
+// Check Scale is 1,2,4,8,16,32,64
+return (V <= 64 &&

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

> If I understand correctly, E can't be combined with D in current 
> specification since E must use ILP32E calling convention.

Calling convention and extensions are separated, calling convention are specify 
the how argument passing and the register convention, so ILP32E *can* use with 
`-march=rv32efd`, but it can't pass or return floating point type in FPR.

Just like we can `ILP32` for `-march=rv32ifd` and `LP64` with `-march=rv64ifd`, 
you may confused about the opposite combination like `ILP32D` with 
`-march=rv32i` and `LP64D` with `-march=rv64i` is not work, that's because it 
require pass or return floating point type in FPR, but FPR isn't existing in 
such ISA config.


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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

Last LLVM sync-up call @asb has raise the discussion about the ILP32E issue, so 
here is note from my site:

RISC-V psABI doc still say "we don't  guarantee the stability of `ILP32E`", the 
reason is RV32E still not a ratified extension, but as psABI chair, what I can 
say is we intend to do NOT change as possible.

As I know rv32e*/ilp32e are already used by many vendors (include SiFive), so I 
support ilp32e should be supported on LLVM upstream.


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[PATCH] D121984: [RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

Oh, apology, I guess I just miss the discussion, let me revert that again.


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[PATCH] D121984: [RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 421477.
kito-cheng added a comment.

Changes:

- Move those stuffs into clang/Support instead of llvm/Support
- Keep table gen staffs in clang/utils/TableGen/RISCVVEmitter.cpp


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Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/CMakeLists.txt
  clang/lib/Support/CMakeLists.txt
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -14,6 +14,7 @@
 //
 //===--===//
 
+#include "clang/Support/RISCVVIntrinsicUtils.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/StringExtras.h"
@@ -25,206 +26,9 @@
 #include 
 
 using namespace llvm;
-using BasicType = char;
-using VScaleVal = Optional;
+using namespace clang::RISCV;
 
 namespace {
-
-// Exponential LMUL
-struct LMULType {
-  int Log2LMUL;
-  LMULType(int Log2LMUL);
-  // Return the C/C++ string representation of LMUL
-  std::string str() const;
-  Optional getScale(unsigned ElementBitwidth) const;
-  void MulLog2LMUL(int Log2LMUL);
-  LMULType &operator*=(uint32_t RHS);
-};
-
-// This class is compact representation of a valid and invalid RVVType.
-class RVVType {
-  enum ScalarTypeKind : uint32_t {
-Void,
-Size_t,
-Ptrdiff_t,
-UnsignedLong,
-SignedLong,
-Boolean,
-SignedInteger,
-UnsignedInteger,
-Float,
-Invalid,
-  };
-  BasicType BT;
-  ScalarTypeKind ScalarType = Invalid;
-  LMULType LMUL;
-  bool IsPointer = false;
-  // IsConstant indices are "int", but have the constant expression.
-  bool IsImmediate = false;
-  // Const qualifier for pointer to const object or object of const type.
-  bool IsConstant = false;
-  unsigned ElementBitwidth = 0;
-  VScaleVal Scale = 0;
-  bool Valid;
-
-  std::string BuiltinStr;
-  std::string ClangBuiltinStr;
-  std::string Str;
-  std::string ShortStr;
-
-public:
-  RVVType() : RVVType(BasicType(), 0, StringRef()) {}
-  RVVType(BasicType BT, int Log2LMUL, StringRef prototype);
-
-  // Return the string representation of a type, which is an encoded string for
-  // passing to the BUILTIN() macro in Builtins.def.
-  const std::string &getBuiltinStr() const { return BuiltinStr; }
-
-  // Return the clang builtin type for RVV vector type which are used in the
-  // riscv_vector.h header file.
-  const std::string &getClangBuiltinStr() const { return ClangBuiltinStr; }
-
-  // Return the C/C++ string representation of a type for use in the
-  // riscv_vector.h header file.
-  const std::string &getTypeStr() const { return Str; }
-
-  // Return the short name of a type for C/C++ name suffix.
-  const std::string &getShortStr() {
-// Not all types are used in short name, so compute the short name by
-// demanded.
-if (ShortStr.empty())
-  initShortStr();
-return ShortStr;
-  }
-
-  bool isValid() const { return Valid; }
-  bool isScalar() const { return Scale.hasValue() && Scale.getValue() == 0; }
-  bool isVector() const { return Scale.hasValue() && Scale.getValue() != 0; }
-  bool isVector(unsigned Width) const {
-return isVector() && ElementBitwidth == Width;
-  }
-  bool isFloat() const { return ScalarType == ScalarTypeKind::Float; }
-  bool isSignedInteger() const {
-return ScalarType == ScalarTypeKind::SignedInteger;
-  }
-  bool isFloatVector(unsigned Width) const {
-return isVector() && isFloat() && ElementBitwidth == Width;
-  }
-  bool isFloat(unsigned Width) const {
-return isFloat() && ElementBitwidth == Width;
-  }
-
-private:
-  // Verify RVV vector type and set Valid.
-  bool verifyType() const;
-
-  // Creates a type based on basic types of TypeRange
-  void applyBasicType();
-
-  // Applies a prototype modifier to the current type. The result maybe an
-  // invalid type.
-  void applyModifier(StringRef prototype);
-
-  // Compute and record a string for legal type.
-  void initBuiltinStr();
-  // Compute and record a builtin RVV vector type string.
-  void initClangBuiltinStr();
-  // Compute and record a type string for used in the header.
-  void initTypeStr();
-  // Compute and record a short name of a type for C/C++ name suffix.
-  void initShortStr();
-};
-
-using RVVTypePtr = RVVType *;
-using RVVTypes = std::vector;
-using RISCVPredefinedMacroT = uint8_t;
-
-enum RISCVPredefinedMacro : RISCVPredefinedMacroT {
-  Basic = 0,
-  V = 1 << 1,
-  Zvfh = 1 << 2,
-  RV64 = 1 << 3,
-  VectorMaxELen64 = 1 << 4,
-  VectorMaxELenFp32 = 1 << 5,
-  VectorMaxELenFp64 = 1 << 6,
-};
-
-enum PolicyScheme : uint8_t {
-  SchemeNone,
-  HasPassthruOperand,
-  HasPolicyOperand,

[PATCH] D121984: [RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

@MaskRay I've move those stuffs into clang/Support which is introduce by this 
patch, and also keep those table gen stuffs in clang-tblgen, did you mind take 
a look?

Thanks :)


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[PATCH] D121984: [RISCV] Moving RVV intrinsic type related util to clang/Support

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

Hi @aaron.ballman:

> Why shouldn't this live in clang/utils/TableGen along with the others?

We plan to use those stuffs on clang side in https://reviews.llvm.org/D111617, 
my original change was put those stuffs on `llvm/Support`, but actually those 
stuffs are only used for clang and clang-tblgen, so that's why we try to create 
`clang/Support`.

It's target specific but need to used in `clang` and `clang-tblgen` so target 
specific stuffs should putting that in `llvm/lib/Target/RISCV` in theory, but 
that made clang dependent on that.

Thanks :)


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[PATCH] D121984: [RISCV] Moving RVV intrinsic type related util to clang/Support

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 422783.
kito-cheng added a comment.

Fix comment in RISCVVIntrinsicUtils.h


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Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/CMakeLists.txt
  clang/lib/Support/CMakeLists.txt
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -14,6 +14,7 @@
 //
 //===--===//
 
+#include "clang/Support/RISCVVIntrinsicUtils.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/StringExtras.h"
@@ -25,206 +26,9 @@
 #include 
 
 using namespace llvm;
-using BasicType = char;
-using VScaleVal = Optional;
+using namespace clang::RISCV;
 
 namespace {
-
-// Exponential LMUL
-struct LMULType {
-  int Log2LMUL;
-  LMULType(int Log2LMUL);
-  // Return the C/C++ string representation of LMUL
-  std::string str() const;
-  Optional getScale(unsigned ElementBitwidth) const;
-  void MulLog2LMUL(int Log2LMUL);
-  LMULType &operator*=(uint32_t RHS);
-};
-
-// This class is compact representation of a valid and invalid RVVType.
-class RVVType {
-  enum ScalarTypeKind : uint32_t {
-Void,
-Size_t,
-Ptrdiff_t,
-UnsignedLong,
-SignedLong,
-Boolean,
-SignedInteger,
-UnsignedInteger,
-Float,
-Invalid,
-  };
-  BasicType BT;
-  ScalarTypeKind ScalarType = Invalid;
-  LMULType LMUL;
-  bool IsPointer = false;
-  // IsConstant indices are "int", but have the constant expression.
-  bool IsImmediate = false;
-  // Const qualifier for pointer to const object or object of const type.
-  bool IsConstant = false;
-  unsigned ElementBitwidth = 0;
-  VScaleVal Scale = 0;
-  bool Valid;
-
-  std::string BuiltinStr;
-  std::string ClangBuiltinStr;
-  std::string Str;
-  std::string ShortStr;
-
-public:
-  RVVType() : RVVType(BasicType(), 0, StringRef()) {}
-  RVVType(BasicType BT, int Log2LMUL, StringRef prototype);
-
-  // Return the string representation of a type, which is an encoded string for
-  // passing to the BUILTIN() macro in Builtins.def.
-  const std::string &getBuiltinStr() const { return BuiltinStr; }
-
-  // Return the clang builtin type for RVV vector type which are used in the
-  // riscv_vector.h header file.
-  const std::string &getClangBuiltinStr() const { return ClangBuiltinStr; }
-
-  // Return the C/C++ string representation of a type for use in the
-  // riscv_vector.h header file.
-  const std::string &getTypeStr() const { return Str; }
-
-  // Return the short name of a type for C/C++ name suffix.
-  const std::string &getShortStr() {
-// Not all types are used in short name, so compute the short name by
-// demanded.
-if (ShortStr.empty())
-  initShortStr();
-return ShortStr;
-  }
-
-  bool isValid() const { return Valid; }
-  bool isScalar() const { return Scale.hasValue() && Scale.getValue() == 0; }
-  bool isVector() const { return Scale.hasValue() && Scale.getValue() != 0; }
-  bool isVector(unsigned Width) const {
-return isVector() && ElementBitwidth == Width;
-  }
-  bool isFloat() const { return ScalarType == ScalarTypeKind::Float; }
-  bool isSignedInteger() const {
-return ScalarType == ScalarTypeKind::SignedInteger;
-  }
-  bool isFloatVector(unsigned Width) const {
-return isVector() && isFloat() && ElementBitwidth == Width;
-  }
-  bool isFloat(unsigned Width) const {
-return isFloat() && ElementBitwidth == Width;
-  }
-
-private:
-  // Verify RVV vector type and set Valid.
-  bool verifyType() const;
-
-  // Creates a type based on basic types of TypeRange
-  void applyBasicType();
-
-  // Applies a prototype modifier to the current type. The result maybe an
-  // invalid type.
-  void applyModifier(StringRef prototype);
-
-  // Compute and record a string for legal type.
-  void initBuiltinStr();
-  // Compute and record a builtin RVV vector type string.
-  void initClangBuiltinStr();
-  // Compute and record a type string for used in the header.
-  void initTypeStr();
-  // Compute and record a short name of a type for C/C++ name suffix.
-  void initShortStr();
-};
-
-using RVVTypePtr = RVVType *;
-using RVVTypes = std::vector;
-using RISCVPredefinedMacroT = uint8_t;
-
-enum RISCVPredefinedMacro : RISCVPredefinedMacroT {
-  Basic = 0,
-  V = 1 << 1,
-  Zvfh = 1 << 2,
-  RV64 = 1 << 3,
-  VectorMaxELen64 = 1 << 4,
-  VectorMaxELenFp32 = 1 << 5,
-  VectorMaxELenFp64 = 1 << 6,
-};
-
-enum PolicyScheme : uint8_t {
-  SchemeNone,
-  HasPassthruOperand,
-  HasPolicyOperand,
-};
-
-// TODO refactor RVVIntrinsic class design after support all intrinsic
-// combination. This r

[PATCH] D121984: [RISCV] Moving RVV intrinsic type related util to clang/Support

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 422786.
kito-cheng marked an inline comment as done.
kito-cheng added a comment.

Fix comment in RISCVVIntrinsicUtils.h...again :P


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Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/CMakeLists.txt
  clang/lib/Support/CMakeLists.txt
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -14,6 +14,7 @@
 //
 //===--===//
 
+#include "clang/Support/RISCVVIntrinsicUtils.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/StringExtras.h"
@@ -25,206 +26,9 @@
 #include 
 
 using namespace llvm;
-using BasicType = char;
-using VScaleVal = Optional;
+using namespace clang::RISCV;
 
 namespace {
-
-// Exponential LMUL
-struct LMULType {
-  int Log2LMUL;
-  LMULType(int Log2LMUL);
-  // Return the C/C++ string representation of LMUL
-  std::string str() const;
-  Optional getScale(unsigned ElementBitwidth) const;
-  void MulLog2LMUL(int Log2LMUL);
-  LMULType &operator*=(uint32_t RHS);
-};
-
-// This class is compact representation of a valid and invalid RVVType.
-class RVVType {
-  enum ScalarTypeKind : uint32_t {
-Void,
-Size_t,
-Ptrdiff_t,
-UnsignedLong,
-SignedLong,
-Boolean,
-SignedInteger,
-UnsignedInteger,
-Float,
-Invalid,
-  };
-  BasicType BT;
-  ScalarTypeKind ScalarType = Invalid;
-  LMULType LMUL;
-  bool IsPointer = false;
-  // IsConstant indices are "int", but have the constant expression.
-  bool IsImmediate = false;
-  // Const qualifier for pointer to const object or object of const type.
-  bool IsConstant = false;
-  unsigned ElementBitwidth = 0;
-  VScaleVal Scale = 0;
-  bool Valid;
-
-  std::string BuiltinStr;
-  std::string ClangBuiltinStr;
-  std::string Str;
-  std::string ShortStr;
-
-public:
-  RVVType() : RVVType(BasicType(), 0, StringRef()) {}
-  RVVType(BasicType BT, int Log2LMUL, StringRef prototype);
-
-  // Return the string representation of a type, which is an encoded string for
-  // passing to the BUILTIN() macro in Builtins.def.
-  const std::string &getBuiltinStr() const { return BuiltinStr; }
-
-  // Return the clang builtin type for RVV vector type which are used in the
-  // riscv_vector.h header file.
-  const std::string &getClangBuiltinStr() const { return ClangBuiltinStr; }
-
-  // Return the C/C++ string representation of a type for use in the
-  // riscv_vector.h header file.
-  const std::string &getTypeStr() const { return Str; }
-
-  // Return the short name of a type for C/C++ name suffix.
-  const std::string &getShortStr() {
-// Not all types are used in short name, so compute the short name by
-// demanded.
-if (ShortStr.empty())
-  initShortStr();
-return ShortStr;
-  }
-
-  bool isValid() const { return Valid; }
-  bool isScalar() const { return Scale.hasValue() && Scale.getValue() == 0; }
-  bool isVector() const { return Scale.hasValue() && Scale.getValue() != 0; }
-  bool isVector(unsigned Width) const {
-return isVector() && ElementBitwidth == Width;
-  }
-  bool isFloat() const { return ScalarType == ScalarTypeKind::Float; }
-  bool isSignedInteger() const {
-return ScalarType == ScalarTypeKind::SignedInteger;
-  }
-  bool isFloatVector(unsigned Width) const {
-return isVector() && isFloat() && ElementBitwidth == Width;
-  }
-  bool isFloat(unsigned Width) const {
-return isFloat() && ElementBitwidth == Width;
-  }
-
-private:
-  // Verify RVV vector type and set Valid.
-  bool verifyType() const;
-
-  // Creates a type based on basic types of TypeRange
-  void applyBasicType();
-
-  // Applies a prototype modifier to the current type. The result maybe an
-  // invalid type.
-  void applyModifier(StringRef prototype);
-
-  // Compute and record a string for legal type.
-  void initBuiltinStr();
-  // Compute and record a builtin RVV vector type string.
-  void initClangBuiltinStr();
-  // Compute and record a type string for used in the header.
-  void initTypeStr();
-  // Compute and record a short name of a type for C/C++ name suffix.
-  void initShortStr();
-};
-
-using RVVTypePtr = RVVType *;
-using RVVTypes = std::vector;
-using RISCVPredefinedMacroT = uint8_t;
-
-enum RISCVPredefinedMacro : RISCVPredefinedMacroT {
-  Basic = 0,
-  V = 1 << 1,
-  Zvfh = 1 << 2,
-  RV64 = 1 << 3,
-  VectorMaxELen64 = 1 << 4,
-  VectorMaxELenFp32 = 1 << 5,
-  VectorMaxELenFp64 = 1 << 6,
-};
-
-enum PolicyScheme : uint8_t {
-  SchemeNone,
-  HasPassthruOperand,
-  HasPolicyOperand,
-};
-
-// TODO refactor RVVIntrinsic class de

[PATCH] D121984: [RISCV] Moving RVV intrinsic type related util to clang/Support

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

> Thank you for the explanation. I still don't think this is really "Support" 
> material, but I'm also struggling to think of a better place to put it in an 
> existing directory in Clang aside from Basic, but that would still be a bit 
> of a layering violation it feels like. So I think I'm convinced that Support 
> is a reasonable place to put it.

Actually I tried to put that on clang/Basic before, and end up with the 
clang/Basic is depended on clang-tblgen, and that made clang-tblgen depend on 
clang/Basic...then CMake report error for circular dependency :P

> Should it live within a RISCV direction inside of the Support directory? Or 
> should we use folders like that for host platform support files instead of 
> target platform support files (as the LLVM Support directory appears to do)?

I saw LLVM/Support are just target specific file on the folder instead of many 
target folder, I guess there should not be too much target specific files in 
clang/Support, and we could reorg the folder organization once it getting 
complicated? What do you think?


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[PATCH] D121984: [RISCV] Moving RVV intrinsic type related util to clang/Support

[Kito Cheng via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGf26c41e8dd28: [RISCV] Moving RVV intrinsic type related util 
to clang/Support (authored by kito-cheng).

Changed prior to commit:
  https://reviews.llvm.org/D121984?vs=422786&id=423887#toc

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Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/CMakeLists.txt
  clang/lib/Support/CMakeLists.txt
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/CMakeLists.txt
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -14,6 +14,7 @@
 //
 //===--===//
 
+#include "clang/Support/RISCVVIntrinsicUtils.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/StringExtras.h"
@@ -25,206 +26,9 @@
 #include 
 
 using namespace llvm;
-using BasicType = char;
-using VScaleVal = Optional;
+using namespace clang::RISCV;
 
 namespace {
-
-// Exponential LMUL
-struct LMULType {
-  int Log2LMUL;
-  LMULType(int Log2LMUL);
-  // Return the C/C++ string representation of LMUL
-  std::string str() const;
-  Optional getScale(unsigned ElementBitwidth) const;
-  void MulLog2LMUL(int Log2LMUL);
-  LMULType &operator*=(uint32_t RHS);
-};
-
-// This class is compact representation of a valid and invalid RVVType.
-class RVVType {
-  enum ScalarTypeKind : uint32_t {
-Void,
-Size_t,
-Ptrdiff_t,
-UnsignedLong,
-SignedLong,
-Boolean,
-SignedInteger,
-UnsignedInteger,
-Float,
-Invalid,
-  };
-  BasicType BT;
-  ScalarTypeKind ScalarType = Invalid;
-  LMULType LMUL;
-  bool IsPointer = false;
-  // IsConstant indices are "int", but have the constant expression.
-  bool IsImmediate = false;
-  // Const qualifier for pointer to const object or object of const type.
-  bool IsConstant = false;
-  unsigned ElementBitwidth = 0;
-  VScaleVal Scale = 0;
-  bool Valid;
-
-  std::string BuiltinStr;
-  std::string ClangBuiltinStr;
-  std::string Str;
-  std::string ShortStr;
-
-public:
-  RVVType() : RVVType(BasicType(), 0, StringRef()) {}
-  RVVType(BasicType BT, int Log2LMUL, StringRef prototype);
-
-  // Return the string representation of a type, which is an encoded string for
-  // passing to the BUILTIN() macro in Builtins.def.
-  const std::string &getBuiltinStr() const { return BuiltinStr; }
-
-  // Return the clang builtin type for RVV vector type which are used in the
-  // riscv_vector.h header file.
-  const std::string &getClangBuiltinStr() const { return ClangBuiltinStr; }
-
-  // Return the C/C++ string representation of a type for use in the
-  // riscv_vector.h header file.
-  const std::string &getTypeStr() const { return Str; }
-
-  // Return the short name of a type for C/C++ name suffix.
-  const std::string &getShortStr() {
-// Not all types are used in short name, so compute the short name by
-// demanded.
-if (ShortStr.empty())
-  initShortStr();
-return ShortStr;
-  }
-
-  bool isValid() const { return Valid; }
-  bool isScalar() const { return Scale.hasValue() && Scale.getValue() == 0; }
-  bool isVector() const { return Scale.hasValue() && Scale.getValue() != 0; }
-  bool isVector(unsigned Width) const {
-return isVector() && ElementBitwidth == Width;
-  }
-  bool isFloat() const { return ScalarType == ScalarTypeKind::Float; }
-  bool isSignedInteger() const {
-return ScalarType == ScalarTypeKind::SignedInteger;
-  }
-  bool isFloatVector(unsigned Width) const {
-return isVector() && isFloat() && ElementBitwidth == Width;
-  }
-  bool isFloat(unsigned Width) const {
-return isFloat() && ElementBitwidth == Width;
-  }
-
-private:
-  // Verify RVV vector type and set Valid.
-  bool verifyType() const;
-
-  // Creates a type based on basic types of TypeRange
-  void applyBasicType();
-
-  // Applies a prototype modifier to the current type. The result maybe an
-  // invalid type.
-  void applyModifier(StringRef prototype);
-
-  // Compute and record a string for legal type.
-  void initBuiltinStr();
-  // Compute and record a builtin RVV vector type string.
-  void initClangBuiltinStr();
-  // Compute and record a type string for used in the header.
-  void initTypeStr();
-  // Compute and record a short name of a type for C/C++ name suffix.
-  void initShortStr();
-};
-
-using RVVTypePtr = RVVType *;
-using RVVTypes = std::vector;
-using RISCVPredefinedMacroT = uint8_t;
-
-enum RISCVPredefinedMacro : RISCVPredefinedMacroT {
-  Basic = 0,
-  V = 1 << 1,
-  Zvfh = 1 << 2,
-  RV64 = 1 << 3,
-  VectorMaxELen64 = 1 << 4,
-  VectorMaxELenFp32 = 1 << 5,
-  Vec

[PATCH] D118225: [RISCV] Decouple Zve* extensions.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

Discussion on riscv-v-spec : 
https://github.com/riscv/riscv-v-spec/issues/723#issuecomment-922153867, 
although v-spec and isa-spec still not clearly describe that, but seems ISA 
folks prefer having those implication relationship between those zve* and v 
extensions.


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[PATCH] D119250: [RISCV][NFC] Refactor RISCVISAInfo.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng accepted this revision.
kito-cheng added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D119837: [RISCV] Fix the include search path order between sysroot and resource folder

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng created this revision.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, 
Jim, benna, psnobl, abidh, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, 
rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, 
rbar, asb.
kito-cheng requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: clang.

Resource folder[1] should include before sysroot[2] in general (Linux clang
toolchain, BareMetal clang toolchain, and GCC using that order), and that
prevent sysroot's header file override resource folder's one, this change is
reference from BareMetal::addclangsystemincludea...@baremetal.cpp[3].

And also fix the behavior of `-nobuiltininc`.

[1] Include path from resource folder is something like this: 
`/lib/clang/13.0.0/include/`
[2] Include path from sysroot is something like this: 
`/riscv32-unknown-elf/include`
[3] 
https://github.com/llvm/llvm-project/blob/llvmorg-13.0.1/clang/lib/Driver/ToolChains/BareMetal.cpp#L193


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Files:
  clang/lib/Driver/ToolChains/RISCVToolchain.cpp
  clang/test/Driver/Inputs/resource_dir/include/.keep
  clang/test/Driver/riscv32-toolchain.c
  clang/test/Driver/riscv64-toolchain.c


Index: clang/test/Driver/riscv64-toolchain.c
===
--- clang/test/Driver/riscv64-toolchain.c
+++ clang/test/Driver/riscv64-toolchain.c
@@ -153,6 +153,20 @@
 // C-RV64-RTLIB-COMPILERRT-LP64: "--start-group" "-lc" "-lgloss" "--end-group" 
"{{.*}}libclang_rt.builtins-riscv64.a"
 // C-RV64-RTLIB-COMPILERRT-LP64: "{{.*}}clang_rt.crtend-riscv64.o"
 
+// RUN: %clang %s -### -no-canonical-prefixes -target riscv64 \
+// RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
+// RUN:   -resource-dir=%s/Inputs/resource_dir 2>&1 \
+// RUN:   | FileCheck -check-prefix=RESOURCE-INC %s
+// RESOURCE-INC: "-internal-isystem" "{{.*}}/Inputs/resource_dir/include"
+// RESOURCE-INC: "-internal-isystem" 
"{{.*}}/basic_riscv64_tree/{{.*}}/riscv64-unknown-elf/include"
+
+// RUN: %clang %s -### -no-canonical-prefixes -target riscv64 \
+// RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
+// RUN:   -resource-dir=%s/Inputs/resource_dir -nobuiltininc 2>&1 \
+// RUN:   | FileCheck -check-prefix=NO-RESOURCE-INC %s
+// NO-RESOURCE-INC-NOT: "-internal-isystem" "{{.*}}Inputs/resource_dir/include"
+// NO-RESOURCE-INC: "-internal-isystem" 
"{{.*}}/basic_riscv64_tree/{{.*}}/riscv64-unknown-elf/include"
+
 // RUN: %clang -target riscv64 %s -emit-llvm -S -o - | FileCheck %s
 
 typedef __builtin_va_list va_list;
Index: clang/test/Driver/riscv32-toolchain.c
===
--- clang/test/Driver/riscv32-toolchain.c
+++ clang/test/Driver/riscv32-toolchain.c
@@ -197,6 +197,20 @@
 // C-RV32-RTLIB-COMPILERRT-ILP32: "--start-group" "-lc" "-lgloss" 
"--end-group" "{{.*}}libclang_rt.builtins-riscv32.a"
 // C-RV32-RTLIB-COMPILERRT-ILP32: "{{.*}}clang_rt.crtend-riscv32.o"
 
+// RUN: %clang %s -### -no-canonical-prefixes -target riscv32 \
+// RUN:   --gcc-toolchain=%S/Inputs/basic_riscv32_tree \
+// RUN:   -resource-dir=%s/Inputs/resource_dir 2>&1 \
+// RUN:   | FileCheck -check-prefix=RESOURCE-INC %s
+// RESOURCE-INC: "-internal-isystem" "{{.*}}/Inputs/resource_dir/include"
+// RESOURCE-INC: "-internal-isystem" 
"{{.*}}/basic_riscv32_tree/{{.*}}/riscv32-unknown-elf/include"
+
+// RUN: %clang %s -### -no-canonical-prefixes -target riscv32 \
+// RUN:   --gcc-toolchain=%S/Inputs/basic_riscv32_tree \
+// RUN:   -resource-dir=%s/Inputs/resource_dir -nobuiltininc 2>&1 \
+// RUN:   | FileCheck -check-prefix=NO-RESOURCE-INC %s
+// NO-RESOURCE-INC-NOT: "-internal-isystem" 
"{{.*}}/Inputs/resource_dir/include"
+// NO-RESOURCE-INC: "-internal-isystem" 
"{{.*}}/basic_riscv32_tree/{{.*}}/riscv32-unknown-elf/include"
+
 // RUN: %clang -target riscv32 %s -emit-llvm -S -o - | FileCheck %s
 
 typedef __builtin_va_list va_list;
Index: clang/lib/Driver/ToolChains/RISCVToolchain.cpp
===
--- clang/lib/Driver/ToolChains/RISCVToolchain.cpp
+++ clang/lib/Driver/ToolChains/RISCVToolchain.cpp
@@ -98,6 +98,12 @@
   if (DriverArgs.hasArg(options::OPT_nostdinc))
 return;
 
+  if (!DriverArgs.hasArg(options::OPT_nobuiltininc)) {
+SmallString<128> Dir(getDriver().ResourceDir);
+llvm::sys::path::append(Dir, "include");
+addSystemInclude(DriverArgs, CC1Args, Dir.str());
+  }
+
   if (!DriverArgs.hasArg(options::OPT_nostdlibinc)) {
 SmallString<128> Dir(computeSysRoot());
 llvm::sys::path::append(Dir, "include");


Index: clang/test/Driver/riscv64-toolchain.c
===
--- clang/test/Driver/riscv64-toolchain.c
+++ clang/test/Driver/riscv64-toolchain.c
@

[PATCH] D124348: [1/2][RISCV]Add Intrinsics for B extension in Clang

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

> And I want to know that do you have any documents about intrinsic of bitmanip 
> extension, like RISC-V Vector Extension Intrinsic Document.

No, we didn't a formal document for that, I expect we will have one once this 
finalized https://github.com/riscv-non-isa/riscv-c-api-doc/pull/25 ...


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[PATCH] D124509: [RISCV] Fix int16 -> __fp16 conversion code gen

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng created this revision.
Herald added subscribers: sunshaoce, VincentWu, luke957, vkmr, frasercrmck, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, arichardson.
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Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: clang.

clang emit wrong code sequence for int16(short) to __fp16 conversion,
and that should fix the code gen directly is the right way I think,
but I found there is a FIXME comment in clang/Basic/TargetInfo.h say
that's should be removed in future so I think just let swich to using
generic LLVM IR rather than llvm.convert.to.fp16 intrinsics code gen
path is enough, and the code gen apperantly more concise for __fp16 to
int16 conversion.

  /// Check whether llvm intrinsics such as llvm.convert.to.fp16 should be used
  /// to convert to and from __fp16.
  /// FIXME: This function should be removed once all targets stop using the
  /// conversion intrinsics.
  virtual bool useFP16ConversionIntrinsics() const {
return true;
  }


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D124509

Files:
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/__fp16-convert.c


Index: clang/test/CodeGen/RISCV/__fp16-convert.c
===
--- clang/test/CodeGen/RISCV/__fp16-convert.c
+++ clang/test/CodeGen/RISCV/__fp16-convert.c
@@ -6,10 +6,10 @@
 short z;
 // CHECK-LABEL: @bar1(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = load i16, ptr @y, align 2
-// CHECK-NEXT:[[TMP1:%.*]] = call float @llvm.convert.from.fp16.f32(i16 
[[TMP0]])
-// CHECK-NEXT:[[CONV:%.*]] = fptosi float [[TMP1]] to i16
-// CHECK-NEXT:store i16 [[CONV]], ptr @z, align 2
+// CHECK-NEXT:[[TMP0:%.*]] = load half, ptr @y, align 2
+// CHECK-NEXT:[[CONV:%.*]] = fpext half [[TMP0]] to float
+// CHECK-NEXT:[[CONV1:%.*]] = fptosi float [[CONV]] to i16
+// CHECK-NEXT:store i16 [[CONV1]], ptr @z, align 2
 // CHECK-NEXT:ret void
 //
 void bar1(){
@@ -18,7 +18,9 @@
 // CHECK-LABEL: @bar2(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = load i16, ptr @z, align 2
-// CHECK-NEXT:store i16 [[TMP0]], ptr @y, align 2
+// CHECK-NEXT:[[CONV:%.*]] = sitofp i16 [[TMP0]] to float
+// CHECK-NEXT:[[CONV1:%.*]] = fptrunc float [[CONV]] to half
+// CHECK-NEXT:store half [[CONV1]], ptr @y, align 2
 // CHECK-NEXT:ret void
 //
 void bar2(){
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -96,6 +96,10 @@
 DiagnosticsEngine &Diags) override;
 
   bool hasBitIntType() const override { return true; }
+
+  bool useFP16ConversionIntrinsics() const override {
+return false;
+  }
 };
 class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
 public:


Index: clang/test/CodeGen/RISCV/__fp16-convert.c
===
--- clang/test/CodeGen/RISCV/__fp16-convert.c
+++ clang/test/CodeGen/RISCV/__fp16-convert.c
@@ -6,10 +6,10 @@
 short z;
 // CHECK-LABEL: @bar1(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = load i16, ptr @y, align 2
-// CHECK-NEXT:[[TMP1:%.*]] = call float @llvm.convert.from.fp16.f32(i16 [[TMP0]])
-// CHECK-NEXT:[[CONV:%.*]] = fptosi float [[TMP1]] to i16
-// CHECK-NEXT:store i16 [[CONV]], ptr @z, align 2
+// CHECK-NEXT:[[TMP0:%.*]] = load half, ptr @y, align 2
+// CHECK-NEXT:[[CONV:%.*]] = fpext half [[TMP0]] to float
+// CHECK-NEXT:[[CONV1:%.*]] = fptosi float [[CONV]] to i16
+// CHECK-NEXT:store i16 [[CONV1]], ptr @z, align 2
 // CHECK-NEXT:ret void
 //
 void bar1(){
@@ -18,7 +18,9 @@
 // CHECK-LABEL: @bar2(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = load i16, ptr @z, align 2
-// CHECK-NEXT:store i16 [[TMP0]], ptr @y, align 2
+// CHECK-NEXT:[[CONV:%.*]] = sitofp i16 [[TMP0]] to float
+// CHECK-NEXT:[[CONV1:%.*]] = fptrunc float [[CONV]] to half
+// CHECK-NEXT:store half [[CONV1]], ptr @y, align 2
 // CHECK-NEXT:ret void
 //
 void bar2(){
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -96,6 +96,10 @@
 DiagnosticsEngine &Diags) override;
 
   bool hasBitIntType() const override { return true; }
+
+  bool useFP16ConversionIntrinsics() const override {
+return false;
+  }
 };
 class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
 public:
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[PATCH] D124510: [RISCV] Precommit test for D124509

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng created this revision.
Herald added subscribers: sunshaoce, VincentWu, luke957, vkmr, frasercrmck, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, arichardson.
Herald added a project: All.
kito-cheng requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: clang.

Test case to show the wrong code gen for `int16` -> `__fp16` conversion,
clang just emit a load and store without did conversion in the case,

and another case used for demonstrate the code gen improvement of `__fp16`
-> `int16`.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D124510

Files:
  clang/test/CodeGen/RISCV/__fp16-convert.c


Index: clang/test/CodeGen/RISCV/__fp16-convert.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/__fp16-convert.c
@@ -0,0 +1,26 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -emit-llvm %s -o - \
+// RUN:   | FileCheck %s
+
+__fp16 y;
+short z;
+// CHECK-LABEL: @bar1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load i16, ptr @y, align 2
+// CHECK-NEXT:[[TMP1:%.*]] = call float @llvm.convert.from.fp16.f32(i16 
[[TMP0]])
+// CHECK-NEXT:[[CONV:%.*]] = fptosi float [[TMP1]] to i16
+// CHECK-NEXT:store i16 [[CONV]], ptr @z, align 2
+// CHECK-NEXT:ret void
+//
+void bar1(){
+z = y;
+}
+// CHECK-LABEL: @bar2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load i16, ptr @z, align 2
+// CHECK-NEXT:store i16 [[TMP0]], ptr @y, align 2
+// CHECK-NEXT:ret void
+//
+void bar2(){
+y = z;
+}


Index: clang/test/CodeGen/RISCV/__fp16-convert.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/__fp16-convert.c
@@ -0,0 +1,26 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -emit-llvm %s -o - \
+// RUN:   | FileCheck %s
+
+__fp16 y;
+short z;
+// CHECK-LABEL: @bar1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load i16, ptr @y, align 2
+// CHECK-NEXT:[[TMP1:%.*]] = call float @llvm.convert.from.fp16.f32(i16 [[TMP0]])
+// CHECK-NEXT:[[CONV:%.*]] = fptosi float [[TMP1]] to i16
+// CHECK-NEXT:store i16 [[CONV]], ptr @z, align 2
+// CHECK-NEXT:ret void
+//
+void bar1(){
+z = y;
+}
+// CHECK-LABEL: @bar2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load i16, ptr @z, align 2
+// CHECK-NEXT:store i16 [[TMP0]], ptr @y, align 2
+// CHECK-NEXT:ret void
+//
+void bar2(){
+y = z;
+}
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[PATCH] D124510: [RISCV] Precommit test for D124509

[Kito Cheng via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG02c7de3a4c32: [RISCV] Precommit test for D124509 (authored 
by kito-cheng).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124510/new/

https://reviews.llvm.org/D124510

Files:
  clang/test/CodeGen/RISCV/__fp16-convert.c


Index: clang/test/CodeGen/RISCV/__fp16-convert.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/__fp16-convert.c
@@ -0,0 +1,26 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -emit-llvm %s -o - \
+// RUN:   | FileCheck %s
+
+__fp16 y;
+short z;
+// CHECK-LABEL: @bar1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load i16, ptr @y, align 2
+// CHECK-NEXT:[[TMP1:%.*]] = call float @llvm.convert.from.fp16.f32(i16 
[[TMP0]])
+// CHECK-NEXT:[[CONV:%.*]] = fptosi float [[TMP1]] to i16
+// CHECK-NEXT:store i16 [[CONV]], ptr @z, align 2
+// CHECK-NEXT:ret void
+//
+void bar1(){
+z = y;
+}
+// CHECK-LABEL: @bar2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load i16, ptr @z, align 2
+// CHECK-NEXT:store i16 [[TMP0]], ptr @y, align 2
+// CHECK-NEXT:ret void
+//
+void bar2(){
+y = z;
+}


Index: clang/test/CodeGen/RISCV/__fp16-convert.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/__fp16-convert.c
@@ -0,0 +1,26 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -emit-llvm %s -o - \
+// RUN:   | FileCheck %s
+
+__fp16 y;
+short z;
+// CHECK-LABEL: @bar1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load i16, ptr @y, align 2
+// CHECK-NEXT:[[TMP1:%.*]] = call float @llvm.convert.from.fp16.f32(i16 [[TMP0]])
+// CHECK-NEXT:[[CONV:%.*]] = fptosi float [[TMP1]] to i16
+// CHECK-NEXT:store i16 [[CONV]], ptr @z, align 2
+// CHECK-NEXT:ret void
+//
+void bar1(){
+z = y;
+}
+// CHECK-LABEL: @bar2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load i16, ptr @z, align 2
+// CHECK-NEXT:store i16 [[TMP0]], ptr @y, align 2
+// CHECK-NEXT:ret void
+//
+void bar2(){
+y = z;
+}
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[PATCH] D124509: [RISCV] Fix int16 -> __fp16 conversion code gen

[Kito Cheng via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG41b951c92931: [RISCV] Fix int16 -> __fp16 conversion code 
gen (authored by kito-cheng).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124509/new/

https://reviews.llvm.org/D124509

Files:
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/__fp16-convert.c


Index: clang/test/CodeGen/RISCV/__fp16-convert.c
===
--- clang/test/CodeGen/RISCV/__fp16-convert.c
+++ clang/test/CodeGen/RISCV/__fp16-convert.c
@@ -6,10 +6,10 @@
 short z;
 // CHECK-LABEL: @bar1(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = load i16, ptr @y, align 2
-// CHECK-NEXT:[[TMP1:%.*]] = call float @llvm.convert.from.fp16.f32(i16 
[[TMP0]])
-// CHECK-NEXT:[[CONV:%.*]] = fptosi float [[TMP1]] to i16
-// CHECK-NEXT:store i16 [[CONV]], ptr @z, align 2
+// CHECK-NEXT:[[TMP0:%.*]] = load half, ptr @y, align 2
+// CHECK-NEXT:[[CONV:%.*]] = fpext half [[TMP0]] to float
+// CHECK-NEXT:[[CONV1:%.*]] = fptosi float [[CONV]] to i16
+// CHECK-NEXT:store i16 [[CONV1]], ptr @z, align 2
 // CHECK-NEXT:ret void
 //
 void bar1(){
@@ -18,7 +18,9 @@
 // CHECK-LABEL: @bar2(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = load i16, ptr @z, align 2
-// CHECK-NEXT:store i16 [[TMP0]], ptr @y, align 2
+// CHECK-NEXT:[[CONV:%.*]] = sitofp i16 [[TMP0]] to float
+// CHECK-NEXT:[[CONV1:%.*]] = fptrunc float [[CONV]] to half
+// CHECK-NEXT:store half [[CONV1]], ptr @y, align 2
 // CHECK-NEXT:ret void
 //
 void bar2(){
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -96,6 +96,10 @@
 DiagnosticsEngine &Diags) override;
 
   bool hasBitIntType() const override { return true; }
+
+  bool useFP16ConversionIntrinsics() const override {
+return false;
+  }
 };
 class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
 public:


Index: clang/test/CodeGen/RISCV/__fp16-convert.c
===
--- clang/test/CodeGen/RISCV/__fp16-convert.c
+++ clang/test/CodeGen/RISCV/__fp16-convert.c
@@ -6,10 +6,10 @@
 short z;
 // CHECK-LABEL: @bar1(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = load i16, ptr @y, align 2
-// CHECK-NEXT:[[TMP1:%.*]] = call float @llvm.convert.from.fp16.f32(i16 [[TMP0]])
-// CHECK-NEXT:[[CONV:%.*]] = fptosi float [[TMP1]] to i16
-// CHECK-NEXT:store i16 [[CONV]], ptr @z, align 2
+// CHECK-NEXT:[[TMP0:%.*]] = load half, ptr @y, align 2
+// CHECK-NEXT:[[CONV:%.*]] = fpext half [[TMP0]] to float
+// CHECK-NEXT:[[CONV1:%.*]] = fptosi float [[CONV]] to i16
+// CHECK-NEXT:store i16 [[CONV1]], ptr @z, align 2
 // CHECK-NEXT:ret void
 //
 void bar1(){
@@ -18,7 +18,9 @@
 // CHECK-LABEL: @bar2(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = load i16, ptr @z, align 2
-// CHECK-NEXT:store i16 [[TMP0]], ptr @y, align 2
+// CHECK-NEXT:[[CONV:%.*]] = sitofp i16 [[TMP0]] to float
+// CHECK-NEXT:[[CONV1:%.*]] = fptrunc float [[CONV]] to half
+// CHECK-NEXT:store half [[CONV1]], ptr @y, align 2
 // CHECK-NEXT:ret void
 //
 void bar2(){
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -96,6 +96,10 @@
 DiagnosticsEngine &Diags) override;
 
   bool hasBitIntType() const override { return true; }
+
+  bool useFP16ConversionIntrinsics() const override {
+return false;
+  }
 };
 class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
 public:
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[PATCH] D124730: [RISCV][NFC] Refactor RISC-V vector intrinsic utils.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng created this revision.
Herald added subscribers: sunshaoce, VincentWu, luke957, vkmr, frasercrmck, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, arichardson.
Herald added a project: All.
kito-cheng requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: clang.

This patch is preparation for D111617 , use 
class/struct/enum rather than
char/StringRef to present internal information as possible, that provide
more compact way to store those info and also easier to
serialize/deserialize.

And also that improve readability of the code, e.g. "v" vs
TypeProfile::Vector.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D124730

Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -48,7 +48,7 @@
   /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
   void createCodeGen(raw_ostream &o);
 
-  std::string getSuffixStr(char Type, int Log2LMUL, StringRef Prototypes);
+  std::string getSuffixStr(BasicType Type, int Log2LMUL, StringRef Prototypes);
 
 private:
   /// Create all intrinsics and add them to \p Out
@@ -60,8 +60,9 @@
   /// or illegal set to avoid compute the  same config again. The result maybe
   /// have illegal RVVType.
   Optional computeTypes(BasicType BT, int Log2LMUL, unsigned NF,
-  ArrayRef PrototypeSeq);
-  Optional computeType(BasicType BT, int Log2LMUL, StringRef Proto);
+  ArrayRef PrototypeSeq);
+  Optional computeType(BasicType BT, int Log2LMUL,
+   TypeProfile Proto);
 
   /// Emit Acrh predecessor definitions and body, assume the element of Defs are
   /// sorted by extension.
@@ -76,11 +77,40 @@
   // Slice Prototypes string into sub prototype string and process each sub
   // prototype string individually in the Handler.
   void parsePrototypes(StringRef Prototypes,
-   std::function Handler);
+   std::function Handler);
 };
 
 } // namespace
 
+static BasicType ParseBasicType(char c) {
+  switch (c) {
+  case 'c':
+return BasicType::Int8;
+break;
+  case 's':
+return BasicType::Int16;
+break;
+  case 'i':
+return BasicType::Int32;
+break;
+  case 'l':
+return BasicType::Int64;
+break;
+  case 'x':
+return BasicType::Float16;
+break;
+  case 'f':
+return BasicType::Float32;
+break;
+  case 'd':
+return BasicType::Float64;
+break;
+
+  default:
+return BasicType::Unknown;
+  }
+}
+
 void emitCodeGenSwitchBody(const RVVIntrinsic *RVVI, raw_ostream &OS) {
   if (!RVVI->getIRName().empty())
 OS << "  ID = Intrinsic::riscv_" + RVVI->getIRName() + ";\n";
@@ -202,24 +232,27 @@
   constexpr int Log2LMULs[] = {-3, -2, -1, 0, 1, 2, 3};
   // Print RVV boolean types.
   for (int Log2LMUL : Log2LMULs) {
-auto T = computeType('c', Log2LMUL, "m");
+auto T = computeType(BasicType::Int8, Log2LMUL, TypeProfile::Mask);
 if (T.hasValue())
   printType(T.getValue());
   }
   // Print RVV int/float types.
   for (char I : StringRef("csil")) {
+BasicType BT = ParseBasicType(I);
 for (int Log2LMUL : Log2LMULs) {
-  auto T = computeType(I, Log2LMUL, "v");
+  auto T = computeType(BT, Log2LMUL, TypeProfile::Vector);
   if (T.hasValue()) {
 printType(T.getValue());
-auto UT = computeType(I, Log2LMUL, "Uv");
+auto UT = computeType(
+BT, Log2LMUL,
+TypeProfile(PrimitiveType::Vector, TypeModifier::UnsignedInteger));
 printType(UT.getValue());
   }
 }
   }
   OS << "#if defined(__riscv_zvfh)\n";
   for (int Log2LMUL : Log2LMULs) {
-auto T = computeType('x', Log2LMUL, "v");
+auto T = computeType(BasicType::Float16, Log2LMUL, TypeProfile::Vector);
 if (T.hasValue())
   printType(T.getValue());
   }
@@ -227,7 +260,7 @@
 
   OS << "#if defined(__riscv_f)\n";
   for (int Log2LMUL : Log2LMULs) {
-auto T = computeType('f', Log2LMUL, "v");
+auto T = computeType(BasicType::Float32, Log2LMUL, TypeProfile::Vector);
 if (T.hasValue())
   printType(T.getValue());
   }
@@ -235,7 +268,7 @@
 
   OS << "#if defined(__riscv_d)\n";
   for (int Log2LMUL : Log2LMULs) {
-auto T = computeType('d', Log2LMUL, "v");
+auto T = computeType(BasicType::Float64, Log2LMUL, TypeProfile::Vector);
 if (T.hasValue())
   printType(T.getValue());
   }
@@ -360,7 +393,7 @@
 }
 
 void RVVEmitter::parsePr

[PATCH] D124730: [RISCV][NFC] Refactor RISC-V vector intrinsic utils.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 426276.
kito-cheng added a comment.

Changes:

- Extract more utils functions to RISCVVIntrinsicUtils


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124730/new/

https://reviews.llvm.org/D124730

Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -32,9 +32,6 @@
 class RVVEmitter {
 private:
   RecordKeeper &Records;
-  // Concat BasicType, LMUL and Proto as key
-  StringMap LegalTypes;
-  StringSet<> IllegalTypes;
 
 public:
   RVVEmitter(RecordKeeper &R) : Records(R) {}
@@ -48,20 +45,11 @@
   /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
   void createCodeGen(raw_ostream &o);
 
-  std::string getSuffixStr(char Type, int Log2LMUL, StringRef Prototypes);
-
 private:
   /// Create all intrinsics and add them to \p Out
   void createRVVIntrinsics(std::vector> &Out);
   /// Print HeaderCode in RVVHeader Record to \p Out
   void printHeaderCode(raw_ostream &OS);
-  /// Compute output and input types by applying different config (basic type
-  /// and LMUL with type transformers). It also record result of type in legal
-  /// or illegal set to avoid compute the  same config again. The result maybe
-  /// have illegal RVVType.
-  Optional computeTypes(BasicType BT, int Log2LMUL, unsigned NF,
-  ArrayRef PrototypeSeq);
-  Optional computeType(BasicType BT, int Log2LMUL, StringRef Proto);
 
   /// Emit Acrh predecessor definitions and body, assume the element of Defs are
   /// sorted by extension.
@@ -73,14 +61,39 @@
   // non-empty string.
   bool emitMacroRestrictionStr(RISCVPredefinedMacroT PredefinedMacros,
raw_ostream &o);
-  // Slice Prototypes string into sub prototype string and process each sub
-  // prototype string individually in the Handler.
-  void parsePrototypes(StringRef Prototypes,
-   std::function Handler);
 };
 
 } // namespace
 
+static BasicType ParseBasicType(char c) {
+  switch (c) {
+  case 'c':
+return BasicType::Int8;
+break;
+  case 's':
+return BasicType::Int16;
+break;
+  case 'i':
+return BasicType::Int32;
+break;
+  case 'l':
+return BasicType::Int64;
+break;
+  case 'x':
+return BasicType::Float16;
+break;
+  case 'f':
+return BasicType::Float32;
+break;
+  case 'd':
+return BasicType::Float64;
+break;
+
+  default:
+return BasicType::Unknown;
+  }
+}
+
 void emitCodeGenSwitchBody(const RVVIntrinsic *RVVI, raw_ostream &OS) {
   if (!RVVI->getIRName().empty())
 OS << "  ID = Intrinsic::riscv_" + RVVI->getIRName() + ";\n";
@@ -202,24 +215,28 @@
   constexpr int Log2LMULs[] = {-3, -2, -1, 0, 1, 2, 3};
   // Print RVV boolean types.
   for (int Log2LMUL : Log2LMULs) {
-auto T = computeType('c', Log2LMUL, "m");
+auto T = RVVType::computeType(BasicType::Int8, Log2LMUL, TypeProfile::Mask);
 if (T.hasValue())
   printType(T.getValue());
   }
   // Print RVV int/float types.
   for (char I : StringRef("csil")) {
+BasicType BT = ParseBasicType(I);
 for (int Log2LMUL : Log2LMULs) {
-  auto T = computeType(I, Log2LMUL, "v");
+  auto T = RVVType::computeType(BT, Log2LMUL, TypeProfile::Vector);
   if (T.hasValue()) {
 printType(T.getValue());
-auto UT = computeType(I, Log2LMUL, "Uv");
+auto UT = RVVType::computeType(
+BT, Log2LMUL,
+TypeProfile(PrimitiveType::Vector, TypeModifier::UnsignedInteger));
 printType(UT.getValue());
   }
 }
   }
   OS << "#if defined(__riscv_zvfh)\n";
   for (int Log2LMUL : Log2LMULs) {
-auto T = computeType('x', Log2LMUL, "v");
+auto T =
+RVVType::computeType(BasicType::Float16, Log2LMUL, TypeProfile::Vector);
 if (T.hasValue())
   printType(T.getValue());
   }
@@ -227,7 +244,8 @@
 
   OS << "#if defined(__riscv_f)\n";
   for (int Log2LMUL : Log2LMULs) {
-auto T = computeType('f', Log2LMUL, "v");
+auto T =
+RVVType::computeType(BasicType::Float32, Log2LMUL, TypeProfile::Vector);
 if (T.hasValue())
   printType(T.getValue());
   }
@@ -235,7 +253,8 @@
 
   OS << "#if defined(__riscv_d)\n";
   for (int Log2LMUL : Log2LMULs) {
-auto T = computeType('d', Log2LMUL, "v");
+auto T =
+RVVType::computeType(BasicType::Float64, Log2LMUL, TypeProfile::Vector);
 if (T.hasValue())
   printType(T.getValue());
   }
@@ -359,32 +378,6 @@
   OS << "\n";
 }
 
-void RVVEmitter::parsePrototypes(StringRef Prototypes,
- std::function Handler) {
-  const StringRef Primaries("evwqom0ztul");
-  while (!Prototypes.empty()) {
-size_t Idx = 

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 426281.
kito-cheng marked 2 inline comments as done.
kito-cheng added a comment.

Changes:

- Split out refactor part to D124730 .
- Add more comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111617/new/

https://reviews.llvm.org/D111617

Files:
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TokenKinds.def
  clang/include/clang/Parse/Parser.h
  clang/include/clang/Sema/Sema.h
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Parse/ParsePragma.cpp
  clang/lib/Sema/CMakeLists.txt
  clang/lib/Sema/SemaLookup.cpp
  clang/lib/Sema/SemaRVVLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -110,6 +110,7 @@
 void EmitRVVHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltins(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltinCG(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitRVVBuiltinSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 
 void EmitCdeHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitCdeBuiltinDef(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -88,6 +88,7 @@
   GenRISCVVectorHeader,
   GenRISCVVectorBuiltins,
   GenRISCVVectorBuiltinCG,
+  GenRISCVVectorBuiltinSema,
   GenAttrDocs,
   GenDiagDocs,
   GenOptDocs,
@@ -243,6 +244,8 @@
"Generate riscv_vector_builtins.inc for clang"),
 clEnumValN(GenRISCVVectorBuiltinCG, "gen-riscv-vector-builtin-codegen",
"Generate riscv_vector_builtin_cg.inc for clang"),
+clEnumValN(GenRISCVVectorBuiltinSema, "gen-riscv-vector-builtin-sema",
+   "Generate riscv_vector_builtin_sema.inc for clang"),
 clEnumValN(GenAttrDocs, "gen-attr-docs",
"Generate attribute documentation"),
 clEnumValN(GenDiagDocs, "gen-diag-docs",
@@ -458,6 +461,9 @@
   case GenRISCVVectorBuiltinCG:
 EmitRVVBuiltinCG(Records, OS);
 break;
+  case GenRISCVVectorBuiltinSema:
+EmitRVVBuiltinSema(Records, OS);
+break;
   case GenAttrDocs:
 EmitClangAttrDocs(Records, OS);
 break;
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -20,6 +20,7 @@
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/StringSet.h"
+#include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
@@ -29,9 +30,30 @@
 using namespace clang::RISCV;
 
 namespace {
+struct SemaRecord {
+  std::string Name;
+  std::string MangledName;
+  std::string TypeRange;
+  std::vector Log2LMULList;
+  std::vector RequiredFeatures;
+
+  SmallVector ProtoSeq;
+  SmallVector ProtoMaskSeq;
+  SmallVector SuffixProto;
+  SmallVector MangledSuffixProto;
+
+  unsigned NF;
+};
+
 class RVVEmitter {
 private:
   RecordKeeper &Records;
+  // Concat BasicType, LMUL and Proto as key
+  StringMap LegalTypes;
+  StringSet<> IllegalTypes;
+
+  std::vector SemaRecords;
+  std::vector SemaSignatureTable;
 
 public:
   RVVEmitter(RecordKeeper &R) : Records(R) {}
@@ -45,22 +67,20 @@
   /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
   void createCodeGen(raw_ostream &o);
 
+  /// Emit all the information needed by SemaRVVLookup.cpp.
+  void createSema(raw_ostream &o);
+
 private:
   /// Create all intrinsics and add them to \p Out
   void createRVVIntrinsics(std::vector> &Out);
+  unsigned GetSemaSignatureIndex(const SmallVector &Signature);
   /// Print HeaderCode in RVVHeader Record to \p Out
   void printHeaderCode(raw_ostream &OS);
 
-  /// Emit Acrh predecessor definitions and body, assume the element of Defs are
-  /// sorted by extension.
-  void emitArchMacroAndBody(
-  std::vector> &Defs, raw_ostream &o,
-  std::function);
+  void ConstructSemaSignatureTable();
 
-  // Emit the architecture preprocessor definitions. Return true when emits
-  // non-empty string.
-  bool emitMacroRestrictionStr(RISCVPredefinedMacroT PredefinedMacros,
-   raw_ostream &o);
+  void EmitSemaRecords(raw_ostream &OS);
+  void EmitSemaSignatureTable(raw_ostream &OS);
 };
 
 } // namespace
@@ -174,7 +194,6 @@
 // RVVEmitter implementation
 //===--

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 426284.
kito-cheng marked 4 inline comments as done.
kito-cheng added a comment.

Changes:

- Add more comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111617/new/

https://reviews.llvm.org/D111617

Files:
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TokenKinds.def
  clang/include/clang/Parse/Parser.h
  clang/include/clang/Sema/Sema.h
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Parse/ParsePragma.cpp
  clang/lib/Sema/CMakeLists.txt
  clang/lib/Sema/SemaLookup.cpp
  clang/lib/Sema/SemaRVVLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -110,6 +110,7 @@
 void EmitRVVHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltins(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltinCG(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitRVVBuiltinSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 
 void EmitCdeHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitCdeBuiltinDef(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -88,6 +88,7 @@
   GenRISCVVectorHeader,
   GenRISCVVectorBuiltins,
   GenRISCVVectorBuiltinCG,
+  GenRISCVVectorBuiltinSema,
   GenAttrDocs,
   GenDiagDocs,
   GenOptDocs,
@@ -243,6 +244,8 @@
"Generate riscv_vector_builtins.inc for clang"),
 clEnumValN(GenRISCVVectorBuiltinCG, "gen-riscv-vector-builtin-codegen",
"Generate riscv_vector_builtin_cg.inc for clang"),
+clEnumValN(GenRISCVVectorBuiltinSema, "gen-riscv-vector-builtin-sema",
+   "Generate riscv_vector_builtin_sema.inc for clang"),
 clEnumValN(GenAttrDocs, "gen-attr-docs",
"Generate attribute documentation"),
 clEnumValN(GenDiagDocs, "gen-diag-docs",
@@ -458,6 +461,9 @@
   case GenRISCVVectorBuiltinCG:
 EmitRVVBuiltinCG(Records, OS);
 break;
+  case GenRISCVVectorBuiltinSema:
+EmitRVVBuiltinSema(Records, OS);
+break;
   case GenAttrDocs:
 EmitClangAttrDocs(Records, OS);
 break;
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -20,6 +20,7 @@
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/StringSet.h"
+#include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
@@ -29,9 +30,48 @@
 using namespace clang::RISCV;
 
 namespace {
+struct SemaRecord {
+  // Intrinsic name, e.g. vadd_vv
+  std::string Name;
+
+  // Overloaded intrinsic name, could be empty if can be computed from Name
+  // e.g. vadd
+  std::string OverloadedName;
+
+  // Supported type, mask of BasicType
+  unsigned TypeRangeMask;
+
+  // Supported LMUL.
+  unsigned Log2LMULMask;
+
+  // Required target features for this intrinsic.
+  std::vector RequiredFeatures;
+
+  // Prototype for this intrinsic.
+  SmallVector Prototype;
+
+  // Prototype for masked intrinsic.
+  SmallVector MaskedPrototype;
+
+  // Suffix of intrinsic name.
+  SmallVector Suffix;
+
+  // Suffix of overloaded intrinsic name.
+  SmallVector OverloadedSuffix;
+
+  // Number of field, large than 1 if it's segment load/store.
+  unsigned NF;
+};
+
 class RVVEmitter {
 private:
   RecordKeeper &Records;
+  // Concat BasicType, LMUL and Proto as key
+  StringMap LegalTypes;
+  StringSet<> IllegalTypes;
+
+  std::vector SemaRecords;
+  std::vector SemaSignatureTable;
 
 public:
   RVVEmitter(RecordKeeper &R) : Records(R) {}
@@ -45,22 +85,27 @@
   /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
   void createCodeGen(raw_ostream &o);
 
+  /// Emit all the information needed by SemaRVVLookup.cpp.
+  /// We've large number of intrinsic function for RVV, creating a customized
+  /// could speed up the compilation time.
+  void createSema(raw_ostream &o);
+
 private:
   /// Create all intrinsics and add them to \p Out
   void createRVVIntrinsics(std::vector> &Out);
   /// Print HeaderCode in RVVHeader Record to \p Out
   void printHeaderCode(raw_ostream &OS);
 
-  /// Emit Acrh predecessor definitions and body, assume the element of Defs are
-  /// sorted by extension.
-  void emitArchMacroAndBody(
-  std::vector> &Defs, raw_ostream &o,
-  std::function);
+  ///

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added inline comments.



Comment at: clang/lib/Sema/SemaRVVLookup.cpp:91
+struct RVVIntrinsicDef {
+  std::string Name;
+  std::string GenericName;

khchen wrote:
> why do we need to declare Name as std::string here but RVVIntrinsicRecord use 
> `const char*`?
`RVVIntrinsicRecord::Name` is raw name of a intrinsic, `RVVIntrinsicDef::Name` 
is expanded with type infos, e.g. `RVVIntrinsicRecord::Name` is `vadd` and  
`RVVIntrinsicDef::Name` is `vadd_vv_i32m1`.



Comment at: clang/lib/Sema/SemaRVVLookup.cpp:92
+  std::string Name;
+  std::string GenericName;
+  std::string BuiltinName;

khchen wrote:
> Nit: I think we use the `overload` terminology rather than `generic`.
Updated.



Comment at: clang/lib/Sema/SemaRVVLookup.cpp:359-371
+  if (!Record.MangledName)
+MangledName = StringRef(Record.Name).split("_").first.str();
+  else
+MangledName = Record.MangledName;
+  if (!SuffixStr.empty())
+Name += "_" + SuffixStr.str();
+  if (!MangledSuffixStr.empty())

khchen wrote:
> IIUC, above code initialize the BuiltinName, Name and MangledName same with 
> RVVIntrinsic::RVVIntrinsic did, right?
> If yes, I think we need to have some comment note that.
More comment added.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 426285.
kito-cheng marked 2 inline comments as done.
kito-cheng added a comment.

Changes:

- Minor tweak.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111617/new/

https://reviews.llvm.org/D111617

Files:
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TokenKinds.def
  clang/include/clang/Parse/Parser.h
  clang/include/clang/Sema/Sema.h
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Parse/ParsePragma.cpp
  clang/lib/Sema/CMakeLists.txt
  clang/lib/Sema/SemaLookup.cpp
  clang/lib/Sema/SemaRVVLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -110,6 +110,7 @@
 void EmitRVVHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltins(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltinCG(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitRVVBuiltinSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 
 void EmitCdeHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitCdeBuiltinDef(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -88,6 +88,7 @@
   GenRISCVVectorHeader,
   GenRISCVVectorBuiltins,
   GenRISCVVectorBuiltinCG,
+  GenRISCVVectorBuiltinSema,
   GenAttrDocs,
   GenDiagDocs,
   GenOptDocs,
@@ -243,6 +244,8 @@
"Generate riscv_vector_builtins.inc for clang"),
 clEnumValN(GenRISCVVectorBuiltinCG, "gen-riscv-vector-builtin-codegen",
"Generate riscv_vector_builtin_cg.inc for clang"),
+clEnumValN(GenRISCVVectorBuiltinSema, "gen-riscv-vector-builtin-sema",
+   "Generate riscv_vector_builtin_sema.inc for clang"),
 clEnumValN(GenAttrDocs, "gen-attr-docs",
"Generate attribute documentation"),
 clEnumValN(GenDiagDocs, "gen-diag-docs",
@@ -458,6 +461,9 @@
   case GenRISCVVectorBuiltinCG:
 EmitRVVBuiltinCG(Records, OS);
 break;
+  case GenRISCVVectorBuiltinSema:
+EmitRVVBuiltinSema(Records, OS);
+break;
   case GenAttrDocs:
 EmitClangAttrDocs(Records, OS);
 break;
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -20,6 +20,7 @@
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/StringSet.h"
+#include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
@@ -29,9 +30,48 @@
 using namespace clang::RISCV;
 
 namespace {
+struct SemaRecord {
+  // Intrinsic name, e.g. vadd_vv
+  std::string Name;
+
+  // Overloaded intrinsic name, could be empty if can be computed from Name
+  // e.g. vadd
+  std::string OverloadedName;
+
+  // Supported type, mask of BasicType
+  unsigned TypeRangeMask;
+
+  // Supported LMUL.
+  unsigned Log2LMULMask;
+
+  // Required target features for this intrinsic.
+  std::vector RequiredFeatures;
+
+  // Prototype for this intrinsic.
+  SmallVector Prototype;
+
+  // Prototype for masked intrinsic.
+  SmallVector MaskedPrototype;
+
+  // Suffix of intrinsic name.
+  SmallVector Suffix;
+
+  // Suffix of overloaded intrinsic name.
+  SmallVector OverloadedSuffix;
+
+  // Number of field, large than 1 if it's segment load/store.
+  unsigned NF;
+};
+
 class RVVEmitter {
 private:
   RecordKeeper &Records;
+  // Concat BasicType, LMUL and Proto as key
+  StringMap LegalTypes;
+  StringSet<> IllegalTypes;
+
+  std::vector SemaRecords;
+  std::vector SemaSignatureTable;
 
 public:
   RVVEmitter(RecordKeeper &R) : Records(R) {}
@@ -45,22 +85,27 @@
   /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
   void createCodeGen(raw_ostream &o);
 
+  /// Emit all the information needed by SemaRVVLookup.cpp.
+  /// We've large number of intrinsic function for RVV, creating a customized
+  /// could speed up the compilation time.
+  void createSema(raw_ostream &o);
+
 private:
   /// Create all intrinsics and add them to \p Out
   void createRVVIntrinsics(std::vector> &Out);
   /// Print HeaderCode in RVVHeader Record to \p Out
   void printHeaderCode(raw_ostream &OS);
 
-  /// Emit Acrh predecessor definitions and body, assume the element of Defs are
-  /// sorted by extension.
-  void emitArchMacroAndBody(
-  std::vector> &Defs, raw_ostream &o,
-  std::function);
+  /// Const

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 444188.
kito-cheng added a comment.

Changes:

- Correct filename for testcases.
- Use forward declaration for llvm::raw_ostream


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Files:
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TokenKinds.def
  clang/include/clang/Parse/Parser.h
  clang/include/clang/Sema/RISCVIntrinsicManager.h
  clang/include/clang/Sema/Sema.h
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Parse/ParsePragma.cpp
  clang/lib/Sema/CMakeLists.txt
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaLookup.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/test/Sema/riscv-bad-intrinsic-pragma.c
  clang/test/Sema/riscv-intrinsic-pragma.c
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -110,6 +110,7 @@
 void EmitRVVHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltins(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltinCG(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitRVVBuiltinSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 
 void EmitCdeHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitCdeBuiltinDef(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -88,6 +88,7 @@
   GenRISCVVectorHeader,
   GenRISCVVectorBuiltins,
   GenRISCVVectorBuiltinCG,
+  GenRISCVVectorBuiltinSema,
   GenAttrDocs,
   GenDiagDocs,
   GenOptDocs,
@@ -243,6 +244,8 @@
"Generate riscv_vector_builtins.inc for clang"),
 clEnumValN(GenRISCVVectorBuiltinCG, "gen-riscv-vector-builtin-codegen",
"Generate riscv_vector_builtin_cg.inc for clang"),
+clEnumValN(GenRISCVVectorBuiltinSema, "gen-riscv-vector-builtin-sema",
+   "Generate riscv_vector_builtin_sema.inc for clang"),
 clEnumValN(GenAttrDocs, "gen-attr-docs",
"Generate attribute documentation"),
 clEnumValN(GenDiagDocs, "gen-diag-docs",
@@ -458,6 +461,9 @@
   case GenRISCVVectorBuiltinCG:
 EmitRVVBuiltinCG(Records, OS);
 break;
+  case GenRISCVVectorBuiltinSema:
+EmitRVVBuiltinSema(Records, OS);
+break;
   case GenAttrDocs:
 EmitClangAttrDocs(Records, OS);
 break;
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -20,6 +20,7 @@
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/StringSet.h"
+#include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
@@ -29,6 +30,59 @@
 using namespace clang::RISCV;
 
 namespace {
+struct SemaRecord {
+  // Intrinsic name, e.g. vadd_vv
+  std::string Name;
+
+  // Overloaded intrinsic name, could be empty if can be computed from Name
+  // e.g. vadd
+  std::string OverloadedName;
+
+  // Supported type, mask of BasicType.
+  unsigned TypeRangeMask;
+
+  // Supported LMUL.
+  unsigned Log2LMULMask;
+
+  // Required extensions for this intrinsic.
+  unsigned RequiredExtensions;
+
+  // Prototype for this intrinsic.
+  SmallVector Prototype;
+
+  // Prototype for masked intrinsic.
+  SmallVector MaskedPrototype;
+
+  // Suffix of intrinsic name.
+  SmallVector Suffix;
+
+  // Suffix of overloaded intrinsic name.
+  SmallVector OverloadedSuffix;
+
+  // Number of field, large than 1 if it's segment load/store.
+  unsigned NF;
+};
+
+// Compressed function signature table.
+class SemaSignatureTable {
+private:
+  std::vector SignatureTable;
+
+  void insert(ArrayRef Signature);
+
+public:
+  static constexpr unsigned INVALID_INDEX = ~0U;
+
+  // Create compressed signature table from SemaRecords.
+  void init(ArrayRef SemaRecords);
+
+  // Query the Signature, return INVALID_INDEX if not found.
+  unsigned getIndex(ArrayRef Signature);
+
+  /// Print signature table in RVVHeader Record to \p OS
+  void print(raw_ostream &OS);
+};
+
 class RVVEmitter {
 private:
   RecordKeeper &Records;
@@ -45,22 +99,22 @@
   /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
   void createCodeGen(raw_ostream &o);
 
+  /// Emit all the information needed by SemaRISCVVectorLookup.cpp.
+  /// We've large number of intrinsic function for RVV, creating a customized
+  /// could speed up 

[PATCH] D130190: [Driver] Error for -gsplit-dwarf with RISC-V linker relaxation

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng accepted this revision.
kito-cheng added a comment.

LGTM


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[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

ping


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[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

@aaron.ballman do you mind give few more look on this patch, we would like 
gather LGTM from both RISC-V folks and clang folks, thanks :)


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[PATCH] D124730: [RISCV][NFC] Refactor RISC-V vector intrinsic utils.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 429184.
kito-cheng marked 3 inline comments as done.
kito-cheng added a comment.

Changes:

- Address @khchen's comment.
- Use new hash scheme for cache the result of computeType.


Repository:
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Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -32,9 +32,6 @@
 class RVVEmitter {
 private:
   RecordKeeper &Records;
-  // Concat BasicType, LMUL and Proto as key
-  StringMap LegalTypes;
-  StringSet<> IllegalTypes;
 
 public:
   RVVEmitter(RecordKeeper &R) : Records(R) {}
@@ -48,20 +45,11 @@
   /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
   void createCodeGen(raw_ostream &o);
 
-  std::string getSuffixStr(char Type, int Log2LMUL, StringRef Prototypes);
-
 private:
   /// Create all intrinsics and add them to \p Out
   void createRVVIntrinsics(std::vector> &Out);
   /// Print HeaderCode in RVVHeader Record to \p Out
   void printHeaderCode(raw_ostream &OS);
-  /// Compute output and input types by applying different config (basic type
-  /// and LMUL with type transformers). It also record result of type in legal
-  /// or illegal set to avoid compute the  same config again. The result maybe
-  /// have illegal RVVType.
-  Optional computeTypes(BasicType BT, int Log2LMUL, unsigned NF,
-  ArrayRef PrototypeSeq);
-  Optional computeType(BasicType BT, int Log2LMUL, StringRef Proto);
 
   /// Emit Acrh predecessor definitions and body, assume the element of Defs are
   /// sorted by extension.
@@ -73,14 +61,39 @@
   // non-empty string.
   bool emitMacroRestrictionStr(RISCVPredefinedMacroT PredefinedMacros,
raw_ostream &o);
-  // Slice Prototypes string into sub prototype string and process each sub
-  // prototype string individually in the Handler.
-  void parsePrototypes(StringRef Prototypes,
-   std::function Handler);
 };
 
 } // namespace
 
+static BasicType ParseBasicType(char c) {
+  switch (c) {
+  case 'c':
+return BasicType::Int8;
+break;
+  case 's':
+return BasicType::Int16;
+break;
+  case 'i':
+return BasicType::Int32;
+break;
+  case 'l':
+return BasicType::Int64;
+break;
+  case 'x':
+return BasicType::Float16;
+break;
+  case 'f':
+return BasicType::Float32;
+break;
+  case 'd':
+return BasicType::Float64;
+break;
+
+  default:
+return BasicType::Unknown;
+  }
+}
+
 void emitCodeGenSwitchBody(const RVVIntrinsic *RVVI, raw_ostream &OS) {
   if (!RVVI->getIRName().empty())
 OS << "  ID = Intrinsic::riscv_" + RVVI->getIRName() + ";\n";
@@ -202,24 +215,31 @@
   constexpr int Log2LMULs[] = {-3, -2, -1, 0, 1, 2, 3};
   // Print RVV boolean types.
   for (int Log2LMUL : Log2LMULs) {
-auto T = computeType('c', Log2LMUL, "m");
+auto T = RVVType::computeType(BasicType::Int8, Log2LMUL,
+  PrototypeDescriptor::Mask);
 if (T.hasValue())
   printType(T.getValue());
   }
   // Print RVV int/float types.
   for (char I : StringRef("csil")) {
+BasicType BT = ParseBasicType(I);
 for (int Log2LMUL : Log2LMULs) {
-  auto T = computeType(I, Log2LMUL, "v");
+  auto T = RVVType::computeType(BT, Log2LMUL, PrototypeDescriptor::Vector);
   if (T.hasValue()) {
 printType(T.getValue());
-auto UT = computeType(I, Log2LMUL, "Uv");
+auto UT = RVVType::computeType(
+BT, Log2LMUL,
+PrototypeDescriptor(BaseTypeModifier::Vector,
+VectorTypeModifier::NoModifier,
+TypeModifier::UnsignedInteger));
 printType(UT.getValue());
   }
 }
   }
   OS << "#if defined(__riscv_zvfh)\n";
   for (int Log2LMUL : Log2LMULs) {
-auto T = computeType('x', Log2LMUL, "v");
+auto T = RVVType::computeType(BasicType::Float16, Log2LMUL,
+  PrototypeDescriptor::Vector);
 if (T.hasValue())
   printType(T.getValue());
   }
@@ -227,7 +247,8 @@
 
   OS << "#if defined(__riscv_f)\n";
   for (int Log2LMUL : Log2LMULs) {
-auto T = computeType('f', Log2LMUL, "v");
+auto T = RVVType::computeType(BasicType::Float32, Log2LMUL,
+  PrototypeDescriptor::Vector);
 if (T.hasValue())
   printType(T.getValue());
   }
@@ -235,7 +256,8 @@
 
   OS << "#if defined(__riscv_d)\n";
   for (int Log2LMUL : Log2LMULs) {
-auto T = computeType('d', Log2LMUL, "v");
+auto T = RVVType::computeType(BasicType::Float64, Log2LMUL,
+  Pr

[PATCH] D124730: [RISCV][NFC] Refactor RISC-V vector intrinsic utils.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added inline comments.



Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:55
+// basic vector type, used to compute type info of arguments.
+enum class PrimitiveType : uint8_t {
+  Invalid,

khchen wrote:
> I think vector is not a primitive type in common sense, is it?
> why Widening2XVector, Widening4XVector, Widening8XVector and MaskVector is 
> not part of VectorTypeModifier?
> 
> Sorry, I'm confused and maybe forget something.
> I think vector is not a primitive type in common sense, is it?
It's called `primitive type transformer` on the comment[1], so that's why I use 
PrimitiveType here, but I admit that's kind of confusing, maybe 
BaseTypeModifier?

> Widening2XVector, Widening4XVector, Widening8XVector and MaskVector is not 
> part of VectorTypeModifier?

Good point, Moved to VectorTypeModifier!

[1] 
https://github.com/llvm/llvm-project/blob/main/clang/lib/Support/RISCVVIntrinsicUtils.cpp#L366



Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:85
+// TypeProfile is used to compute type info of arguments or return value.
+struct TypeProfile {
+  constexpr TypeProfile() = default;

khchen wrote:
> I think we need to update the comment in riscv_vector.td to sync the word 
> "TypeProfile", I feel the new word `TypeProfile` is similar to `modifier` or 
> `prototype`, is it?
> 
> ```
> The C/C++ prototype of the builtin is defined by the Prototype attribute.
> Prototype is a non-empty sequence of type transformers, the first of which
> is the return type of the builtin and the rest are the parameters of the
> builtin, in order. For instance if Prototype is "wvv" and TypeRange is "si"
> a first builtin will have type
> ```
> 
> we call it  `modifier` or `prototype` is because those words are coming from 
> clang intrinsic definition and other target.
> 
> https://github.com/llvm/llvm-project/blob/main/clang/include/clang/Basic/Builtins.def#L52
> https://github.com/llvm/llvm-project/blob/main/clang/include/clang/Basic/arm_sve.td#L58
> 
> personally I think consistent naming maybe better than creating a new word, 
> what do you think?
> 
> 
> BTW, I think having this new class is really good idea for refactoring!
Renamed to `PrototypeDescriptor`, that should be better I guess :)



Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:90
+  : PT(static_cast(PT)), TM(static_cast(TM)) {}
+  constexpr TypeProfile(uint8_t PT, uint8_t VTM, uint8_t TM)
+  : PT(PT), VTM(VTM), TM(TM) {}

khchen wrote:
> If we allow parameter could `uint8_t`, why other constructors not follow the 
> same rule?
Keep only two version of constructor, one for all uint8_t and one for all enum.

All enum one used for checking type safe as possilbe.
And uint8_t version used for low-level construct (used in 
https://reviews.llvm.org/D111617)



Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:97
+
+  std::string IndexStr() const {
+return std::to_string(PT) + "_" + std::to_string(VTM) + "_" +

khchen wrote:
> What's purpose of this function, translate TypeProfile to the Proto string?
Used for caching the `RVVType`, but I realized we could use integer(`uint64_t`) 
as hash value, use new hash scheme in new version.


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[PATCH] D124730: [RISCV][NFC] Refactor RISC-V vector intrinsic utils.

[Kito Cheng via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG7ff0bf576b84: [RISCV][NFC] Refactor RISC-V vector intrinsic 
utils. (authored by kito-cheng).

Changed prior to commit:
  https://reviews.llvm.org/D124730?vs=429184&id=429620#toc

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Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -32,9 +32,6 @@
 class RVVEmitter {
 private:
   RecordKeeper &Records;
-  // Concat BasicType, LMUL and Proto as key
-  StringMap LegalTypes;
-  StringSet<> IllegalTypes;
 
 public:
   RVVEmitter(RecordKeeper &R) : Records(R) {}
@@ -48,20 +45,11 @@
   /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
   void createCodeGen(raw_ostream &o);
 
-  std::string getSuffixStr(char Type, int Log2LMUL, StringRef Prototypes);
-
 private:
   /// Create all intrinsics and add them to \p Out
   void createRVVIntrinsics(std::vector> &Out);
   /// Print HeaderCode in RVVHeader Record to \p Out
   void printHeaderCode(raw_ostream &OS);
-  /// Compute output and input types by applying different config (basic type
-  /// and LMUL with type transformers). It also record result of type in legal
-  /// or illegal set to avoid compute the  same config again. The result maybe
-  /// have illegal RVVType.
-  Optional computeTypes(BasicType BT, int Log2LMUL, unsigned NF,
-  ArrayRef PrototypeSeq);
-  Optional computeType(BasicType BT, int Log2LMUL, StringRef Proto);
 
   /// Emit Acrh predecessor definitions and body, assume the element of Defs are
   /// sorted by extension.
@@ -73,14 +61,39 @@
   // non-empty string.
   bool emitMacroRestrictionStr(RISCVPredefinedMacroT PredefinedMacros,
raw_ostream &o);
-  // Slice Prototypes string into sub prototype string and process each sub
-  // prototype string individually in the Handler.
-  void parsePrototypes(StringRef Prototypes,
-   std::function Handler);
 };
 
 } // namespace
 
+static BasicType ParseBasicType(char c) {
+  switch (c) {
+  case 'c':
+return BasicType::Int8;
+break;
+  case 's':
+return BasicType::Int16;
+break;
+  case 'i':
+return BasicType::Int32;
+break;
+  case 'l':
+return BasicType::Int64;
+break;
+  case 'x':
+return BasicType::Float16;
+break;
+  case 'f':
+return BasicType::Float32;
+break;
+  case 'd':
+return BasicType::Float64;
+break;
+
+  default:
+return BasicType::Unknown;
+  }
+}
+
 void emitCodeGenSwitchBody(const RVVIntrinsic *RVVI, raw_ostream &OS) {
   if (!RVVI->getIRName().empty())
 OS << "  ID = Intrinsic::riscv_" + RVVI->getIRName() + ";\n";
@@ -202,24 +215,31 @@
   constexpr int Log2LMULs[] = {-3, -2, -1, 0, 1, 2, 3};
   // Print RVV boolean types.
   for (int Log2LMUL : Log2LMULs) {
-auto T = computeType('c', Log2LMUL, "m");
+auto T = RVVType::computeType(BasicType::Int8, Log2LMUL,
+  PrototypeDescriptor::Mask);
 if (T.hasValue())
   printType(T.getValue());
   }
   // Print RVV int/float types.
   for (char I : StringRef("csil")) {
+BasicType BT = ParseBasicType(I);
 for (int Log2LMUL : Log2LMULs) {
-  auto T = computeType(I, Log2LMUL, "v");
+  auto T = RVVType::computeType(BT, Log2LMUL, PrototypeDescriptor::Vector);
   if (T.hasValue()) {
 printType(T.getValue());
-auto UT = computeType(I, Log2LMUL, "Uv");
+auto UT = RVVType::computeType(
+BT, Log2LMUL,
+PrototypeDescriptor(BaseTypeModifier::Vector,
+VectorTypeModifier::NoModifier,
+TypeModifier::UnsignedInteger));
 printType(UT.getValue());
   }
 }
   }
   OS << "#if defined(__riscv_zvfh)\n";
   for (int Log2LMUL : Log2LMULs) {
-auto T = computeType('x', Log2LMUL, "v");
+auto T = RVVType::computeType(BasicType::Float16, Log2LMUL,
+  PrototypeDescriptor::Vector);
 if (T.hasValue())
   printType(T.getValue());
   }
@@ -227,7 +247,8 @@
 
   OS << "#if defined(__riscv_f)\n";
   for (int Log2LMUL : Log2LMULs) {
-auto T = computeType('f', Log2LMUL, "v");
+auto T = RVVType::computeType(BasicType::Float32, Log2LMUL,
+  PrototypeDescriptor::Vector);
 if (T.hasValue())
   printType(T.getValue());
   }
@@ -235,7 +256,8 @@
 
   OS << "#if defined(__riscv_d)\n";
   for (int Log2LMUL : Log2LMULs) {
-auto T = computeType('d', Log2LMUL, "v");
+auto T = RVVType::computeType(BasicType::Float6

[PATCH] D125886: [RISCV][NFC] Rename variable in RISCVVEmitter.cpp

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng created this revision.
Herald added subscribers: sunshaoce, VincentWu, luke957, vkmr, frasercrmck, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
kito-cheng requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: clang.

- Use `Overloaded` rather than `Mangled`.
- Use `Prototype` or `Desc` rather than `Seq`, it's not just a string sequence.
  - `Prototype` for those PrototypeDescriptor will used to evaluate as argument 
type.
  - `Desc` for those PrototypeDescriptor will


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D125886

Files:
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -387,8 +387,8 @@
   for (auto *R : RV) {
 StringRef Name = R->getValueAsString("Name");
 StringRef SuffixProto = R->getValueAsString("Suffix");
-StringRef MangledName = R->getValueAsString("MangledName");
-StringRef MangledSuffixProto = R->getValueAsString("MangledSuffix");
+StringRef OverloadedName = R->getValueAsString("MangledName");
+StringRef OverloadedSuffixProto = R->getValueAsString("MangledSuffix");
 StringRef Prototypes = R->getValueAsString("Prototype");
 StringRef TypeRange = R->getValueAsString("TypeRange");
 bool HasMasked = R->getValueAsBit("HasMasked");
@@ -414,30 +414,30 @@
 unsigned NF = R->getValueAsInt("NF");
 
 // Parse prototype and create a list of primitive type with transformers
-// (operand) in ProtoSeq. ProtoSeq[0] is output operand.
-SmallVector ProtoSeq = parsePrototypes(Prototypes);
+// (operand) in Prototype. Prototype[0] is output operand.
+SmallVector Prototype = parsePrototypes(Prototypes);
 
-SmallVector SuffixProtoSeq =
-parsePrototypes(SuffixProto);
-SmallVector MangledSuffixProtoSeq =
-parsePrototypes(MangledSuffixProto);
+SmallVector SuffixDesc = parsePrototypes(SuffixProto);
+SmallVector OverloadedSuffixDesc =
+parsePrototypes(OverloadedSuffixProto);
 
 // Compute Builtin types
-SmallVector ProtoMaskSeq = ProtoSeq;
+SmallVector MaskedPrototype = Prototype;
 if (HasMasked) {
   // If HasMaskedOffOperand, insert result type as first input operand.
   if (HasMaskedOffOperand) {
 if (NF == 1) {
-  ProtoMaskSeq.insert(ProtoMaskSeq.begin() + 1, ProtoSeq[0]);
+  MaskedPrototype.insert(MaskedPrototype.begin() + 1, Prototype[0]);
 } else {
   // Convert
   // (void, op0 address, op1 address, ...)
   // to
   // (void, op0 address, op1 address, ..., maskedoff0, maskedoff1, ...)
-  PrototypeDescriptor MaskoffType = ProtoSeq[1];
+  PrototypeDescriptor MaskoffType = Prototype[1];
   MaskoffType.TM &= ~static_cast(TypeModifier::Pointer);
   for (unsigned I = 0; I < NF; ++I)
-ProtoMaskSeq.insert(ProtoMaskSeq.begin() + NF + 1, MaskoffType);
+MaskedPrototype.insert(MaskedPrototype.begin() + NF + 1,
+   MaskoffType);
 }
   }
   if (HasMaskedOffOperand && NF > 1) {
@@ -446,18 +446,18 @@
 // to
 // (void, op0 address, op1 address, ..., mask, maskedoff0, maskedoff1,
 // ...)
-ProtoMaskSeq.insert(ProtoMaskSeq.begin() + NF + 1,
-PrototypeDescriptor::Mask);
+MaskedPrototype.insert(MaskedPrototype.begin() + NF + 1,
+   PrototypeDescriptor::Mask);
   } else {
 // If HasMasked, insert PrototypeDescriptor:Mask as first input operand.
-ProtoMaskSeq.insert(ProtoMaskSeq.begin() + 1,
-PrototypeDescriptor::Mask);
+MaskedPrototype.insert(MaskedPrototype.begin() + 1,
+   PrototypeDescriptor::Mask);
   }
 }
 // If HasVL, append PrototypeDescriptor:VL to last operand
 if (HasVL) {
-  ProtoSeq.push_back(PrototypeDescriptor::VL);
-  ProtoMaskSeq.push_back(PrototypeDescriptor::VL);
+  Prototype.push_back(PrototypeDescriptor::VL);
+  MaskedPrototype.push_back(PrototypeDescriptor::VL);
 }
 
 // Create Intrinsics for each type and LMUL.
@@ -465,18 +465,17 @@
   for (int Log2LMUL : Log2LMULList) {
 BasicType BT = ParseBasicType(I);
 Optional Types =
-RVVType::computeTypes(BT, Log2LMUL, NF, ProtoSeq);
+RVVType::computeTypes(BT, Log2LMUL, NF, Prototype);
 // Ignored to create new intrinsic if there are any illegal types.
 if (!Types.hasValue())
   cont

[PATCH] D125886: [RISCV][NFC] Rename variable in RISCVVEmitter.cpp

[Kito Cheng via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG1467e01f8f69: [RISCV][NFC] Rename variable in 
RISCVVEmitter.cpp (authored by kito-cheng).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125886/new/

https://reviews.llvm.org/D125886

Files:
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -387,8 +387,8 @@
   for (auto *R : RV) {
 StringRef Name = R->getValueAsString("Name");
 StringRef SuffixProto = R->getValueAsString("Suffix");
-StringRef MangledName = R->getValueAsString("MangledName");
-StringRef MangledSuffixProto = R->getValueAsString("MangledSuffix");
+StringRef OverloadedName = R->getValueAsString("MangledName");
+StringRef OverloadedSuffixProto = R->getValueAsString("MangledSuffix");
 StringRef Prototypes = R->getValueAsString("Prototype");
 StringRef TypeRange = R->getValueAsString("TypeRange");
 bool HasMasked = R->getValueAsBit("HasMasked");
@@ -414,30 +414,30 @@
 unsigned NF = R->getValueAsInt("NF");
 
 // Parse prototype and create a list of primitive type with transformers
-// (operand) in ProtoSeq. ProtoSeq[0] is output operand.
-SmallVector ProtoSeq = parsePrototypes(Prototypes);
+// (operand) in Prototype. Prototype[0] is output operand.
+SmallVector Prototype = parsePrototypes(Prototypes);
 
-SmallVector SuffixProtoSeq =
-parsePrototypes(SuffixProto);
-SmallVector MangledSuffixProtoSeq =
-parsePrototypes(MangledSuffixProto);
+SmallVector SuffixDesc = parsePrototypes(SuffixProto);
+SmallVector OverloadedSuffixDesc =
+parsePrototypes(OverloadedSuffixProto);
 
 // Compute Builtin types
-SmallVector ProtoMaskSeq = ProtoSeq;
+SmallVector MaskedPrototype = Prototype;
 if (HasMasked) {
   // If HasMaskedOffOperand, insert result type as first input operand.
   if (HasMaskedOffOperand) {
 if (NF == 1) {
-  ProtoMaskSeq.insert(ProtoMaskSeq.begin() + 1, ProtoSeq[0]);
+  MaskedPrototype.insert(MaskedPrototype.begin() + 1, Prototype[0]);
 } else {
   // Convert
   // (void, op0 address, op1 address, ...)
   // to
   // (void, op0 address, op1 address, ..., maskedoff0, maskedoff1, ...)
-  PrototypeDescriptor MaskoffType = ProtoSeq[1];
+  PrototypeDescriptor MaskoffType = Prototype[1];
   MaskoffType.TM &= ~static_cast(TypeModifier::Pointer);
   for (unsigned I = 0; I < NF; ++I)
-ProtoMaskSeq.insert(ProtoMaskSeq.begin() + NF + 1, MaskoffType);
+MaskedPrototype.insert(MaskedPrototype.begin() + NF + 1,
+   MaskoffType);
 }
   }
   if (HasMaskedOffOperand && NF > 1) {
@@ -446,18 +446,18 @@
 // to
 // (void, op0 address, op1 address, ..., mask, maskedoff0, maskedoff1,
 // ...)
-ProtoMaskSeq.insert(ProtoMaskSeq.begin() + NF + 1,
-PrototypeDescriptor::Mask);
+MaskedPrototype.insert(MaskedPrototype.begin() + NF + 1,
+   PrototypeDescriptor::Mask);
   } else {
 // If HasMasked, insert PrototypeDescriptor:Mask as first input operand.
-ProtoMaskSeq.insert(ProtoMaskSeq.begin() + 1,
-PrototypeDescriptor::Mask);
+MaskedPrototype.insert(MaskedPrototype.begin() + 1,
+   PrototypeDescriptor::Mask);
   }
 }
 // If HasVL, append PrototypeDescriptor:VL to last operand
 if (HasVL) {
-  ProtoSeq.push_back(PrototypeDescriptor::VL);
-  ProtoMaskSeq.push_back(PrototypeDescriptor::VL);
+  Prototype.push_back(PrototypeDescriptor::VL);
+  MaskedPrototype.push_back(PrototypeDescriptor::VL);
 }
 
 // Create Intrinsics for each type and LMUL.
@@ -465,18 +465,17 @@
   for (int Log2LMUL : Log2LMULList) {
 BasicType BT = ParseBasicType(I);
 Optional Types =
-RVVType::computeTypes(BT, Log2LMUL, NF, ProtoSeq);
+RVVType::computeTypes(BT, Log2LMUL, NF, Prototype);
 // Ignored to create new intrinsic if there are any illegal types.
 if (!Types.hasValue())
   continue;
 
-auto SuffixStr =
-RVVIntrinsic::getSuffixStr(BT, Log2LMUL, SuffixProtoSeq);
-auto MangledSuffixStr =
-RVVIntrinsic::getSuffixStr(BT, Log2LMUL, MangledSuffixProtoSeq);
+auto SuffixStr = RVVIntrinsic::getSuffixStr(BT, Log2LMUL, SuffixDesc);
+auto OverloadedSuffixStr =
+RVVIntrinsic::getSuffixStr(BT, Log2LMUL, OverloadedSuffixDesc);
 // Create a unmasked intrinsic
 Out.push_back(std::make_unique(
-Name, SuffixStr, MangledName, Man

[PATCH] D125893: [RISCV][NFC] Change interface of RVVIntrinsic::getSuffixStr

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng created this revision.
kito-cheng added a reviewer: khchen.
Herald added subscribers: sunshaoce, VincentWu, luke957, vkmr, frasercrmck, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
kito-cheng requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: clang.

This NFC patch is splited from D111617 .

Using llvm::ArrayRef rather than llvm::SmallVector, ArrayRef is more generic
interface that could accept both llvm::ArrayRef and llvm::SmallVector.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D125893

Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Support/RISCVVIntrinsicUtils.cpp


Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -928,7 +928,7 @@
 
 std::string RVVIntrinsic::getSuffixStr(
 BasicType Type, int Log2LMUL,
-const llvm::SmallVector &PrototypeDescriptors) {
+const llvm::ArrayRef &PrototypeDescriptors) {
   SmallVector SuffixStrs;
   for (auto PD : PrototypeDescriptors) {
 auto T = RVVType::computeType(Type, Log2LMUL, PD);
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -341,9 +341,10 @@
   // Return the type string for a BUILTIN() macro in Builtins.def.
   std::string getBuiltinTypeStr() const;
 
-  static std::string getSuffixStr(
-  BasicType Type, int Log2LMUL,
-  const llvm::SmallVector &PrototypeDescriptors);
+  static std::string
+  getSuffixStr(BasicType Type, int Log2LMUL,
+   const llvm::ArrayRefSmallVector
+   &PrototypeDescriptors);
 };
 
 } // end namespace RISCV


Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -928,7 +928,7 @@
 
 std::string RVVIntrinsic::getSuffixStr(
 BasicType Type, int Log2LMUL,
-const llvm::SmallVector &PrototypeDescriptors) {
+const llvm::ArrayRef &PrototypeDescriptors) {
   SmallVector SuffixStrs;
   for (auto PD : PrototypeDescriptors) {
 auto T = RVVType::computeType(Type, Log2LMUL, PD);
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -341,9 +341,10 @@
   // Return the type string for a BUILTIN() macro in Builtins.def.
   std::string getBuiltinTypeStr() const;
 
-  static std::string getSuffixStr(
-  BasicType Type, int Log2LMUL,
-  const llvm::SmallVector &PrototypeDescriptors);
+  static std::string
+  getSuffixStr(BasicType Type, int Log2LMUL,
+   const llvm::ArrayRefSmallVector
+   &PrototypeDescriptors);
 };
 
 } // end namespace RISCV
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[PATCH] D125893: [RISCV][NFC] Change interface of RVVIntrinsic::getSuffixStr

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 430390.
kito-cheng added a comment.

Changes:

- Fix dumb typo...


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125893/new/

https://reviews.llvm.org/D125893

Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Support/RISCVVIntrinsicUtils.cpp


Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -928,7 +928,7 @@
 
 std::string RVVIntrinsic::getSuffixStr(
 BasicType Type, int Log2LMUL,
-const llvm::SmallVector &PrototypeDescriptors) {
+const llvm::ArrayRef &PrototypeDescriptors) {
   SmallVector SuffixStrs;
   for (auto PD : PrototypeDescriptors) {
 auto T = RVVType::computeType(Type, Log2LMUL, PD);
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -305,13 +305,15 @@
   unsigned NF = 1;
 
 public:
-  RVVIntrinsic(llvm::StringRef Name, llvm::StringRef Suffix, llvm::StringRef 
MangledName,
-   llvm::StringRef MangledSuffix, llvm::StringRef IRName, bool 
IsMasked,
-   bool HasMaskedOffOperand, bool HasVL, PolicyScheme Scheme,
-   bool HasUnMaskedOverloaded, bool HasBuiltinAlias,
-   llvm::StringRef ManualCodegen, const RVVTypes &Types,
+  RVVIntrinsic(llvm::StringRef Name, llvm::StringRef Suffix,
+   llvm::StringRef MangledName, llvm::StringRef MangledSuffix,
+   llvm::StringRef IRName, bool IsMasked, bool HasMaskedOffOperand,
+   bool HasVL, PolicyScheme Scheme, bool HasUnMaskedOverloaded,
+   bool HasBuiltinAlias, llvm::StringRef ManualCodegen,
+   const RVVTypes &Types,
const std::vector &IntrinsicTypes,
-   const std::vector &RequiredFeatures, unsigned 
NF);
+   const std::vector &RequiredFeatures,
+   unsigned NF);
   ~RVVIntrinsic() = default;
 
   RVVTypePtr getOutputType() const { return OutputType; }
@@ -341,9 +343,9 @@
   // Return the type string for a BUILTIN() macro in Builtins.def.
   std::string getBuiltinTypeStr() const;
 
-  static std::string getSuffixStr(
-  BasicType Type, int Log2LMUL,
-  const llvm::SmallVector &PrototypeDescriptors);
+  static std::string
+  getSuffixStr(BasicType Type, int Log2LMUL,
+   const llvm::ArrayRef 
&PrototypeDescriptors);
 };
 
 } // end namespace RISCV


Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -928,7 +928,7 @@
 
 std::string RVVIntrinsic::getSuffixStr(
 BasicType Type, int Log2LMUL,
-const llvm::SmallVector &PrototypeDescriptors) {
+const llvm::ArrayRef &PrototypeDescriptors) {
   SmallVector SuffixStrs;
   for (auto PD : PrototypeDescriptors) {
 auto T = RVVType::computeType(Type, Log2LMUL, PD);
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -305,13 +305,15 @@
   unsigned NF = 1;
 
 public:
-  RVVIntrinsic(llvm::StringRef Name, llvm::StringRef Suffix, llvm::StringRef MangledName,
-   llvm::StringRef MangledSuffix, llvm::StringRef IRName, bool IsMasked,
-   bool HasMaskedOffOperand, bool HasVL, PolicyScheme Scheme,
-   bool HasUnMaskedOverloaded, bool HasBuiltinAlias,
-   llvm::StringRef ManualCodegen, const RVVTypes &Types,
+  RVVIntrinsic(llvm::StringRef Name, llvm::StringRef Suffix,
+   llvm::StringRef MangledName, llvm::StringRef MangledSuffix,
+   llvm::StringRef IRName, bool IsMasked, bool HasMaskedOffOperand,
+   bool HasVL, PolicyScheme Scheme, bool HasUnMaskedOverloaded,
+   bool HasBuiltinAlias, llvm::StringRef ManualCodegen,
+   const RVVTypes &Types,
const std::vector &IntrinsicTypes,
-   const std::vector &RequiredFeatures, unsigned NF);
+   const std::vector &RequiredFeatures,
+   unsigned NF);
   ~RVVIntrinsic() = default;
 
   RVVTypePtr getOutputType() const { return OutputType; }
@@ -341,9 +343,9 @@
   // Return the type string for a BUILTIN() macro in Builtins.def.
   std::string getBuiltinTypeStr() const;
 
-  static std::string getSuffixStr(
-  BasicType Type, int Log2LMUL,
-  const llvm::SmallVector &PrototypeDescriptors);
+  static std::string
+  getSuffixStr(BasicType Type, int Log2LMUL,
+   const llvm::ArrayRef &PrototypeDescriptors);
 

[PATCH] D125893: [RISCV][NFC] Change interface of RVVIntrinsic::getSuffixStr

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 430391.
kito-cheng added a comment.

Changes:

- clang-format has applied on unexpected part, remove that.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125893/new/

https://reviews.llvm.org/D125893

Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Support/RISCVVIntrinsicUtils.cpp


Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -928,7 +928,7 @@
 
 std::string RVVIntrinsic::getSuffixStr(
 BasicType Type, int Log2LMUL,
-const llvm::SmallVector &PrototypeDescriptors) {
+const llvm::ArrayRef &PrototypeDescriptors) {
   SmallVector SuffixStrs;
   for (auto PD : PrototypeDescriptors) {
 auto T = RVVType::computeType(Type, Log2LMUL, PD);
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -341,9 +341,9 @@
   // Return the type string for a BUILTIN() macro in Builtins.def.
   std::string getBuiltinTypeStr() const;
 
-  static std::string getSuffixStr(
-  BasicType Type, int Log2LMUL,
-  const llvm::SmallVector &PrototypeDescriptors);
+  static std::string
+  getSuffixStr(BasicType Type, int Log2LMUL,
+   const llvm::ArrayRef 
&PrototypeDescriptors);
 };
 
 } // end namespace RISCV


Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -928,7 +928,7 @@
 
 std::string RVVIntrinsic::getSuffixStr(
 BasicType Type, int Log2LMUL,
-const llvm::SmallVector &PrototypeDescriptors) {
+const llvm::ArrayRef &PrototypeDescriptors) {
   SmallVector SuffixStrs;
   for (auto PD : PrototypeDescriptors) {
 auto T = RVVType::computeType(Type, Log2LMUL, PD);
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -341,9 +341,9 @@
   // Return the type string for a BUILTIN() macro in Builtins.def.
   std::string getBuiltinTypeStr() const;
 
-  static std::string getSuffixStr(
-  BasicType Type, int Log2LMUL,
-  const llvm::SmallVector &PrototypeDescriptors);
+  static std::string
+  getSuffixStr(BasicType Type, int Log2LMUL,
+   const llvm::ArrayRef &PrototypeDescriptors);
 };
 
 } // end namespace RISCV
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[PATCH] D125893: [RISCV][NFC] Change interface of RVVIntrinsic::getSuffixStr

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 430911.
kito-cheng added a comment.

Changes:

- Apply @craig.topper's suggestion.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125893/new/

https://reviews.llvm.org/D125893

Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Support/RISCVVIntrinsicUtils.cpp


Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -922,7 +922,7 @@
 
 std::string RVVIntrinsic::getSuffixStr(
 BasicType Type, int Log2LMUL,
-const llvm::SmallVector &PrototypeDescriptors) {
+llvm::ArrayRef PrototypeDescriptors) {
   SmallVector SuffixStrs;
   for (auto PD : PrototypeDescriptors) {
 auto T = RVVType::computeType(Type, Log2LMUL, PD);
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -340,9 +340,9 @@
   // Return the type string for a BUILTIN() macro in Builtins.def.
   std::string getBuiltinTypeStr() const;
 
-  static std::string getSuffixStr(
-  BasicType Type, int Log2LMUL,
-  const llvm::SmallVector &PrototypeDescriptors);
+  static std::string
+  getSuffixStr(BasicType Type, int Log2LMUL,
+   llvm::ArrayRef PrototypeDescriptors);
 };
 
 } // end namespace RISCV


Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -922,7 +922,7 @@
 
 std::string RVVIntrinsic::getSuffixStr(
 BasicType Type, int Log2LMUL,
-const llvm::SmallVector &PrototypeDescriptors) {
+llvm::ArrayRef PrototypeDescriptors) {
   SmallVector SuffixStrs;
   for (auto PD : PrototypeDescriptors) {
 auto T = RVVType::computeType(Type, Log2LMUL, PD);
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -340,9 +340,9 @@
   // Return the type string for a BUILTIN() macro in Builtins.def.
   std::string getBuiltinTypeStr() const;
 
-  static std::string getSuffixStr(
-  BasicType Type, int Log2LMUL,
-  const llvm::SmallVector &PrototypeDescriptors);
+  static std::string
+  getSuffixStr(BasicType Type, int Log2LMUL,
+   llvm::ArrayRef PrototypeDescriptors);
 };
 
 } // end namespace RISCV
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[PATCH] D125893: [RISCV][NFC] Change interface of RVVIntrinsic::getSuffixStr

[Kito Cheng via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGb166aa833e44: [RISCV][NFC] Change interface of 
RVVIntrinsic::getSuffixStr (authored by kito-cheng).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125893/new/

https://reviews.llvm.org/D125893

Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Support/RISCVVIntrinsicUtils.cpp


Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -922,7 +922,7 @@
 
 std::string RVVIntrinsic::getSuffixStr(
 BasicType Type, int Log2LMUL,
-const llvm::SmallVector &PrototypeDescriptors) {
+llvm::ArrayRef PrototypeDescriptors) {
   SmallVector SuffixStrs;
   for (auto PD : PrototypeDescriptors) {
 auto T = RVVType::computeType(Type, Log2LMUL, PD);
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -340,9 +340,9 @@
   // Return the type string for a BUILTIN() macro in Builtins.def.
   std::string getBuiltinTypeStr() const;
 
-  static std::string getSuffixStr(
-  BasicType Type, int Log2LMUL,
-  const llvm::SmallVector &PrototypeDescriptors);
+  static std::string
+  getSuffixStr(BasicType Type, int Log2LMUL,
+   llvm::ArrayRef PrototypeDescriptors);
 };
 
 } // end namespace RISCV


Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -922,7 +922,7 @@
 
 std::string RVVIntrinsic::getSuffixStr(
 BasicType Type, int Log2LMUL,
-const llvm::SmallVector &PrototypeDescriptors) {
+llvm::ArrayRef PrototypeDescriptors) {
   SmallVector SuffixStrs;
   for (auto PD : PrototypeDescriptors) {
 auto T = RVVType::computeType(Type, Log2LMUL, PD);
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -340,9 +340,9 @@
   // Return the type string for a BUILTIN() macro in Builtins.def.
   std::string getBuiltinTypeStr() const;
 
-  static std::string getSuffixStr(
-  BasicType Type, int Log2LMUL,
-  const llvm::SmallVector &PrototypeDescriptors);
+  static std::string
+  getSuffixStr(BasicType Type, int Log2LMUL,
+   llvm::ArrayRef PrototypeDescriptors);
 };
 
 } // end namespace RISCV
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[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 431646.
kito-cheng marked 5 inline comments as done.
kito-cheng added a comment.

Changes:

- Split out several NFC changes to individual NFC patchs.
- Moving most code emission logic into RISCVVIntrinsicUtils to prevent require 
sync manually.
- PCH support is WIP, will update soon.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111617/new/

https://reviews.llvm.org/D111617

Files:
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TokenKinds.def
  clang/include/clang/Parse/Parser.h
  clang/include/clang/Sema/Sema.h
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Parse/ParsePragma.cpp
  clang/lib/Sema/CMakeLists.txt
  clang/lib/Sema/SemaLookup.cpp
  clang/lib/Sema/SemaRVVLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -110,6 +110,7 @@
 void EmitRVVHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltins(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltinCG(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitRVVBuiltinSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 
 void EmitCdeHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitCdeBuiltinDef(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -88,6 +88,7 @@
   GenRISCVVectorHeader,
   GenRISCVVectorBuiltins,
   GenRISCVVectorBuiltinCG,
+  GenRISCVVectorBuiltinSema,
   GenAttrDocs,
   GenDiagDocs,
   GenOptDocs,
@@ -243,6 +244,8 @@
"Generate riscv_vector_builtins.inc for clang"),
 clEnumValN(GenRISCVVectorBuiltinCG, "gen-riscv-vector-builtin-codegen",
"Generate riscv_vector_builtin_cg.inc for clang"),
+clEnumValN(GenRISCVVectorBuiltinSema, "gen-riscv-vector-builtin-sema",
+   "Generate riscv_vector_builtin_sema.inc for clang"),
 clEnumValN(GenAttrDocs, "gen-attr-docs",
"Generate attribute documentation"),
 clEnumValN(GenDiagDocs, "gen-diag-docs",
@@ -458,6 +461,9 @@
   case GenRISCVVectorBuiltinCG:
 EmitRVVBuiltinCG(Records, OS);
 break;
+  case GenRISCVVectorBuiltinSema:
+EmitRVVBuiltinSema(Records, OS);
+break;
   case GenAttrDocs:
 EmitClangAttrDocs(Records, OS);
 break;
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -20,6 +20,7 @@
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/StringSet.h"
+#include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
@@ -29,10 +30,46 @@
 using namespace clang::RISCV;
 
 namespace {
+struct SemaRecord {
+  // Intrinsic name, e.g. vadd_vv
+  std::string Name;
+
+  // Overloaded intrinsic name, could be empty if can be computed from Name
+  // e.g. vadd
+  std::string OverloadedName;
+
+  // Supported type, mask of BasicType
+  unsigned TypeRangeMask;
+
+  // Supported LMUL.
+  unsigned Log2LMULMask;
+
+  // Required extensions for this intrinsic.
+  unsigned RequiredExtension;
+
+  // Prototype for this intrinsic.
+  SmallVector Prototype;
+
+  // Prototype for masked intrinsic.
+  SmallVector MaskedPrototype;
+
+  // Suffix of intrinsic name.
+  SmallVector Suffix;
+
+  // Suffix of overloaded intrinsic name.
+  SmallVector OverloadedSuffix;
+
+  // Number of field, large than 1 if it's segment load/store.
+  unsigned NF;
+};
+
 class RVVEmitter {
 private:
   RecordKeeper &Records;
 
+  std::vector SemaRecords;
+  std::vector SemaSignatureTable;
+
 public:
   RVVEmitter(RecordKeeper &R) : Records(R) {}
 
@@ -45,22 +82,25 @@
   /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
   void createCodeGen(raw_ostream &o);
 
+  /// Emit all the information needed by SemaRVVLookup.cpp.
+  /// We've large number of intrinsic function for RVV, creating a customized
+  /// could speed up the compilation time.
+  void createSema(raw_ostream &o);
+
 private:
   /// Create all intrinsics and add them to \p Out
   void createRVVIntrinsics(std::vector> &Out);
+  /// Create all intrinsics record from RVVIntrinsics.
+  void createRVVIntrinsicRecord(std::vector &Out);
+
   /// Print HeaderCode in RVVHeader Record to \p Out
   void printHeaderCode(raw_ostream &OS);
 
-  /// Emit Acrh predecessor defin

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added inline comments.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:480
+// They are handled by riscv_vector.h
+if (Name == "vsetvli" || Name == "vsetvlimax")
+  continue;

khchen wrote:
> I feel little tricky to checking the name here. what do you mean they are 
> handled by riscv_vector.h?
> do you mean they have `vsetvl_macro:RVVHeader`?
Yeah, they are defined in riscv_vector.h like this:
```
#define vsetvl_e8mf8(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 5)
#define vsetvl_e8mf4(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 6)
#define vsetvl_e8mf2(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 7)
#define vsetvl_e8m1(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 0)
#define vsetvl_e8m2(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 1)
...
```



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:611
+  for (const auto &SR : SemaRecords) {
+// Output *MUST* sync with RVVIntrinsicRecord in SemaRVVLookup.cpp.
+OS << "{"

khchen wrote:
> I'm thinking is it possible to have an unittest or test to make sure we won't 
> screw up in the future implementation?
> Is it possible to have unittest to test implement really have `sync` 
> correctly?
> Is it easy to debug the mismatch problem during implementation without any 
> new test added?
> We will add a new implementation (really cool speed up and meaningful 
> improvement), but unfortunately we don't have any tests, that make me a 
> little hesitating...
> 
> What do you think?
Change to another way to preventing sync those file manually, thanks for point 
out that!


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