On 2/2/26 23:33, Peter Maydell wrote:
The ID register ID_AA64ZFR0_EL1's fields are not all for SVE
exclusive features; some are also used to describe SME on an
SME-only CPU:
SVE-only fields:
* F64MM, F32MM, F16MM, SM4, B16B16, SVEVer
Fields used for SVE and SME (in some cases there is also a
field for SME in ID_AA64SMFR0_EL1, but it is just a "present
or absent" single bit flag and the ZFR0 field then tells you
what level of support is present):
* I8MM, SHA3, BF16, BitPerm, EltPerm, AES
Currently we zero the whole ID_AA64ZFR0_EL1 register in
arm_cpu_sve_finalize() if SVE is not present, which wipes also the
fields we need for SME. Only clear the fields which are SVE-specific
here, and clear the rest in arm_cpu_sme_finalize() if we
have neither SME nor SVE.
This requires us to update our ID_AA64ZFR0 field definitions
to match the rev M.a.a Arm ARM, as the F16MM SVE-only field
is not one we had a definition for previously.
Signed-off-by: Peter Maydell<[email protected]>
---
target/arm/cpu-features.h | 2 ++
target/arm/cpu64.c | 16 ++++++++++++++--
2 files changed, 16 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <[email protected]>
r~
