On 2/2/26 23:33, Peter Maydell wrote:
With FEAT_SME, even a CPU which does not implement FEAT_SVE is
allowed to execute the subset of SVE instructions which are permitted
in streaming SVE mode. We correctly handle this when the emulated
CPU has both FEAT_SVE and FEAT_SME, because sve_access_check()
includes the logic for this, matching the pseudocode
CheckSVEEnabled(). However if the emulated CPU only implement
FEAT_SME, it will fail the initial dc_isar_feature(aa64_sve, s)
feature check, because this doesn't match the check in the
per-instruction decode pseudocode, which is typically:
!IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME)
Add a new aa64_sme_or_sve feature function that we can use
to update the relevant uses of aa64_sve, and similarly
aa64_sme_or_sve2 for where we need to check FEAT_SVE2 || FEAT_SME.
Signed-off-by: Peter Maydell <[email protected]>
---
target/arm/cpu-features.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index a7ca410dcb..40393d88f0 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -1507,6 +1507,16 @@ static inline bool isar_feature_aa64_sme2p1(const
ARMISARegisters *id)
/*
* Combinations of feature tests, for ease of use with TRANS_FEAT.
*/
+static inline bool isar_feature_aa64_sme_or_sve(const ARMISARegisters *id)
+{
+ return isar_feature_aa64_sme(id) || isar_feature_aa64_sve(id);
+}
+
+static inline bool isar_feature_aa64_sme_or_sve2(const ARMISARegisters *id)
+{
+ return isar_feature_aa64_sme(id) || isar_feature_aa64_sve2(id);
+}
+
static inline bool isar_feature_aa64_sme_or_sve2p1(const ARMISARegisters *id)
{
return isar_feature_aa64_sme(id) || isar_feature_aa64_sve2p1(id);
Reviewed-by: Richard Henderson <[email protected]>
r~
