On 2/2/26 23:33, Peter Maydell wrote:
As with I8MM, the BF16 field of ID_AA64ZFR0_EL1 is set when the
CPU implements FEAT_BF16 and either FEAT_SVE or FEAT_SME, so
we need to have separate checks for "(SVE || SME) && BF16"
and "SVE && BF16". Follow the same pattern as with I8MM:
* aa64_sve_sme_bf16 means (SVE || SME) && BF16
* aa64_sve_bf16 means (SVE && BF16)
BFMMLA is the only SVE BF16 insn that isn't in SME.
Signed-off-by: Peter Maydell<[email protected]>
---
target/arm/cpu-features.h | 7 ++++++-
target/arm/tcg/translate-sve.c | 16 ++++++++--------
2 files changed, 14 insertions(+), 9 deletions(-)
Reviewed-by: Richard Henderson <[email protected]>
r~
