* common/config/i386/cpuinfo.h (XSTATE_SCALEDATA):
(XCR_ACE_ENABLED_MASK):
(get_available_features):
* common/config/i386/i386-common.cc (OPTION_MASK_ISA2_ACE_V1_SET):
(OPTION_MASK_ISA2_AVX10_V2_AUX_UNSET):
(OPTION_MASK_ISA2_ACE_V1_UNSET):
(OPTION_MASK_ISA2_TILE_UNSET):
(ix86_handle_option):
* common/config/i386/i386-cpuinfo.h (enum processor_features):
* common/config/i386/i386-isas.h:
* config/i386/cpuid.h (bit_ACE):
* config/i386/i386-c.cc (ix86_target_macros_internal):
* config/i386/i386-isa.def (ACE_V1):
* config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p):
* config/i386/i386.opt:
* doc/extend.texi:
* doc/invoke.texi:
gcc/testsuite/ChangeLog:
* gcc.target/i386/funcspec-56.inc:
* gcc.target/i386/tile-1.c: New test.
* gcc.target/i386/tile-2.c: New test.
gcc/common/config/i386/cpuinfo.h | 31 ++++++++++++++++++-
gcc/common/config/i386/i386-common.cc | 25 +++++++++++++--
gcc/common/config/i386/i386-cpuinfo.h | 1 +
gcc/common/config/i386/i386-isas.h | 1 +
gcc/config/i386/cpuid.h | 3 ++
gcc/config/i386/i386-c.cc | 2 ++
gcc/config/i386/i386-isa.def | 1 +
gcc/config/i386/i386-options.cc | 2 ++
gcc/config/i386/i386.opt | 4 +++
gcc/doc/extend.texi | 5 +++
gcc/doc/invoke.texi | 2 +-
gcc/testsuite/gcc.target/i386/funcspec-56.inc | 2 ++
gcc/testsuite/gcc.target/i386/tile-1.c | 11 +++++++
gcc/testsuite/gcc.target/i386/tile-2.c | 11 +++++++
14 files changed, 97 insertions(+), 4 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/tile-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/tile-2.c
diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
index 6310e7294da..f284917b3f5 100644
--- a/gcc/common/config/i386/cpuinfo.h
+++ b/gcc/common/config/i386/cpuinfo.h
@@ -804,6 +804,7 @@ get_available_features (struct __processor_model *cpu_model,
#define XSTATE_TILECFG 0x20000
#define XSTATE_TILEDATA 0x40000
#define XSTATE_APX_F 0x80000
+#define XSTATE_SCALEDATA 0x80000
#define XCR_AVX_ENABLED_MASK \
(XSTATE_SSE | XSTATE_YMM)
@@ -812,17 +813,23 @@ get_available_features (struct __processor_model
*cpu_model,
#define XCR_AMX_ENABLED_MASK \
(XSTATE_TILECFG | XSTATE_TILEDATA)
#define XCR_APX_F_ENABLED_MASK XSTATE_APX_F
+#define XCR_ACE_ENABLED_MASK \
+ (XCR_AMX_ENABLED_MASK | XSTATE_SCALEDATA)
/* Check if AVX, AVX512 and APX are usable. */
int avx_usable = 0;
int avx512_usable = 0;
int amx_usable = 0;
int apx_usable = 0;
+ int ace_usable = 0;
/* Check if KL is usable. */
int has_kl = 0;
/* Record AVX10 version. */
int avx10_set = 0;
int version = 0;
+ int ace_set = 0;
+ int ace_version = 0;
+ int avx10_v2_aux_set = 0;
if ((ecx & bit_OSXSAVE))
{
/* Check if XMM, YMM, OPMASK, upper 256 bits of ZMM0-ZMM15 and
@@ -840,6 +847,8 @@ get_available_features (struct __processor_model *cpu_model,
}
amx_usable = ((xcrlow & XCR_AMX_ENABLED_MASK)
== XCR_AMX_ENABLED_MASK);
+ ace_usable = ((xcrlow & XCR_ACE_ENABLED_MASK)
+ == XCR_ACE_ENABLED_MASK);
apx_usable = ((xcrlow & XCR_APX_F_ENABLED_MASK)
== XCR_APX_F_ENABLED_MASK);
}
@@ -1057,6 +1066,11 @@ get_available_features (struct __processor_model
*cpu_model,
if (edx & bit_APX_F)
set_feature (FEATURE_APX_F);
}
+ if (ace_usable)
+ {
+ if (ecx & bit_ACE)
+ ace_set = 1;
+ }
}
}
@@ -1142,7 +1156,22 @@ get_available_features (struct __processor_model
*cpu_model,
/* CPUID.(EAX=24H, ECX=1) for AVX10_V2_AUX features. */
__cpuid_count (0x24, 1, eax, ebx, ecx, edx);
if (ecx & bit_AVX10_V2_AUX)
- set_feature (FEATURE_AVX10_V2_AUX);
+ {
+ set_feature (FEATURE_AVX10_V2_AUX);
+ avx10_v2_aux_set = 1;
+ }
+ }
+
+ /* Get Advanced Features at level 0x1D (eax = 0x1D, ecx = 2). */
+ /* TODO: ADD check for AUX v1 and v2*/
+ if (ace_set && max_cpuid_level >= 0x1d)
+ {
+ __cpuid_count (0x1d, 2, eax, ebx, ecx, edx);
+ ace_version = eax & 0xff;
+ if((version >=1) &&
+ (avx10_v2_aux_set == 1) &&
+ (ace_version >= 1))
+ set_feature (FEATURE_ACE_V1);
}
/* Check cpuid level of extended features. */
diff --git a/gcc/common/config/i386/i386-common.cc
b/gcc/common/config/i386/i386-common.cc
index 4a306827715..68a27109589 100644
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -144,6 +144,9 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA2_AVX10_V2_AUX_SET \
(OPTION_MASK_ISA2_AVX10_1_SET | OPTION_MASK_ISA2_AVX10_V2_AUX)
#define OPTION_MASK_ISA2_TILE_SET OPTION_MASK_ISA2_TILE
+#define OPTION_MASK_ISA2_ACE_V1_SET \
+ (OPTION_MASK_ISA2_TILE_SET | OPTION_MASK_ISA2_AVX10_V2_AUX_SET \
+ | OPTION_MASK_ISA2_ACE_V1)
/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
as -msse4.2. */
@@ -338,9 +341,12 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA2_MOVRS_UNSET OPTION_MASK_ISA2_MOVRS
#define OPTION_MASK_ISA2_AMX_MOVRS_UNSET OPTION_MASK_ISA2_AMX_MOVRS
#define OPTION_MASK_ISA2_AVX512BMM_UNSET OPTION_MASK_ISA2_AVX512BMM
-#define OPTION_MASK_ISA2_AVX10_V2_AUX_UNSET OPTION_MASK_ISA2_AVX10_V2_AUX
+#define OPTION_MASK_ISA2_AVX10_V2_AUX_UNSET \
+ (OPTION_MASK_ISA2_ACE_V1_UNSET | OPTION_MASK_ISA2_AVX10_V2_AUX)
+#define OPTION_MASK_ISA2_ACE_V1_UNSET OPTION_MASK_ISA2_ACE_V1
#define OPTION_MASK_ISA2_TILE_UNSET \
- (OPTION_MASK_ISA2_TILE | OPTION_MASK_ISA2_AMX_TILE_UNSET)
+ (OPTION_MASK_ISA2_TILE | OPTION_MASK_ISA2_AMX_TILE_UNSET \
+ | OPTION_MASK_ISA2_ACE_V1_UNSET)
/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
as -mno-sse4.1. */
#define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
@@ -1001,6 +1007,21 @@ ix86_handle_option (struct gcc_options *opts,
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXVNNI_UNSET;
}
return true;
+
+ case OPT_mace_v1:
+ if (value)
+ {
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_ACE_V1_SET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ACE_V1_SET;
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET;
+ opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET;
+ }
+ else
+ {
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_ACE_V1_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ACE_V1_UNSET;
+ }
+ return true;
case OPT_mtile:
if (value)
diff --git a/gcc/common/config/i386/i386-cpuinfo.h
b/gcc/common/config/i386/i386-cpuinfo.h
index 20444fae38b..9d01c15cbc1 100644
--- a/gcc/common/config/i386/i386-cpuinfo.h
+++ b/gcc/common/config/i386/i386-cpuinfo.h
@@ -285,6 +285,7 @@ enum processor_features
FEATURE_AMX_MOVRS,
FEATURE_AVX512BMM,
FEATURE_AVX10_V2_AUX,
+ FEATURE_ACE_V1,
FEATURE_TILE,
CPU_FEATURE_MAX
};
diff --git a/gcc/common/config/i386/i386-isas.h
b/gcc/common/config/i386/i386-isas.h
index ec3e9273a47..b58a2e20d63 100644
--- a/gcc/common/config/i386/i386-isas.h
+++ b/gcc/common/config/i386/i386-isas.h
@@ -194,5 +194,6 @@ ISA_NAMES_TABLE_START
ISA_NAMES_TABLE_ENTRY("avx512bmm", FEATURE_AVX512BMM, P_NONE, "-mavx512bmm")
ISA_NAMES_TABLE_ENTRY("avx10-v2-aux", FEATURE_AVX10_V2_AUX, P_NONE,
"-mavx10-v2-aux")
+ ISA_NAMES_TABLE_ENTRY("ace-v1", FEATURE_ACE_V1, P_NONE, "-mace-v1")
ISA_NAMES_TABLE_ENTRY("tile", FEATURE_TILE, P_NONE, "-mtile")
ISA_NAMES_TABLE_END
diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h
index 4d03bedcc83..7d46bc91154 100644
--- a/gcc/config/i386/cpuid.h
+++ b/gcc/config/i386/cpuid.h
@@ -153,6 +153,9 @@
#define bit_AVX10 (1 << 19)
#define bit_APX_F (1 << 21)
+/* %ecx */
+#define bit_ACE (1 << 11)
+
/* Extended State Enumeration Sub-leaf (%eax == 0xd, %ecx == 1) */
#define bit_XSAVEOPT (1 << 0)
#define bit_XSAVEC (1 << 1)
diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc
index 7f2e2f58109..ec1a3ac4ddf 100644
--- a/gcc/config/i386/i386-c.cc
+++ b/gcc/config/i386/i386-c.cc
@@ -794,6 +794,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
def_or_undef (parse_in, "__AVX512BMM__");
if (isa_flag2 & OPTION_MASK_ISA2_AVX10_V2_AUX)
def_or_undef (parse_in, "__AVX10_V2_AUX__");
+ if (isa_flag2 & OPTION_MASK_ISA2_ACE_V1)
+ def_or_undef (parse_in, "__ACE_V1__");
if (isa_flag2 & OPTION_MASK_ISA2_TILE)
def_or_undef (parse_in, "__TILE__");
if (TARGET_IAMCU)
diff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def
index 58800e1dc4f..711fe6a459f 100644
--- a/gcc/config/i386/i386-isa.def
+++ b/gcc/config/i386/i386-isa.def
@@ -127,4 +127,5 @@ DEF_PTA(MOVRS)
DEF_PTA(AMX_MOVRS)
DEF_PTA(AVX512BMM)
DEF_PTA(AVX10_V2_AUX)
+DEF_PTA(ACE_V1)
DEF_PTA(TILE)
diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index 84f8cc683fe..5e382de2dee 100644
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -277,6 +277,7 @@ static struct ix86_target_opts isa2_opts[] =
{ "-mamx-movrs", OPTION_MASK_ISA2_AMX_MOVRS },
{ "-mavx512bmm", OPTION_MASK_ISA2_AVX512BMM },
{ "-mavx10-v2-aux", OPTION_MASK_ISA2_AVX10_V2_AUX },
+ { "-mace-v1", OPTION_MASK_ISA2_ACE_V1 },
{ "-mtile", OPTION_MASK_ISA2_TILE }
};
static struct ix86_target_opts isa_opts[] =
@@ -1144,6 +1145,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree
args, char *p_strings[],
IX86_ATTR_ISA ("amx-movrs", OPT_mamx_movrs),
IX86_ATTR_ISA ("avx512bmm", OPT_mavx512bmm),
IX86_ATTR_ISA ("avx10-v2-aux", OPT_mavx10_v2_aux),
+ IX86_ATTR_ISA ("ace-v1", OPT_mace_v1),
IX86_ATTR_ISA ("tile", OPT_mtile),
/* enum options */
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index db45ed64c61..494e0b901ce 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -1394,6 +1394,10 @@ mavx10-v2-aux
Target Mask(ISA2_AVX10_V2_AUX) Var(ix86_isa_flags2) Save
Support AVX10_V2_AUX built-in functions and code generation.
+mace-v1
+Target Mask(ISA2_ACE_V1) Var(ix86_isa_flags2) Save
+Support ACE built-in functions and code generation.
+
mtile
Target Mask(ISA2_TILE) Var(ix86_isa_flags2) Save
Support TILE built-in functions and code generation.
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 9b54348d18f..024a5b7329b 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -9507,6 +9507,11 @@ Enable/disable the generation of the MOVRS instructions.
@itemx no-amx-movrs
Enable/disable the generation of the AMX-MOVRS instructions.
+@cindex @code{target("ace-v1")} function attribute, x86
+@item ace
+@itemx no-ace
+Enable/disable the generation of the ACE instructions.
+
@atindex @code{target("cld")}, x86
@item cld
@itemx no-cld
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index a8685896897..e08b0fff8c3 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1552,7 +1552,7 @@ See RS/6000 and PowerPC Options.
-mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mapxf
-musermsr -mavx10.1 -mavx10.2 -mamx-avx512 -mamx-tf32 -mmovrs
-mamx-movrs -mavx512bmm -mavx10-v2-aux -mcldemote -mms-bitfields
--mno-align-stringops -minline-all-stringops
+-mace-v1 -mno-align-stringops -minline-all-stringops
-minline-stringops-dynamically -mstringop-strategy=@var{alg}
-mkl -mwidekl
-mmemcpy-strategy=@var{strategy} -mmemset-strategy=@var{strategy}
diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
index 9d4eb832b1e..c33ecdc3ad7 100644
--- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
+++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
@@ -94,6 +94,7 @@ extern void test_amx_fp8 (void)
__attribute__((__target__("amx-f
extern void test_movrs (void)
__attribute__((__target__("movrs")));
extern void test_amx_movrs (void)
__attribute__((__target__("amx-movrs")));
extern void test_tile (void)
__attribute__((__target__("tile")));
+extern void test_ace_v1 (void)
__attribute__((__target__("ace-v1")));
extern void test_no_sgx (void)
__attribute__((__target__("no-sgx")));
extern void test_no_avx512vpopcntdq(void)
__attribute__((__target__("no-avx512vpopcntdq")));
@@ -189,6 +190,7 @@ extern void test_no_amx_fp8 (void)
__attribute__((__target__("no-am
extern void test_no_movrs (void)
__attribute__((__target__("no-movrs")));
extern void test_no_amx_movrs (void)
__attribute__((__target__("no-amx-movrs")));
extern void test_no_tile (void)
__attribute__((__target__("no-tile")));
+extern void test_no_ace_v1 (void)
__attribute__((__target__("no-ace-v1")));
extern void test_arch_nocona (void)
__attribute__((__target__("arch=nocona")));
extern void test_arch_core2 (void)
__attribute__((__target__("arch=core2")));
diff --git a/gcc/testsuite/gcc.target/i386/tile-1.c
b/gcc/testsuite/gcc.target/i386/tile-1.c
new file mode 100644
index 00000000000..55d05258f02
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/tile-1.c
@@ -0,0 +1,11 @@
+/* Verify that -mace-v1 implies -mtile (ACE enables TILE). */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mace-v1" } */
+
+#ifndef __ACE_V1__
+#error "-mace-v1 should define __ACE_V1__"
+#endif
+
+#ifndef __TILE__
+#error "-mace-v1 should imply -mtile and define __TILE__"
+#endif
diff --git a/gcc/testsuite/gcc.target/i386/tile-2.c
b/gcc/testsuite/gcc.target/i386/tile-2.c
new file mode 100644
index 00000000000..b6d8773b81a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/tile-2.c
@@ -0,0 +1,11 @@
+/* Verify that -mtile does NOT imply -mace-v1 (the implication is one-way). */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mtile -mno-ace-v1" } */
+
+#ifndef __TILE__
+#error "-mtile should define __TILE__"
+#endif
+
+#ifdef __ACE_V1__
+#error "-mtile must not imply -mace-v1; __ACE_V1__ should not be defined"
+#endif
--
2.34.1
