---
gcc/ChangeLog:
* config/i386/avx10_v2_auxintrin.h (__attribute__):
(_mm_cvtbiasps_bf8):
(_mm_mask_cvtbiasps_bf8):
(_mm_maskz_cvtbiasps_bf8):
(_mm256_cvtbiasps_bf8):
(_mm256_mask_cvtbiasps_bf8):
(_mm256_maskz_cvtbiasps_bf8):
(_mm512_cvtbiasps_bf8):
(_mm512_mask_cvtbiasps_bf8):
(_mm512_maskz_cvtbiasps_bf8):
(_mm_cvts_biasps_bf8):
(_mm_mask_cvts_biasps_bf8):
(_mm_maskz_cvts_biasps_bf8):
(_mm256_cvts_biasps_bf8):
(_mm256_mask_cvts_biasps_bf8):
(_mm256_maskz_cvts_biasps_bf8):
(_mm512_cvts_biasps_bf8):
(_mm512_mask_cvts_biasps_bf8):
(_mm512_maskz_cvts_biasps_bf8):
(_mm_cvtbiasps_hf8):
(_mm_mask_cvtbiasps_hf8):
(_mm_maskz_cvtbiasps_hf8):
(_mm256_cvtbiasps_hf8):
(_mm256_mask_cvtbiasps_hf8):
(_mm256_maskz_cvtbiasps_hf8):
(_mm512_cvtbiasps_hf8):
(_mm512_mask_cvtbiasps_hf8):
(_mm512_maskz_cvtbiasps_hf8):
(_mm_cvts_biasps_hf8):
(_mm_mask_cvts_biasps_hf8):
(_mm_maskz_cvts_biasps_hf8):
(_mm256_cvts_biasps_hf8):
(_mm256_mask_cvts_biasps_hf8):
(_mm256_maskz_cvts_biasps_hf8):
(_mm512_cvts_biasps_hf8):
(_mm512_mask_cvts_biasps_hf8):
(_mm512_maskz_cvts_biasps_hf8):
* config/i386/i386-builtin-types.def (V16QI):
* config/i386/i386-builtin.def (BDESC):
* config/i386/i386-expand.cc (ix86_expand_args_builtin):
* config/i386/sse.md (vcvt<convertbiasps2fp8><mode>):
(vcvt<convertbiasps2fp8><mode>_mask):
(*vcvt<convertbiasps2fp8><mode>_mask):
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx10_2-v2-aux-convert-3.c: New test.
gcc/config/i386/avx10_v2_auxintrin.h | 385 ++++++++++++++++++
gcc/config/i386/i386-builtin-types.def | 3 +
gcc/config/i386/i386-builtin.def | 12 +
gcc/config/i386/i386-expand.cc | 3 +
gcc/config/i386/sse.md | 65 +++
.../i386/avx10_2-v2-aux-convert-3.c | 88 ++++
6 files changed, 556 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-v2-aux-convert-3.c
diff --git a/gcc/config/i386/avx10_v2_auxintrin.h
b/gcc/config/i386/avx10_v2_auxintrin.h
index a0da0ec4f3a..18997ba8e6f 100644
--- a/gcc/config/i386/avx10_v2_auxintrin.h
+++ b/gcc/config/i386/avx10_v2_auxintrin.h
@@ -587,6 +587,391 @@ _mm512_maskz_cvts_rops_hf8 (__mmask16 __U, __m512 __A)
(__mmask16) __U);
}
+// VCVTBIASPS2BF8 - 128-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtbiasps_bf8(__m128i __A, __m128 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8128_mask ((__v16qi) __A,
+ (__v4sf) __B,
+ (__v16qi)(__m128i)
_mm_undefined_si128 (),
+ (__mmask8) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_cvtbiasps_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8128_mask ((__v16qi) __A,
+ (__v4sf) __B,
+ (__v16qi) __W,
+ (__mmask8) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_cvtbiasps_bf8(__mmask8 __U, __m128i __A, __m128 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8128_mask ((__v16qi) __A,
+ (__v4sf) __B,
+ (__v16qi)(__m128i)
_mm_setzero_si128 (),
+ (__mmask8) __U);
+}
+
+// VCVTBIASPS2BF8 - 256-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvtbiasps_bf8(__m256i __A, __m256 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8256_mask ((__v32qi) __A,
+ (__v8sf) __B,
+ (__v16qi)
_mm_undefined_si128 (),
+ (__mmask8) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvtbiasps_bf8(__m128i __W, __mmask8 __U, __m256i __A, __m256 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8256_mask ((__v32qi) __A,
+ (__v8sf) __B,
+ (__v16qi) __W,
+ (__mmask8) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvtbiasps_bf8(__mmask8 __U, __m256i __A, __m256 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8256_mask ((__v32qi) __A,
+ (__v8sf) __B,
+ (__v16qi)
_mm_setzero_si128 (),
+ (__mmask8) __U);
+}
+
+// VCVTBIASPS2BF8 - 512-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvtbiasps_bf8(__m512i __A, __m512 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8512_mask ((__v64qi) __A,
+ (__v16sf) __B,
+ (__v16qi)
_mm_undefined_si128 (),
+ (__mmask16) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_cvtbiasps_bf8(__m128i __W, __mmask16 __U, __m512i __A, __m512 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8512_mask ((__v64qi) __A,
+ (__v16sf) __B,
+ (__v16qi) __W,
+ (__mmask16) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_cvtbiasps_bf8(__mmask16 __U, __m512i __A, __m512 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8512_mask ((__v64qi) __A,
+ (__v16sf) __B,
+ (__v16qi)
_mm_setzero_si128 (),
+ (__mmask16) __U);
+}
+
+// VCVTBIASPS2BF8S - 128-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvts_biasps_bf8(__m128i __A, __m128 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8s128_mask ((__v16qi) __A,
+ (__v4sf) __B,
+ (__v16qi)
_mm_undefined_si128 (),
+ (__mmask8) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_cvts_biasps_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8s128_mask ((__v16qi) __A,
+ (__v4sf) __B,
+ (__v16qi) __W,
+ (__mmask8) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_cvts_biasps_bf8(__mmask8 __U, __m128i __A, __m128 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8s128_mask ((__v16qi) __A,
+ (__v4sf) __B,
+ (__v16qi)
_mm_setzero_si128 (),
+ (__mmask8) __U);
+}
+
+// VCVTBIASPS2BF8S - 256-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvts_biasps_bf8(__m256i __A, __m256 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8s256_mask ((__v32qi) __A,
+ (__v8sf) __B,
+ (__v16qi)
_mm_undefined_si128 (),
+ (__mmask8) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvts_biasps_bf8(__m128i __W, __mmask8 __U, __m256i __A, __m256 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8s256_mask ((__v32qi) __A,
+ (__v8sf) __B,
+ (__v16qi) __W,
+ (__mmask8) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvts_biasps_bf8(__mmask8 __U, __m256i __A, __m256 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8s256_mask ((__v32qi) __A,
+ (__v8sf) __B,
+ (__v16qi)
_mm_setzero_si128 (),
+ (__mmask8) __U);
+}
+
+// VCVTBIASPS2BF8S - 512-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvts_biasps_bf8(__m512i __A, __m512 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8s512_mask ((__v64qi) __A,
+ (__v16sf) __B,
+ (__v16qi)
_mm_undefined_si128 (),
+ (__mmask16) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_cvts_biasps_bf8(__m128i __W, __mmask16 __U, __m512i __A, __m512
__B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8s512_mask ((__v64qi) __A,
+ (__v16sf) __B,
+ (__v16qi) __W,
+ (__mmask16) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_cvts_biasps_bf8(__mmask16 __U, __m512i __A, __m512 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8s512_mask ((__v64qi) __A,
+ (__v16sf) __B,
+ (__v16qi)
_mm_setzero_si128 (),
+ (__mmask16) __U);
+}
+
+// VCVTBIASPS2HF8 - 128-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtbiasps_hf8(__m128i __A, __m128 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8128_mask ((__v16qi) __A,
+ (__v4sf) __B,
+ (__v16qi)
_mm_undefined_si128 (),
+ (__mmask8) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_cvtbiasps_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8128_mask ((__v16qi) __A,
+ (__v4sf) __B,
+ (__v16qi) __W,
+ (__mmask8) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_cvtbiasps_hf8(__mmask8 __U, __m128i __A, __m128 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8128_mask ((__v16qi) __A,
+ (__v4sf) __B,
+ (__v16qi)
_mm_setzero_si128 (),
+ (__mmask8) __U);
+}
+
+// VCVTBIASPS2HF8 - 256-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvtbiasps_hf8(__m256i __A, __m256 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8256_mask ((__v32qi) __A,
+ (__v8sf) __B,
+ (__v16qi)
_mm_undefined_si128 (),
+ (__mmask8) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvtbiasps_hf8(__m128i __W, __mmask8 __U, __m256i __A, __m256 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8256_mask ((__v32qi) __A,
+ (__v8sf) __B,
+ (__v16qi) __W,
+ (__mmask8) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvtbiasps_hf8(__mmask8 __U, __m256i __A, __m256 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8256_mask ((__v32qi) __A,
+ (__v8sf) __B,
+ (__v16qi)
_mm_setzero_si128 (),
+ (__mmask8) __U);
+}
+
+// VCVTBIASPS2HF8 - 512-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvtbiasps_hf8(__m512i __A, __m512 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8512_mask ((__v64qi) __A,
+ (__v16sf) __B,
+ (__v16qi)
_mm_undefined_si128 (),
+ (__mmask16) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_cvtbiasps_hf8(__m128i __W, __mmask16 __U, __m512i __A, __m512 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8512_mask ((__v64qi) __A,
+ (__v16sf) __B,
+ (__v16qi) __W,
+ (__mmask16) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_cvtbiasps_hf8(__mmask16 __U, __m512i __A, __m512 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8512_mask ((__v64qi) __A,
+ (__v16sf) __B,
+ (__v16qi)
_mm_setzero_si128 (),
+ (__mmask16) __U);
+}
+
+// VCVTBIASPS2HF8S - 128-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvts_biasps_hf8(__m128i __A, __m128 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8s128_mask ((__v16qi) __A,
+ (__v4sf) __B,
+ (__v16qi)
_mm_undefined_si128 (),
+ (__mmask8) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_cvts_biasps_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8s128_mask ((__v16qi) __A,
+ (__v4sf) __B,
+ (__v16qi) __W,
+ (__mmask8) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_cvts_biasps_hf8(__mmask8 __U, __m128i __A, __m128 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8s128_mask ((__v16qi) __A,
+ (__v4sf) __B,
+ (__v16qi)
_mm_setzero_si128 (),
+ (__mmask8) __U);
+}
+
+// VCVTBIASPS2HF8S - 256-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvts_biasps_hf8(__m256i __A, __m256 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8s256_mask ((__v32qi) __A,
+ (__v8sf) __B,
+ (__v16qi)
_mm_undefined_si128 (),
+ (__mmask8) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvts_biasps_hf8(__m128i __W, __mmask8 __U, __m256i __A, __m256 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8s256_mask ((__v32qi) __A,
+ (__v8sf) __B,
+ (__v16qi) __W,
+ (__mmask8) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvts_biasps_hf8(__mmask8 __U, __m256i __A, __m256 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8s256_mask ((__v32qi) __A,
+ (__v8sf) __B,
+ (__v16qi)
_mm_setzero_si128 (),
+ (__mmask8) __U);
+}
+
+// VCVTBIASPS2HF8S - 512-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvts_biasps_hf8(__m512i __A, __m512 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8s512_mask ((__v64qi) __A,
+ (__v16sf) __B,
+ (__v16qi)
_mm_undefined_si128 (),
+ (__mmask16) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_cvts_biasps_hf8(__m128i __W, __mmask16 __U, __m512i __A, __m512
__B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8s512_mask ((__v64qi) __A,
+ (__v16sf) __B,
+ (__v16qi) __W,
+ (__mmask16) __U);
+}
+
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_cvts_biasps_hf8(__mmask16 __U, __m512i __A, __m512 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8s512_mask ((__v64qi) __A,
+ (__v16sf) __B,
+ (__v16qi)
_mm_setzero_si128 (),
+ (__mmask16) __U);
+}
+
#ifdef __DISABLE_AVX10_V2_AUX__
#undef __DISABLE_AVX10_V2_AUX__
#pragma GCC pop_options
diff --git a/gcc/config/i386/i386-builtin-types.def
b/gcc/config/i386/i386-builtin-types.def
index f35bdcd2056..59bc019c637 100644
--- a/gcc/config/i386/i386-builtin-types.def
+++ b/gcc/config/i386/i386-builtin-types.def
@@ -1478,6 +1478,9 @@ DEF_FUNCTION_TYPE (V8SI, V8DF, V8SI, UQI)
DEF_FUNCTION_TYPE (V16QI, V4SF, V16QI, UQI)
DEF_FUNCTION_TYPE (V16QI, V8SF, V16QI, UQI)
DEF_FUNCTION_TYPE (V16QI, V16SF, V16QI, UHI)
+DEF_FUNCTION_TYPE (V16QI, V16QI, V4SF, V16QI, UQI)
+DEF_FUNCTION_TYPE (V16QI, V32QI, V8SF, V16QI, UQI)
+DEF_FUNCTION_TYPE (V16QI, V64QI, V16SF, V16QI, UHI)
# SM4 builtins
DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI)
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index 6d4f9869d23..cdb28295000 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -3388,6 +3388,18 @@ BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX,
CODE_FOR_vcvtrops2hf8v16sf_mask, "__bui
BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvtrops2hf8sv4sf_mask,
"__builtin_ia32_vcvtrops2hf8s128_mask", IX86_BUILTIN_VCVTROPS2HF8S128_MASK,
UNKNOWN, (int) V16QI_FTYPE_V4SF_V16QI_UQI)
BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvtrops2hf8sv8sf_mask,
"__builtin_ia32_vcvtrops2hf8s256_mask", IX86_BUILTIN_VCVTROPS2HF8S256_MASK,
UNKNOWN, (int) V16QI_FTYPE_V8SF_V16QI_UQI)
BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvtrops2hf8sv16sf_mask,
"__builtin_ia32_vcvtrops2hf8s512_mask", IX86_BUILTIN_VCVTROPS2HF8S512_MASK,
UNKNOWN, (int) V16QI_FTYPE_V16SF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvtbiasps2bf8v4sf_mask,
"__builtin_ia32_vcvtbiasps2bf8128_mask", IX86_BUILTIN_VCVTBIASPS2BF8128_MASK,
UNKNOWN, (int) V16QI_FTYPE_V16QI_V4SF_V16QI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvtbiasps2bf8v8sf_mask,
"__builtin_ia32_vcvtbiasps2bf8256_mask", IX86_BUILTIN_VCVTBIASPS2BF8256_MASK,
UNKNOWN, (int) V16QI_FTYPE_V32QI_V8SF_V16QI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvtbiasps2bf8v16sf_mask,
"__builtin_ia32_vcvtbiasps2bf8512_mask", IX86_BUILTIN_VCVTBIASPS2BF8512_MASK,
UNKNOWN, (int) V16QI_FTYPE_V64QI_V16SF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvtbiasps2bf8sv4sf_mask,
"__builtin_ia32_vcvtbiasps2bf8s128_mask", IX86_BUILTIN_VCVTBIASPS2BF8S128_MASK,
UNKNOWN, (int) V16QI_FTYPE_V16QI_V4SF_V16QI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvtbiasps2bf8sv8sf_mask,
"__builtin_ia32_vcvtbiasps2bf8s256_mask", IX86_BUILTIN_VCVTBIASPS2BF8S256_MASK,
UNKNOWN, (int) V16QI_FTYPE_V32QI_V8SF_V16QI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvtbiasps2bf8sv16sf_mask,
"__builtin_ia32_vcvtbiasps2bf8s512_mask", IX86_BUILTIN_VCVTBIASPS2BF8S512_MASK,
UNKNOWN, (int) V16QI_FTYPE_V64QI_V16SF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvtbiasps2hf8v4sf_mask,
"__builtin_ia32_vcvtbiasps2hf8128_mask", IX86_BUILTIN_VCVTBIASPS2HF8128_MASK,
UNKNOWN, (int) V16QI_FTYPE_V16QI_V4SF_V16QI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvtbiasps2hf8v8sf_mask,
"__builtin_ia32_vcvtbiasps2hf8256_mask", IX86_BUILTIN_VCVTBIASPS2HF8256_MASK,
UNKNOWN, (int) V16QI_FTYPE_V32QI_V8SF_V16QI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvtbiasps2hf8v16sf_mask,
"__builtin_ia32_vcvtbiasps2hf8512_mask", IX86_BUILTIN_VCVTBIASPS2HF8512_MASK,
UNKNOWN, (int) V16QI_FTYPE_V64QI_V16SF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvtbiasps2hf8sv4sf_mask,
"__builtin_ia32_vcvtbiasps2hf8s128_mask", IX86_BUILTIN_VCVTBIASPS2HF8S128_MASK,
UNKNOWN, (int) V16QI_FTYPE_V16QI_V4SF_V16QI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvtbiasps2hf8sv8sf_mask,
"__builtin_ia32_vcvtbiasps2hf8s256_mask", IX86_BUILTIN_VCVTBIASPS2HF8S256_MASK,
UNKNOWN, (int) V16QI_FTYPE_V32QI_V8SF_V16QI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvtbiasps2hf8sv16sf_mask,
"__builtin_ia32_vcvtbiasps2hf8s512_mask", IX86_BUILTIN_VCVTBIASPS2HF8S512_MASK,
UNKNOWN, (int) V16QI_FTYPE_V64QI_V16SF_V16QI_UHI)
/* Builtins with rounding support. */
BDESC_END (ARGS, ROUND_ARGS)
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index 2bd26ce5d81..a31a19c744c 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -13065,6 +13065,9 @@ ix86_expand_args_builtin (const struct
builtin_description *d,
case V16QI_FTYPE_V16QI_V8HF_V16QI_UHI:
case V16QI_FTYPE_V32QI_V16HF_V16QI_UHI:
case V32QI_FTYPE_V64QI_V32HF_V32QI_USI:
+ case V16QI_FTYPE_V16QI_V4SF_V16QI_UQI:
+ case V16QI_FTYPE_V32QI_V8SF_V16QI_UQI:
+ case V16QI_FTYPE_V64QI_V16SF_V16QI_UHI:
nargs = 4;
break;
case V2DF_FTYPE_V2DF_V2DF_V2DI_INT:
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index cdaecc713a6..c72e24da6cc 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -266,6 +266,10 @@
UNSPEC_VCVTPS2HF8S
UNSPEC_VCVTROPS2HF8
UNSPEC_VCVTROPS2HF8S
+ UNSPEC_VCVTBIASPS2BF8
+ UNSPEC_VCVTBIASPS2BF8S
+ UNSPEC_VCVTBIASPS2HF8
+ UNSPEC_VCVTBIASPS2HF8S
])
(define_c_enum "unspecv" [
@@ -33861,3 +33865,64 @@
"vcvt<convertps2fp8>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
[(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
+
+;; FP32 to FP8 biased converts (VCVTBIASPS2BF8, VCVTBIASPS2BF8S,
+;; VCVTBIASPS2HF8, VCVTBIASPS2HF8S)
+
+(define_int_iterator UNSPEC_CONVERTBIASPS2FP8
+ [UNSPEC_VCVTBIASPS2BF8 UNSPEC_VCVTBIASPS2BF8S
+ UNSPEC_VCVTBIASPS2HF8 UNSPEC_VCVTBIASPS2HF8S])
+
+(define_int_attr convertbiasps2fp8
+ [(UNSPEC_VCVTBIASPS2BF8 "biasps2bf8")
+ (UNSPEC_VCVTBIASPS2BF8S "biasps2bf8s")
+ (UNSPEC_VCVTBIASPS2HF8 "biasps2hf8")
+ (UNSPEC_VCVTBIASPS2HF8S "biasps2hf8s")])
+
+(define_mode_attr VxQI_SRC
+ [(V4SF "V16QI") (V8SF "V32QI") (V16SF "V64QI")])
+
+(define_insn "vcvt<convertbiasps2fp8><mode>"
+ [(set (match_operand:V16QI 0 "register_operand" "=v")
+ (unspec:V16QI
+ [(match_operand:<VxQI_SRC> 1 "register_operand" "v")
+ (match_operand:VF1_AVX512VL 2 "nonimmediate_operand" "vm")]
+ UNSPEC_CONVERTBIASPS2FP8))]
+ "TARGET_AVX10_V2_AUX"
+ "vcvt<convertbiasps2fp8>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
+
+(define_expand "vcvt<convertbiasps2fp8><mode>_mask"
+ [(set (match_operand:V16QI 0 "register_operand")
+ (vec_merge:V16QI
+ (unspec:V16QI
+ [(match_operand:<VxQI_SRC> 1 "register_operand")
+ (match_operand:VF1_AVX512VL 2 "nonimmediate_operand")]
+ UNSPEC_CONVERTBIASPS2FP8)
+ (match_operand:V16QI 3 "nonimm_or_0_operand")
+ (match_operand:<avx512fmaskmode> 4 "register_or_constm1_operand")))]
+ "TARGET_AVX10_V2_AUX"
+{
+ if (CONST_INT_P (operands[4]))
+ {
+ emit_insn (gen_vcvt<convertbiasps2fp8><mode> (operands[0],
+ operands[1],
+ operands[2]));
+ DONE;
+ }
+})
+
+(define_insn "*vcvt<convertbiasps2fp8><mode>_mask"
+ [(set (match_operand:V16QI 0 "register_operand" "=v")
+ (vec_merge:V16QI
+ (unspec:V16QI
+ [(match_operand:<VxQI_SRC> 1 "register_operand" "v")
+ (match_operand:VF1_AVX512VL 2 "nonimmediate_operand" "vm")]
+ UNSPEC_CONVERTBIASPS2FP8)
+ (match_operand:V16QI 3 "nonimm_or_0_operand" "0C")
+ (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
+ "TARGET_AVX10_V2_AUX"
+ "vcvt<convertbiasps2fp8>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-v2-aux-convert-3.c
b/gcc/testsuite/gcc.target/i386/avx10_2-v2-aux-convert-3.c
new file mode 100644
index 00000000000..a0d2f18ba08
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_2-v2-aux-convert-3.c
@@ -0,0 +1,88 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx10-v2-aux -O2" } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+__m128i test_mm_cvtbiasps_bf8 (__m128i a, __m128 b) { return _mm_cvtbiasps_bf8
(a, b); }
+__m128i test_mm_mask_cvtbiasps_bf8 (__m128i w, __mmask8 u, __m128i a, __m128
b) { return _mm_mask_cvtbiasps_bf8 (w, u, a, b); }
+__m128i test_mm_maskz_cvtbiasps_bf8 (__mmask8 u, __m128i a, __m128 b) { return
_mm_maskz_cvtbiasps_bf8 (u, a, b); }
+
+__m128i test_mm256_cvtbiasps_bf8 (__m256i a, __m256 b) { return
_mm256_cvtbiasps_bf8 (a, b); }
+__m128i test_mm256_mask_cvtbiasps_bf8 (__m128i w, __mmask8 u, __m256i a,
__m256 b) { return _mm256_mask_cvtbiasps_bf8 (w, u, a, b); }
+__m128i test_mm256_maskz_cvtbiasps_bf8 (__mmask8 u, __m256i a, __m256 b) {
return _mm256_maskz_cvtbiasps_bf8 (u, a, b); }
+
+__m128i test_mm512_cvtbiasps_bf8 (__m512i a, __m512 b) { return
_mm512_cvtbiasps_bf8 (a, b); }
+__m128i test_mm512_mask_cvtbiasps_bf8 (__m128i w, __mmask16 u, __m512i a,
__m512 b) { return _mm512_mask_cvtbiasps_bf8 (w, u, a, b); }
+__m128i test_mm512_maskz_cvtbiasps_bf8 (__mmask16 u, __m512i a, __m512 b) {
return _mm512_maskz_cvtbiasps_bf8 (u, a, b); }
+
+__m128i test_mm_cvts_biasps_bf8 (__m128i a, __m128 b) { return
_mm_cvts_biasps_bf8 (a, b); }
+__m128i test_mm_mask_cvts_biasps_bf8 (__m128i w, __mmask8 u, __m128i a, __m128
b) { return _mm_mask_cvts_biasps_bf8 (w, u, a, b); }
+__m128i test_mm_maskz_cvts_biasps_bf8 (__mmask8 u, __m128i a, __m128 b) {
return _mm_maskz_cvts_biasps_bf8 (u, a, b); }
+
+__m128i test_mm256_cvts_biasps_bf8 (__m256i a, __m256 b) { return
_mm256_cvts_biasps_bf8 (a, b); }
+__m128i test_mm256_mask_cvts_biasps_bf8 (__m128i w, __mmask8 u, __m256i a,
__m256 b) { return _mm256_mask_cvts_biasps_bf8 (w, u, a, b); }
+__m128i test_mm256_maskz_cvts_biasps_bf8 (__mmask8 u, __m256i a, __m256 b) {
return _mm256_maskz_cvts_biasps_bf8 (u, a, b); }
+
+__m128i test_mm512_cvts_biasps_bf8 (__m512i a, __m512 b) { return
_mm512_cvts_biasps_bf8 (a, b); }
+__m128i test_mm512_mask_cvts_biasps_bf8 (__m128i w, __mmask16 u, __m512i a,
__m512 b) { return _mm512_mask_cvts_biasps_bf8 (w, u, a, b); }
+__m128i test_mm512_maskz_cvts_biasps_bf8 (__mmask16 u, __m512i a, __m512 b) {
return _mm512_maskz_cvts_biasps_bf8 (u, a, b); }
+
+__m128i test_mm_cvtbiasps_hf8 (__m128i a, __m128 b) { return _mm_cvtbiasps_hf8
(a, b); }
+__m128i test_mm_mask_cvtbiasps_hf8 (__m128i w, __mmask8 u, __m128i a, __m128
b) { return _mm_mask_cvtbiasps_hf8 (w, u, a, b); }
+__m128i test_mm_maskz_cvtbiasps_hf8 (__mmask8 u, __m128i a, __m128 b) { return
_mm_maskz_cvtbiasps_hf8 (u, a, b); }
+
+__m128i test_mm256_cvtbiasps_hf8 (__m256i a, __m256 b) { return
_mm256_cvtbiasps_hf8 (a, b); }
+__m128i test_mm256_mask_cvtbiasps_hf8 (__m128i w, __mmask8 u, __m256i a,
__m256 b) { return _mm256_mask_cvtbiasps_hf8 (w, u, a, b); }
+__m128i test_mm256_maskz_cvtbiasps_hf8 (__mmask8 u, __m256i a, __m256 b) {
return _mm256_maskz_cvtbiasps_hf8 (u, a, b); }
+
+__m128i test_mm512_cvtbiasps_hf8 (__m512i a, __m512 b) { return
_mm512_cvtbiasps_hf8 (a, b); }
+__m128i test_mm512_mask_cvtbiasps_hf8 (__m128i w, __mmask16 u, __m512i a,
__m512 b) { return _mm512_mask_cvtbiasps_hf8 (w, u, a, b); }
+__m128i test_mm512_maskz_cvtbiasps_hf8 (__mmask16 u, __m512i a, __m512 b) {
return _mm512_maskz_cvtbiasps_hf8 (u, a, b); }
+
+__m128i test_mm_cvts_biasps_hf8 (__m128i a, __m128 b) { return
_mm_cvts_biasps_hf8 (a, b); }
+__m128i test_mm_mask_cvts_biasps_hf8 (__m128i w, __mmask8 u, __m128i a, __m128
b) { return _mm_mask_cvts_biasps_hf8 (w, u, a, b); }
+__m128i test_mm_maskz_cvts_biasps_hf8 (__mmask8 u, __m128i a, __m128 b) {
return _mm_maskz_cvts_biasps_hf8 (u, a, b); }
+
+__m128i test_mm256_cvts_biasps_hf8 (__m256i a, __m256 b) { return
_mm256_cvts_biasps_hf8 (a, b); }
+__m128i test_mm256_mask_cvts_biasps_hf8 (__m128i w, __mmask8 u, __m256i a,
__m256 b) { return _mm256_mask_cvts_biasps_hf8 (w, u, a, b); }
+__m128i test_mm256_maskz_cvts_biasps_hf8 (__mmask8 u, __m256i a, __m256 b) {
return _mm256_maskz_cvts_biasps_hf8 (u, a, b); }
+
+__m128i test_mm512_cvts_biasps_hf8 (__m512i a, __m512 b) { return
_mm512_cvts_biasps_hf8 (a, b); }
+__m128i test_mm512_mask_cvts_biasps_hf8 (__m128i w, __mmask16 u, __m512i a,
__m512 b) { return _mm512_mask_cvts_biasps_hf8 (w, u, a, b); }
+__m128i test_mm512_maskz_cvts_biasps_hf8 (__mmask16 u, __m512i a, __m512 b) {
return _mm512_maskz_cvts_biasps_hf8 (u, a, b); }
--
2.34.1
