---
gcc/ChangeLog:
* config.gcc:
* config/i386/immintrin.h:
* doc/sourcebuild.texi:
* config/i386/aceintrin.h: New file.
gcc/testsuite/ChangeLog:
* g++.dg/other/i386-2.C:
* g++.dg/other/i386-3.C:
* gcc.target/i386/tile-1.c: Move to...
* gcc.target/i386/ace-define-1.c: ...here.
* gcc.target/i386/tile-2.c: Move to...
* gcc.target/i386/ace-define-2.c: ...here.
* lib/target-supports.exp:
* gcc.target/i386/ace-asmatt-1.c: New test.
* gcc.target/i386/ace-asmintel-1.c: New test.
* gcc.target/i386/ace-funcspec-1.c: New test.
gcc/config.gcc | 2 +-
gcc/config/i386/aceintrin.h | 151 ++++++++++++++++++
gcc/config/i386/immintrin.h | 2 +
gcc/doc/sourcebuild.texi | 3 +
gcc/testsuite/g++.dg/other/i386-2.C | 4 +-
gcc/testsuite/g++.dg/other/i386-3.C | 4 +-
gcc/testsuite/gcc.target/i386/ace-asmatt-1.c | 58 +++++++
.../gcc.target/i386/ace-asmintel-1.c | 58 +++++++
.../i386/{tile-1.c => ace-define-1.c} | 0
.../i386/{tile-2.c => ace-define-2.c} | 4 -
.../gcc.target/i386/ace-funcspec-1.c | 14 ++
gcc/testsuite/lib/target-supports.exp | 12 ++
12 files changed, 303 insertions(+), 9 deletions(-)
create mode 100644 gcc/config/i386/aceintrin.h
create mode 100644 gcc/testsuite/gcc.target/i386/ace-asmatt-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/ace-asmintel-1.c
rename gcc/testsuite/gcc.target/i386/{tile-1.c => ace-define-1.c} (100%)
rename gcc/testsuite/gcc.target/i386/{tile-2.c => ace-define-2.c} (80%)
create mode 100644 gcc/testsuite/gcc.target/i386/ace-funcspec-1.c
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 8fc0b37c0f9..afa4c600e4d 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -472,7 +472,7 @@ i[34567]86-*-* | x86_64-*-*)
avx10_2minmaxintrin.h avx10_2copyintrin.h
amxavx512intrin.h amxtf32intrin.h amxfp8intrin.h
movrsintrin.h amxmovrsintrin.h avx512bmmintrin.h
- avx512bmmvlintrin.h avx10_v2_auxintrin.h tileintrin.h"
+ avx512bmmvlintrin.h avx10_v2_auxintrin.h tileintrin.h
aceintrin.h"
;;
ia64-*-*)
extra_headers=ia64intrin.h
diff --git a/gcc/config/i386/aceintrin.h b/gcc/config/i386/aceintrin.h
new file mode 100644
index 00000000000..b9292520ba7
--- /dev/null
+++ b/gcc/config/i386/aceintrin.h
@@ -0,0 +1,151 @@
+/* Copyright (C) 2020-2025 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GCC is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#if !defined _IMMINTRIN_H_INCLUDED
+#error "Never use <aceintrin.h> directly; include <immintrin.h> instead."
+#endif
+
+#ifndef _ACEINTRIN_H_INCLUDED
+#define _ACEINTRIN_H_INCLUDED
+
+#if !defined(__ACE_V1__)
+#pragma GCC push_options
+#pragma GCC target("ace-v1")
+#define __DISABLE_ACE_V1__
+#endif /* __ACE_V1__ */
+
+#if defined(__x86_64__)
+
+#define _tile_setrowi(dst, src1, imm8) \
+ __asm__ volatile \
+ ("{tilemovrow\t%1, %0, %%tmm"#dst"|tilemovrow\ttmm"#dst", %0, %1}" \
+ :: "v" (src1), "i" (imm8))
+
+#define _tile_setrow(dst, src1, r32) \
+ __asm__ volatile \
+ ("{tilemovrow\t%1, %0, %%tmm"#dst"|tilemovrow\ttmm"#dst", %0, %1}" \
+ :: "v" (src1), "r" (r32))
+
+#define _tile_setcoli(dst, src1, imm8) \
+ __asm__ volatile \
+ ("{tilemovcol\t%1, %0, %%tmm"#dst"|tilemovcol\ttmm"#dst", %0, %1}" \
+ :: "v" (src1), "i" (imm8))
+
+#define _tile_setcol(dst, src1, r32) \
+ __asm__ volatile \
+ ("{tilemovcol\t%1, %0, %%tmm"#dst"|tilemovcol\ttmm"#dst", %0, %1}" \
+ :: "v" (src1), "r" (r32))
+
+#define _bsr_movf(src1, src2) \
+ __asm__ volatile \
+ ("{bsrmovf\t%1, %0, %%bsr0|bsrmovf\tbsr0, %0, %1}" \
+ :: "v" (src1), "v" (src2))
+
+#define _bsr_movh_set(src) \
+ __asm__ volatile \
+ ("{bsrmovh\t%0, %%bsr0|bsrmovh\tbsr0, %0}" \
+ :: "v" (src))
+
+#define _bsr_movl_set(src) \
+ __asm__ volatile \
+ ("{bsrmovl\t%0, %%bsr0|bsrmovl\tbsr0, %0}" \
+ :: "v" (src))
+
+#define _bsr_movh_get() \
+({ __m512i dst; \
+ __asm__ volatile \
+ ("{bsrmovh\t%%bsr0, %0|bsrmovh\t%0, bsr0}" \
+ : "=v" (dst)); \
+ dst; \
+})
+
+#define _bsr_movl_get() \
+({ __m512i dst; \
+ __asm__ volatile \
+ ("{bsrmovl\t%%bsr0, %0|bsrmovl\t%0, bsr0}" \
+ : "=v" (dst)); \
+ dst; \
+})
+
+#define _bsr_init \
+ __asm__ volatile \
+ ("{bsrinit\t%%bsr0|bsrinit\tbsr0}" ::)
+
+#define _tile_top2bf16ps(dst, src1, src2) \
+ __asm__ volatile \
+ ("{top2bf16ps\t%1, %0, %%tmm"#dst"|top2bf16ps\ttmm"#dst", %0, %1}" \
+ :: "v" (src1), "v" (src2))
+
+#define _tile_top4bssd(dst, src1, src2) \
+ __asm__ volatile \
+ ("{top4bssd\t%1, %0, %%tmm"#dst"|top4bssd\ttmm"#dst", %0, %1}" \
+ :: "v" (src1), "v" (src2))
+
+#define _tile_top4busd(dst, src1, src2) \
+ __asm__ volatile \
+ ("{top4busd\t%1, %0, %%tmm"#dst"|top4busd\ttmm"#dst", %0, %1}" \
+ :: "v" (src1), "v" (src2))
+
+#define _tile_top4bsud(dst, src1, src2) \
+ __asm__ volatile \
+ ("{top4bsud\t%1, %0, %%tmm"#dst"|top4bsud\ttmm"#dst", %0, %1}" \
+ :: "v" (src1), "v" (src2))
+
+#define _tile_top4buud(dst, src1, src2) \
+ __asm__ volatile \
+ ("{top4buud\t%1, %0, %%tmm"#dst"|top4buud\ttmm"#dst", %0, %1}" \
+ :: "v" (src1), "v" (src2))
+
+#define _tile_top4mxbf8ps(dst, src1, src2, imm8) \
+ __asm__ volatile \
+ ("{top4mxbf8ps\t%2, %1, %0, %%tmm"#dst"|top4mxbf8ps\ttmm"#dst", %0, %1, %2}"
\
+ :: "v" (src1), "v" (src2), "i" (imm8))
+
+#define _tile_top4mxbhf8ps(dst, src1, src2, imm8) \
+ __asm__ volatile \
+ ("{top4mxbhf8ps\t%2, %1, %0, %%tmm"#dst"|top4mxbhf8ps\ttmm"#dst", %0, %1,
%2}" \
+ :: "v" (src1), "v" (src2), "i" (imm8))
+
+#define _tile_top4mxhf8ps(dst, src1, src2, imm8) \
+ __asm__ volatile \
+ ("{top4mxhf8ps\t%2, %1, %0, %%tmm"#dst"|top4mxhf8ps\ttmm"#dst", %0, %1, %2}"
\
+ :: "v" (src1), "v" (src2), "i" (imm8))
+
+#define _tile_top4mxhbf8ps(dst, src1, src2, imm8) \
+ __asm__ volatile \
+ ("{top4mxhbf8ps\t%2, %1, %0, %%tmm"#dst"|top4mxhbf8ps\ttmm"#dst", %0, %1,
%2}" \
+ :: "v" (src1), "v" (src2), "i" (imm8))
+
+#define _tile_top4mxbssps(dst, src1, src2, imm8) \
+ __asm__ volatile \
+ ("{top4mxbssps\t%2, %1, %0, %%tmm"#dst"|top4mxbssps\ttmm"#dst", %0, %1, %2}"
\
+ :: "v" (src1), "v" (src2), "i" (imm8))
+
+#endif
+
+#ifdef __DISABLE_ACE_V1__
+#undef __DISABLE_ACE_V1__
+#pragma GCC pop_options
+#endif /* __DISABLE_ACE_V1__ */
+
+#endif /* _ACEINTRIN_H_INCLUDED */
diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h
index 18afee336e7..c06fe49287c 100644
--- a/gcc/config/i386/immintrin.h
+++ b/gcc/config/i386/immintrin.h
@@ -167,4 +167,6 @@
#include <avx512bmmintrin.h>
#include <avx512bmmvlintrin.h>
+
+#include <aceintrin.h>
#endif /* _IMMINTRIN_H_INCLUDED */
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 7850b9de934..21b9ef5dbe1 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2731,6 +2731,9 @@ Target supports the execution of @code{amx-fp16}
instructions.
@item amx_movrs
Target supports the execution of @code{amx-movrs} instructions.
+@item ace-v1
+Target supports the execution of @code{ace-v1} instructions.
+
@item amx_tf32
Target supports the execution of @code{amx-tf32} instructions.
diff --git a/gcc/testsuite/g++.dg/other/i386-2.C
b/gcc/testsuite/g++.dg/other/i386-2.C
index 89b9420397a..ee25673c219 100644
--- a/gcc/testsuite/g++.dg/other/i386-2.C
+++ b/gcc/testsuite/g++.dg/other/i386-2.C
@@ -1,5 +1,5 @@
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2
-mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp
-mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt
-msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku -msgx
-mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize
-mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma
-mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint
-mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2 -mamx-avx512
-mamx-tf32 -mamx-fp8 -mmovrs -mamx-movrs" } */
+/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2
-mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp
-mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt
-msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku -msgx
-mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize
-mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma
-mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint
-mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2 -mamx-avx512
-mamx-tf32 -mamx-fp8 -mmovrs -mamx-movrs -mace-v1" } */
/* { dg-skip-if "requires hosted libstdc++ for cstdlib malloc" { ! hostedlib }
} */
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
@@ -7,7 +7,7 @@
popcntintrin.h, fmaintrin.h, pkuintrin.h, avx512vpopcntdqintrin.h,
gfniintrin.h, avx512bitalgintrin.h, avx512vp2intersectintrin.h,
tsxldtrkintrin.h, tileintrin.h, amxtileintrin.h, amxint8intrin.h,
amxbf16intrin.h,
- avx512vp2intersectvlintrin.h and mm_malloc.h.h are usable
+ avx512vp2intersectvlintrin.h, aceintrin.h and mm_malloc.h.h are usable
with -O -pedantic-errors. */
#include <x86intrin.h>
diff --git a/gcc/testsuite/g++.dg/other/i386-3.C
b/gcc/testsuite/g++.dg/other/i386-3.C
index 6c25b028029..8f40e2f8fc1 100644
--- a/gcc/testsuite/g++.dg/other/i386-3.C
+++ b/gcc/testsuite/g++.dg/other/i386-3.C
@@ -1,5 +1,5 @@
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx
-mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm
-mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr
-mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku
-msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect
-mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni
-mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi
-mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2
-mamx-avx512 -mamx-tf32 -mamx-fp8 -mmovrs -mamx-movrs" } */
+/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx
-mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm
-mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr
-mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku
-msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect
-mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni
-mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi
-mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2
-mamx-avx512 -mamx-tf32 -mamx-fp8 -mmovrs -mamx-movrs -mace-v1" } */
/* { dg-skip-if "requires hosted libstdc++ for cstdlib malloc" { ! hostedlib }
} */
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
@@ -7,7 +7,7 @@
popcntintrin.h, fmaintrin.h, pkuintrin.h, avx512vpopcntdqintrin.h,
gfniintrin.h, avx512bitalgintrin.h, avx512vp2intersectintrin.h,
tsxldtrkintrin.h, tileintrin.h, amxtileintrin.h, amxint8intrin.h,
amxbf16intrin.h,
- avx512vp2intersectvlintrin.h and mm_malloc.h are usable
+ avx512vp2intersectvlintrin.h, aceintrin.h and mm_malloc.h are usable
with -O -fkeep-inline-functions. */
#include <x86intrin.h>
diff --git a/gcc/testsuite/gcc.target/i386/ace-asmatt-1.c
b/gcc/testsuite/gcc.target/i386/ace-asmatt-1.c
new file mode 100644
index 00000000000..7311b212fd5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/ace-asmatt-1.c
@@ -0,0 +1,58 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mace-v1" } */
+/* { dg-final { scan-assembler "ldtilecfg\[ \\t]+" } } */
+/* { dg-final { scan-assembler "sttilecfg\[ \\t]+" } } */
+/* { dg-final { scan-assembler "tilerelease" } } */
+/* { dg-final { scan-assembler "tilezero\[ \\t]+\[^\n\]*%tmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "tilemovrow\[ \\t]+\[^\n\]*%tmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "tilemovcol\[ \\t]+\[^\n\]*%tmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "bsrinit\[ \\t]+\[^\n\]*%bsr0" } } */
+/* { dg-final { scan-assembler "bsrmovf\[ \\t]+\[^\n\]*%bsr0" } } */
+/* { dg-final { scan-assembler "bsrmovh\[ \\t]+\[^\n\]*%bsr0" } } */
+/* { dg-final { scan-assembler "bsrmovl\[ \\t]+\[^\n\]*%bsr0" } } */
+/* { dg-final { scan-assembler "top2bf16ps\[ \\t]+\[^\n\]*%tmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "top4bssd\[ \\t]+\[^\n\]*%tmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "top4busd\[ \\t]+\[^\n\]*%tmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "top4bsud\[ \\t]+\[^\n\]*%tmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "top4buud\[ \\t]+\[^\n\]*%tmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "top4mxbf8ps\[ \\t]+\[^\n\]*%tmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "top4mxbhf8ps\[ \\t]+\[^\n\]*%tmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "top4mxhf8ps\[ \\t]+\[^\n\]*%tmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "top4mxhbf8ps\[ \\t]+\[^\n\]*%tmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "top4mxbssps\[ \\t]+\[^\n\]*%tmm\[0-9\]" } } */
+#include <immintrin.h>
+
+void test_ace_data (void)
+{
+ __m512bh b = (__m512bh) _mm512_setzero_si512 ();
+ __m512i i = _mm512_setzero_si512 ();
+ char cfg[64];
+ __m512 z = _mm512_setzero_ps ();
+ __m512i zi = _mm512_setzero_si512 ();
+ int index = 1;
+
+ _tile_loadconfig (cfg);
+ _tile_storeconfig (cfg);
+ _tile_release ();
+ _tile_zero (0);
+ _tile_setrowi (0, z, 0);
+ _tile_setrow (0, z, index);
+ _tile_setcoli (1, z, 0);
+ _tile_setcol (1, z, index);
+ _bsr_init;
+ _bsr_movf (zi, zi);
+ _bsr_movh_set (zi);
+ _bsr_movl_set (zi);
+ (void) _bsr_movh_get ();
+ (void) _bsr_movl_get ();
+ _tile_top2bf16ps (0, b, b);
+ _tile_top4bssd (1, i, i);
+ _tile_top4busd (2, i, i);
+ _tile_top4bsud (3, i, i);
+ _tile_top4buud (4, i, i);
+ _tile_top4mxbf8ps (5, i, i, 0);
+ _tile_top4mxbhf8ps (6, i, i, 0);
+ _tile_top4mxhf8ps (7, i, i, 0);
+ _tile_top4mxhbf8ps (0, i, i, 0);
+ _tile_top4mxbssps (1, i, i, 0);
+}
diff --git a/gcc/testsuite/gcc.target/i386/ace-asmintel-1.c
b/gcc/testsuite/gcc.target/i386/ace-asmintel-1.c
new file mode 100644
index 00000000000..4ef3cb2d42a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/ace-asmintel-1.c
@@ -0,0 +1,58 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-require-effective-target masm_intel } */
+/* { dg-options "-O2 -mace-v1 -masm=intel" } */
+/* { dg-final { scan-assembler "ldtilecfg\[ \\t]" } } */
+/* { dg-final { scan-assembler "sttilecfg\[ \\t]" } } */
+/* { dg-final { scan-assembler "tilerelease" } } */
+/* { dg-final { scan-assembler "tilezero\[ \\t]+\[^\n%\]*tmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "tilemovrow\[ \\t]+\[^\n%\]*tmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "tilemovcol\[ \\t]+\[^\n%\]*tmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "bsrinit\[ \\t]+\[^\n%\]*bsr0" } } */
+/* { dg-final { scan-assembler "bsrmovf\[ \\t]+\[^\n%\]*bsr0" } } */
+/* { dg-final { scan-assembler "bsrmovh\[ \\t]+\[^\n%\]*bsr0" } } */
+/* { dg-final { scan-assembler "bsrmovl\[ \\t]+\[^\n%\]*bsr0" } } */
+/* { dg-final { scan-assembler "top2bf16ps\[ \\t]+\[^\n%\]*tmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "top4bssd\[ \\t]+\[^\n%\]*tmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "top4busd\[ \\t]+\[^\n%\]*tmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "top4bsud\[ \\t]+\[^\n%\]*tmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "top4buud\[ \\t]+\[^\n%\]*tmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "top4mxbf8ps\[ \\t]+\[^\n%\]*tmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "top4mxbhf8ps\[ \\t]+\[^\n%\]*tmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "top4mxhf8ps\[ \\t]+\[^\n%\]*tmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "top4mxhbf8ps\[ \\t]+\[^\n%\]*tmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "top4mxbssps\[ \\t]+\[^\n%\]*tmm\[0-9\]" } } */
+#include <immintrin.h>
+
+void test_ace_data (void)
+{
+ __m512bh b = (__m512bh) _mm512_setzero_si512 ();
+ __m512i i = _mm512_setzero_si512 ();
+ char cfg[64];
+ __m512 z = _mm512_setzero_ps ();
+ __m512i zi = _mm512_setzero_si512 ();
+ int index = 1;
+ _tile_loadconfig (cfg);
+ _tile_storeconfig (cfg);
+ _tile_release ();
+ _tile_zero (0);
+ _tile_setrowi (0, z, 0);
+ _tile_setrow (0, z, index);
+ _tile_setcoli (1, z, 0);
+ _tile_setcol (1, z, index);
+ _bsr_init;
+ _bsr_movf (zi, zi);
+ _bsr_movh_set (zi);
+ _bsr_movl_set (zi);
+ zi = _bsr_movh_get ();
+ zi = _bsr_movl_get ();
+ _tile_top2bf16ps (0, b, b);
+ _tile_top4bssd (1, i, i);
+ _tile_top4busd (2, i, i);
+ _tile_top4bsud (3, i, i);
+ _tile_top4buud (4, i, i);
+ _tile_top4mxbf8ps (5, i, i, 0);
+ _tile_top4mxbhf8ps (6, i, i, 0);
+ _tile_top4mxhf8ps (7, i, i, 0);
+ _tile_top4mxhbf8ps (0, i, i, 0);
+ _tile_top4mxbssps (1, i, i, 0);
+}
diff --git a/gcc/testsuite/gcc.target/i386/tile-1.c
b/gcc/testsuite/gcc.target/i386/ace-define-1.c
similarity index 100%
rename from gcc/testsuite/gcc.target/i386/tile-1.c
rename to gcc/testsuite/gcc.target/i386/ace-define-1.c
diff --git a/gcc/testsuite/gcc.target/i386/tile-2.c
b/gcc/testsuite/gcc.target/i386/ace-define-2.c
similarity index 80%
rename from gcc/testsuite/gcc.target/i386/tile-2.c
rename to gcc/testsuite/gcc.target/i386/ace-define-2.c
index b6d8773b81a..99a1d92b26b 100644
--- a/gcc/testsuite/gcc.target/i386/tile-2.c
+++ b/gcc/testsuite/gcc.target/i386/ace-define-2.c
@@ -2,10 +2,6 @@
/* { dg-do compile { target { ! ia32 } } } */
/* { dg-options "-mtile -mno-ace-v1" } */
-#ifndef __TILE__
-#error "-mtile should define __TILE__"
-#endif
-
#ifdef __ACE_V1__
#error "-mtile must not imply -mace-v1; __ACE_V1__ should not be defined"
#endif
diff --git a/gcc/testsuite/gcc.target/i386/ace-funcspec-1.c
b/gcc/testsuite/gcc.target/i386/ace-funcspec-1.c
new file mode 100644
index 00000000000..a61699d6a71
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/ace-funcspec-1.c
@@ -0,0 +1,14 @@
+/* Test that target attributes ace are accepted
+ and that functions with these attributes can be called. */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2" } */
+
+void test_ace (void) __attribute__ ((target ("ace-v1")));
+
+void test_ace (void) {}
+
+int main (void)
+{
+ test_ace ();
+ return 0;
+}
\ No newline at end of file
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index c32387cea3e..39781dcf7db 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -11580,6 +11580,18 @@ proc check_effective_target_amx_movrs { } {
} "-mamx-movrs" ]
}
+# Return 1 if ace instructions can be compiled.
+proc check_effective_target_ace_tile { } {
+ return [check_no_compiler_messages ace object {
+ void
+ foo ()
+ {
+ __asm__ volatile ("bsrinit\t%%bsr0" ::);
+ __asm__ volatile ("top2bf16ps\t%%tmm0, %%zmm1, %%zmm2" ::);
+ }
+ } "-mace-v1" ]
+}
+
# Return 1 if sse instructions can be compiled.
proc check_effective_target_sse { } {
return [check_no_compiler_messages sse object {
--
2.34.1
