---
gcc/ChangeLog:
* config/i386/avx10_v2_auxintrin.h (__attribute__):
(_mm_cvtbf8_bf4s):
(_mm256_cvtbf8_bf4s):
(_mm512_cvtbf8_bf4s):
(_mm_cvthf8_bf4s):
(_mm256_cvthf8_bf4s):
(_mm512_cvthf8_bf4s):
(_mm_cvtbf4_hf8):
(_mm_mask_cvtbf4_hf8):
(_mm_maskz_cvtbf4_hf8):
(_mm256_cvtbf4_hf8):
(_mm256_mask_cvtbf4_hf8):
(_mm256_maskz_cvtbf4_hf8):
(_mm512_cvtbf4_hf8):
(_mm512_mask_cvtbf4_hf8):
(_mm512_maskz_cvtbf4_hf8):
* config/i386/i386-builtin-types.def (V16QI):
(V32QI):
(V64QI):
* config/i386/i386-builtin.def (BDESC):
* config/i386/i386-expand.cc (ix86_expand_args_builtin):
* config/i386/sse.md (vcvt<convertfp82bf4>v16qi):
(vcvt<convertfp82bf4>v32qi):
(vcvt<convertfp82bf4>v64qi):
(vcvtbf42hf8<mode>):
(vcvtbf42hf8<mode>_mask):
(*vcvtbf42hf8<mode>_mask):
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx10_2-v2-aux-convert-5.c: New test.
* gcc.target/i386/avx10_2-v2-aux-convert-6.c: New test.
gcc/config/i386/avx10_v2_auxintrin.h | 124 ++++++++++++++++++
gcc/config/i386/i386-builtin-types.def | 3 +
gcc/config/i386/i386-builtin.def | 9 ++
gcc/config/i386/i386-expand.cc | 3 +
gcc/config/i386/sse.md | 87 ++++++++++++
.../i386/avx10_2-v2-aux-convert-5.c | 18 +++
.../i386/avx10_2-v2-aux-convert-6.c | 25 ++++
7 files changed, 269 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-v2-aux-convert-5.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_2-v2-aux-convert-6.c
diff --git a/gcc/config/i386/avx10_v2_auxintrin.h
b/gcc/config/i386/avx10_v2_auxintrin.h
index f63f835f08f..0570fe9a738 100644
--- a/gcc/config/i386/avx10_v2_auxintrin.h
+++ b/gcc/config/i386/avx10_v2_auxintrin.h
@@ -1147,6 +1147,130 @@ _mm512_maskz_cvthf8_ps(__mmask16 __U, __m128i __A)
(__mmask16) __U);
}
+// VCVTBF82BF4S
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtbf8_bf4s (__m128i __A)
+{
+ return (__m128i) __builtin_ia32_vcvtbf82bf4s128 ((__v16qi) __A);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvtbf8_bf4s (__m256i __A)
+{
+ return (__m128i) __builtin_ia32_vcvtbf82bf4s256 ((__v32qi) __A);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvtbf8_bf4s (__m512i __A)
+{
+ return (__m256i) __builtin_ia32_vcvtbf82bf4s512 ((__v64qi) __A);
+}
+
+// VCVTHF82BF4S
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvthf8_bf4s (__m128i __A)
+{
+ return (__m128i) __builtin_ia32_vcvthf82bf4s128 ((__v16qi) __A);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvthf8_bf4s (__m256i __A)
+{
+ return (__m128i) __builtin_ia32_vcvthf82bf4s256 ((__v32qi) __A);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvthf8_bf4s (__m512i __A)
+{
+ return (__m256i) __builtin_ia32_vcvthf82bf4s512 ((__v64qi) __A);
+}
+
+// VCVTBF42HF8 - 128-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtbf4_hf8(__m128i __A) {
+ return (__m128i) __builtin_ia32_vcvtbf42hf8128_mask((__v16qi)__A,
+ (__v16qi) _mm_undefined_si128
(),
+ (__mmask16) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_cvtbf4_hf8(__m128i __W, __mmask16 __U, __m128i __A) {
+ return (__m128i) __builtin_ia32_vcvtbf42hf8128_mask((__v16qi)__A,
+ (__v16qi) __W,
+ (__mmask16) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_cvtbf4_hf8(__mmask16 __U, __m128i __A) {
+ return (__m128i) __builtin_ia32_vcvtbf42hf8128_mask((__v16qi)__A,
+ (__v16qi) _mm_setzero_si128 (),
+ (__mmask16) __U);
+}
+
+// VCVTBF42HF8 - 256-bit
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvtbf4_hf8(__m128i __A) {
+ return (__m256i) __builtin_ia32_vcvtbf42hf8256_mask((__v16qi)__A,
+ (__v32qi)
_mm256_undefined_si256 (),
+ (__mmask32) -1);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvtbf4_hf8(__m256i __W, __mmask32 __U, __m128i __A) {
+ return (__m256i) __builtin_ia32_vcvtbf42hf8256_mask((__v16qi)__A,
+ (__v32qi) __W,
+ (__mmask32) __U);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvtbf4_hf8(__mmask32 __U, __m128i __A) {
+ return (__m256i) __builtin_ia32_vcvtbf42hf8256_mask((__v16qi)__A,
+ (__v32qi) _mm256_setzero_si256
(),
+ (__mmask32) __U);
+}
+
+// VCVTBF42HF8 - 512-bit
+
+extern __inline __m512i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvtbf4_hf8(__m256i __A) {
+ return (__m512i) __builtin_ia32_vcvtbf42hf8512_mask((__v32qi)__A,
+ (__v64qi)
_mm512_undefined_epi32 (),
+ (__mmask64) -1);
+}
+
+extern __inline __m512i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_cvtbf4_hf8(__m512i __W, __mmask64 __U, __m256i __A) {
+ return (__m512i) __builtin_ia32_vcvtbf42hf8512_mask((__v32qi)__A,
+ (__v64qi) __W,
+ (__mmask64) __U);
+}
+
+extern __inline __m512i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_cvtbf4_hf8(__mmask64 __U, __m256i __A) {
+ return (__m512i) __builtin_ia32_vcvtbf42hf8512_mask((__v32qi)__A,
+ (__v64qi) _mm512_setzero_si512
(),
+ (__mmask64) __U);
+}
+
#ifdef __DISABLE_AVX10_V2_AUX__
#undef __DISABLE_AVX10_V2_AUX__
#pragma GCC pop_options
diff --git a/gcc/config/i386/i386-builtin-types.def
b/gcc/config/i386/i386-builtin-types.def
index a23b0fed1dd..2622afdf49a 100644
--- a/gcc/config/i386/i386-builtin-types.def
+++ b/gcc/config/i386/i386-builtin-types.def
@@ -1475,12 +1475,15 @@ DEF_FUNCTION_TYPE (V8DI, V8DF, V8DI, UQI)
DEF_FUNCTION_TYPE (V8SI, V8DF, V8SI, UQI)
# AVX10_V2_AUX builtins
+DEF_FUNCTION_TYPE (V16QI, V32QI)
+DEF_FUNCTION_TYPE (V32QI, V64QI)
DEF_FUNCTION_TYPE (V4SF, V16QI, V4SF, UQI)
DEF_FUNCTION_TYPE (V8SF, V16QI, V8SF, UQI)
DEF_FUNCTION_TYPE (V16SF, V16QI, V16SF, UHI)
DEF_FUNCTION_TYPE (V16QI, V4SF, V16QI, UQI)
DEF_FUNCTION_TYPE (V16QI, V8SF, V16QI, UQI)
DEF_FUNCTION_TYPE (V16QI, V16SF, V16QI, UHI)
+DEF_FUNCTION_TYPE (V64QI, V32QI, V64QI, UDI)
DEF_FUNCTION_TYPE (V16QI, V16QI, V4SF, V16QI, UQI)
DEF_FUNCTION_TYPE (V16QI, V32QI, V8SF, V16QI, UQI)
DEF_FUNCTION_TYPE (V16QI, V64QI, V16SF, V16QI, UHI)
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index f89252a3f1e..1f50fde62e0 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -3406,6 +3406,15 @@ BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX,
CODE_FOR_vcvtbf82psv16sf_mask, "__built
BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvthf82psv4sf_mask,
"__builtin_ia32_vcvthf82ps128_mask", IX86_BUILTIN_VCVTHF82PS128_MASK, UNKNOWN,
(int) V4SF_FTYPE_V16QI_V4SF_UQI)
BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvthf82psv8sf_mask,
"__builtin_ia32_vcvthf82ps256_mask", IX86_BUILTIN_VCVTHF82PS256_MASK, UNKNOWN,
(int) V8SF_FTYPE_V16QI_V8SF_UQI)
BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvthf82psv16sf_mask,
"__builtin_ia32_vcvthf82ps512_mask", IX86_BUILTIN_VCVTHF82PS512_MASK, UNKNOWN,
(int) V16SF_FTYPE_V16QI_V16SF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvtbf82bf4sv16qi,
"__builtin_ia32_vcvtbf82bf4s128", IX86_BUILTIN_VCVTBF82BF4S128, UNKNOWN, (int)
V16QI_FTYPE_V16QI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvtbf82bf4sv32qi,
"__builtin_ia32_vcvtbf82bf4s256", IX86_BUILTIN_VCVTBF82BF4S256, UNKNOWN, (int)
V16QI_FTYPE_V32QI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvtbf82bf4sv64qi,
"__builtin_ia32_vcvtbf82bf4s512", IX86_BUILTIN_VCVTBF82BF4S512, UNKNOWN, (int)
V32QI_FTYPE_V64QI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvthf82bf4sv16qi,
"__builtin_ia32_vcvthf82bf4s128", IX86_BUILTIN_VCVTHF82BF4S128, UNKNOWN, (int)
V16QI_FTYPE_V16QI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvthf82bf4sv32qi,
"__builtin_ia32_vcvthf82bf4s256", IX86_BUILTIN_VCVTHF82BF4S256, UNKNOWN, (int)
V16QI_FTYPE_V32QI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvthf82bf4sv64qi,
"__builtin_ia32_vcvthf82bf4s512", IX86_BUILTIN_VCVTHF82BF4S512, UNKNOWN, (int)
V32QI_FTYPE_V64QI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvtbf42hf8v16qi_mask,
"__builtin_ia32_vcvtbf42hf8128_mask", IX86_BUILTIN_VCVTBF42HF8128_MASK,
UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvtbf42hf8v32qi_mask,
"__builtin_ia32_vcvtbf42hf8256_mask", IX86_BUILTIN_VCVTBF42HF8256_MASK,
UNKNOWN, (int) V32QI_FTYPE_V16QI_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_V2_AUX, CODE_FOR_vcvtbf42hf8v64qi_mask,
"__builtin_ia32_vcvtbf42hf8512_mask", IX86_BUILTIN_VCVTBF42HF8512_MASK,
UNKNOWN, (int) V64QI_FTYPE_V32QI_V64QI_UDI)
/* Builtins with rounding support. */
BDESC_END (ARGS, ROUND_ARGS)
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index f40ac2780b2..c56fc8e8d34 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -12524,6 +12524,8 @@ ix86_expand_args_builtin (const struct
builtin_description *d,
case V16BF_FTYPE_V16SF:
case V8BF_FTYPE_V8SF:
case V8BF_FTYPE_V4SF:
+ case V16QI_FTYPE_V32QI:
+ case V32QI_FTYPE_V64QI:
nargs = 1;
break;
case V4SF_FTYPE_V4SF_VEC_MERGE:
@@ -12904,6 +12906,7 @@ ix86_expand_args_builtin (const struct
builtin_description *d,
case V4SF_FTYPE_V16QI_V4SF_UQI:
case V8SF_FTYPE_V16QI_V8SF_UQI:
case V16SF_FTYPE_V16QI_V16SF_UHI:
+ case V64QI_FTYPE_V32QI_V64QI_UDI:
nargs = 3;
break;
case V32QI_FTYPE_V32QI_V32QI_INT:
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 358ac449c8b..0e3bcc8db37 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -272,6 +272,9 @@
UNSPEC_VCVTBIASPS2HF8S
UNSPEC_VCVTBF82PS
UNSPEC_VCVTHF82PS
+ UNSPEC_VCVTBF82BF4S
+ UNSPEC_VCVTHF82BF4S
+ UNSPEC_VCVTBF42HF8
])
(define_c_enum "unspecv" [
@@ -33977,3 +33980,87 @@
"vcvt<convertfp82ps>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
[(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
+
+;; FP8 to FP4 converts (VCVTBF82BF4S, VCVTHF82BF4S) - no masking
+
+(define_int_iterator UNSPEC_CONVERTFP82BF4
+ [UNSPEC_VCVTBF82BF4S UNSPEC_VCVTHF82BF4S])
+
+(define_int_attr convertfp82bf4
+ [(UNSPEC_VCVTBF82BF4S "bf82bf4s")
+ (UNSPEC_VCVTHF82BF4S "hf82bf4s")])
+
+(define_insn "vcvt<convertfp82bf4>v16qi"
+ [(set (match_operand:V16QI 0 "register_operand" "=v")
+ (unspec:V16QI
+ [(match_operand:V16QI 1 "register_operand" "v")]
+ UNSPEC_CONVERTFP82BF4))]
+ "TARGET_AVX10_V2_AUX"
+ "vcvt<convertfp82bf4>\t{%1, %0|%0, %1}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "TI")])
+
+(define_insn "vcvt<convertfp82bf4>v32qi"
+ [(set (match_operand:V16QI 0 "register_operand" "=v")
+ (unspec:V16QI
+ [(match_operand:V32QI 1 "register_operand" "v")]
+ UNSPEC_CONVERTFP82BF4))]
+ "TARGET_AVX10_V2_AUX"
+ "vcvt<convertfp82bf4>\t{%1, %0|%0, %1}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "OI")])
+
+(define_insn "vcvt<convertfp82bf4>v64qi"
+ [(set (match_operand:V32QI 0 "register_operand" "=v")
+ (unspec:V32QI
+ [(match_operand:V64QI 1 "register_operand" "v")]
+ UNSPEC_CONVERTFP82BF4))]
+ "TARGET_AVX10_V2_AUX"
+ "vcvt<convertfp82bf4>\t{%1, %0|%0, %1}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "XI")])
+
+;; FP4 to FP8 converts (VCVTBF42HF8) with masking
+
+(define_mode_attr bf42hf8_srcmode
+ [(V16QI "V16QI") (V32QI "V16QI") (V64QI "V32QI")])
+
+(define_insn "vcvtbf42hf8<mode>"
+ [(set (match_operand:VI1_AVX512VL 0 "register_operand" "=v")
+ (unspec:VI1_AVX512VL
+ [(match_operand:<bf42hf8_srcmode> 1 "nonimmediate_operand" "vm")]
+ UNSPEC_VCVTBF42HF8))]
+ "TARGET_AVX10_V2_AUX"
+ "vcvtbf42hf8\t{%1, %0|%0, %1}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
+
+(define_expand "vcvtbf42hf8<mode>_mask"
+ [(set (match_operand:VI1_AVX512VL 0 "register_operand")
+ (vec_merge:VI1_AVX512VL
+ (unspec:VI1_AVX512VL
+ [(match_operand:<bf42hf8_srcmode> 1 "nonimmediate_operand")]
+ UNSPEC_VCVTBF42HF8)
+ (match_operand:VI1_AVX512VL 2 "nonimm_or_0_operand")
+ (match_operand:<avx512fmaskmode> 3 "register_or_constm1_operand")))]
+ "TARGET_AVX10_V2_AUX"
+{
+ if (CONST_INT_P (operands[3]))
+ {
+ emit_insn (gen_vcvtbf42hf8<mode> (operands[0], operands[1]));
+ DONE;
+ }
+})
+
+(define_insn "*vcvtbf42hf8<mode>_mask"
+ [(set (match_operand:VI1_AVX512VL 0 "register_operand" "=v")
+ (vec_merge:VI1_AVX512VL
+ (unspec:VI1_AVX512VL
+ [(match_operand:<bf42hf8_srcmode> 1 "nonimmediate_operand" "vm")]
+ UNSPEC_VCVTBF42HF8)
+ (match_operand:VI1_AVX512VL 2 "nonimm_or_0_operand" "0C")
+ (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))]
+ "TARGET_AVX10_V2_AUX"
+ "vcvtbf42hf8\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-v2-aux-convert-5.c
b/gcc/testsuite/gcc.target/i386/avx10_2-v2-aux-convert-5.c
new file mode 100644
index 00000000000..4f4ebcfe449
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_2-v2-aux-convert-5.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx10-v2-aux -O2" } */
+/* { dg-final { scan-assembler-times "vcvtbf82bf4s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf82bf4s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf82bf4s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf82bf4s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf82bf4s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf82bf4s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+__m128i test_mm_cvtbf8_bf4s (__m128i a) { return _mm_cvtbf8_bf4s (a); }
+__m128i test_mm256_cvtbf8_bf4s (__m256i a) { return _mm256_cvtbf8_bf4s (a); }
+__m256i test_mm512_cvtbf8_bf4s (__m512i a) { return _mm512_cvtbf8_bf4s (a); }
+
+__m128i test_mm_cvthf8_bf4s (__m128i a) { return _mm_cvthf8_bf4s (a); }
+__m128i test_mm256_cvthf8_bf4s (__m256i a) { return _mm256_cvthf8_bf4s (a); }
+__m256i test_mm512_cvthf8_bf4s (__m512i a) { return _mm512_cvthf8_bf4s (a); }
diff --git a/gcc/testsuite/gcc.target/i386/avx10_2-v2-aux-convert-6.c
b/gcc/testsuite/gcc.target/i386/avx10_2-v2-aux-convert-6.c
new file mode 100644
index 00000000000..eb70049c2c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_2-v2-aux-convert-6.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx10-v2-aux -O2" } */
+/* { dg-final { scan-assembler-times "vcvtbf42hf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf42hf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf42hf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf42hf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf42hf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf42hf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf42hf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf42hf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf42hf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+__m128i test_mm_cvtbf4_hf8 (__m128i a) { return _mm_cvtbf4_hf8 (a); }
+__m128i test_mm_mask_cvtbf4_hf8 (__m128i w, __mmask16 u, __m128i a) { return
_mm_mask_cvtbf4_hf8 (w, u, a); }
+__m128i test_mm_maskz_cvtbf4_hf8 (__mmask16 u, __m128i a) { return
_mm_maskz_cvtbf4_hf8 (u, a); }
+
+__m256i test_mm256_cvtbf4_hf8 (__m128i a) { return _mm256_cvtbf4_hf8 (a); }
+__m256i test_mm256_mask_cvtbf4_hf8 (__m256i w, __mmask32 u, __m128i a) {
return _mm256_mask_cvtbf4_hf8 (w, u, a); }
+__m256i test_mm256_maskz_cvtbf4_hf8 (__mmask32 u, __m128i a) { return
_mm256_maskz_cvtbf4_hf8 (u, a); }
+
+__m512i test_mm512_cvtbf4_hf8 (__m256i a) { return _mm512_cvtbf4_hf8 (a); }
+__m512i test_mm512_mask_cvtbf4_hf8 (__m512i w, __mmask64 u, __m256i a) {
return _mm512_mask_cvtbf4_hf8 (w, u, a); }
+__m512i test_mm512_maskz_cvtbf4_hf8 (__mmask64 u, __m256i a) { return
_mm512_maskz_cvtbf4_hf8 (u, a); }
--
2.34.1
