[llvm-branch-commits] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

@@ -2211,6 +2223,18 @@ ParseStatus RISCVAsmParser::parseVTypeI(OperandVector &Operands) { if (getLexer().is(AsmToken::EndOfStatement) && State == VTypeState_Done) { RISCVII::VLMUL VLMUL = RISCVVType::encodeLMUL(Lmul, Fractional); +if (Fractional) { + unsigned E

[llvm-branch-commits] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

@@ -2155,6 +2155,17 @@ bool RISCVAsmParser::parseVTypeToken(const AsmToken &Tok, VTypeState &State, break; if (!RISCVVType::isValidLMUL(Lmul, Fractional)) break; + +if (Fractional) { + unsigned ELEN = STI->hasFeature(RISCV::FeatureStdExtZve64x) ? 64 :

[llvm-branch-commits] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

@@ -2155,6 +2155,17 @@ bool RISCVAsmParser::parseVTypeToken(const AsmToken &Tok, VTypeState &State, break; if (!RISCVVType::isValidLMUL(Lmul, Fractional)) break; + +if (Fractional) { + unsigned ELEN = STI->hasFeature(RISCV::FeatureStdExtZve64x) ? 64 :

[llvm-branch-commits] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

@@ -2155,6 +2155,17 @@ bool RISCVAsmParser::parseVTypeToken(const AsmToken &Tok, VTypeState &State, break; if (!RISCVVType::isValidLMUL(Lmul, Fractional)) break; + +if (Fractional) { + unsigned ELEN = STI->hasFeature(RISCV::FeatureStdExtZve64x) ? 64 :

[llvm-branch-commits] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

@@ -71,18 +73,21 @@ vsetvli a2, a0, e32, m8, ta, ma vsetvli a2, a0, e32, mf2, ta, ma # CHECK-INST: vsetvli a2, a0, e32, mf2, ta, ma +# CHECK-WARNING: :[[#@LINE-2]]:17: warning: SEW > 16 may not be compatible with all RVV implementations{{$}} # CHECK-ENCODING: [0x57,0x76,0x75

[llvm-branch-commits] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

@@ -71,18 +73,21 @@ vsetvli a2, a0, e32, m8, ta, ma vsetvli a2, a0, e32, mf2, ta, ma # CHECK-INST: vsetvli a2, a0, e32, mf2, ta, ma +# CHECK-WARNING: :[[#@LINE-2]]:17: warning: SEW > 16 may not be compatible with all RVV implementations{{$}} # CHECK-ENCODING: [0x57,0x76,0x75

[llvm-branch-commits] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

@@ -2155,6 +2155,17 @@ bool RISCVAsmParser::parseVTypeToken(const AsmToken &Tok, VTypeState &State, break; if (!RISCVVType::isValidLMUL(Lmul, Fractional)) break; + +if (Fractional) { + unsigned ELEN = STI->hasFeature(RISCV::FeatureStdExtZve64x) ? 64 :

[llvm-branch-commits] [compiler-rt] Revert "[compiler-rt][RISCV] Implement __init_riscv_feature_bits (#85… (PR #101320)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/101320 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/19.x: [VP] Refactor VectorBuilder to avoid layering violation. NFC (#99276) (PR #101102)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/101102 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/19.x: [RISCV] Use experimental.vp.splat to splat specific vector length elements. (#101329) (PR #101506)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/101506 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [Clang][RISCV] Refactor builtins to TableGen (PR #80280)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/80280 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Support select optimization (PR #80124)

@@ -445,6 +450,9 @@ void RISCVPassConfig::addIRPasses() { if (EnableLoopDataPrefetch) addPass(createLoopDataPrefetchPass()); +if (EnableSelectOpt && getOptLevel() == CodeGenOptLevel::Aggressive) topperc wrote: Shoudl this be after addIRPasses li

[llvm-branch-commits] [RISCV] Support select optimization (PR #80124)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/80124 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

@@ -126,9 +126,10 @@ enum NodeType : unsigned { // Floating point fmax and fmin matching the RISC-V instruction semantics. FMAX, FMIN, - // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target - // (returns (Lo, Hi)). It takes a chain operand. - READ_CYCL

[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

@@ -11724,13 +11726,27 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N, Results.push_back(Result); break; } - case ISD::READCYCLECOUNTER: { -assert(!Subtarget.is64Bit() && - "READCYCLECOUNTER only has custom type legalization on riscv32"); +

[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

@@ -363,7 +365,7 @@ def CSRSystemRegister : AsmOperandClass { let DiagnosticType = "InvalidCSRSystemRegister"; } -def csr_sysreg : RISCVOp { +def csr_sysreg : RISCVOp, ImmLeaf(Imm);"> { topperc wrote: TImmLeaf https://github.com/llvm/llvm-project/pull/8232

[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)

@@ -1046,6 +1046,14 @@ def FeatureFastUnalignedAccess def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", "UsePostRAScheduler", "true", "Schedule again after register allocation">; +def FeaturePredictableSelectIsExpensive + : SubtargetFeature<"predictabl

[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)

https://github.com/topperc deleted https://github.com/llvm/llvm-project/pull/80124 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)

@@ -101,6 +101,11 @@ static cl::opt EnableMISchedLoadClustering( cl::desc("Enable load clustering in the machine scheduler"), cl::init(false)); +static cl::opt +EnableSelectOpt("riscv-select-opt", cl::Hidden, topperc wrote: If no in tree targets u

[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)

@@ -101,6 +101,11 @@ static cl::opt EnableMISchedLoadClustering( cl::desc("Enable load clustering in the machine scheduler"), cl::init(false)); +static cl::opt +EnableSelectOpt("riscv-select-opt", cl::Hidden, topperc wrote: But we added a bunch of

[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)

@@ -1136,11 +1136,35 @@ static void mergeAtomic(DenseMap &intAttr, }; } +static void mergeX3RegUse(DenseMap &intAttr, + const InputSectionBase *oldSection, + const InputSectionBase *newSection, + uns

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

@@ -14,12 +14,33 @@ #define LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H #include "llvm/CodeGen/TargetRegisterInfo.h" +#include "llvm/TargetParser/RISCVTargetParser.h" #define GET_REGINFO_HEADER #include "RISCVGenRegisterInfo.inc" namespace llvm { +enum { + // The VLMul

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

@@ -14,12 +14,33 @@ #define LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H #include "llvm/CodeGen/TargetRegisterInfo.h" +#include "llvm/TargetParser/RISCVTargetParser.h" #define GET_REGINFO_HEADER #include "RISCVGenRegisterInfo.inc" namespace llvm { +enum { + // The VLMul

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/84894 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -302,102 +302,87 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock &MBB, RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/84455 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -302,102 +302,87 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock &MBB, RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -302,102 +302,87 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock &MBB, RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -302,102 +302,87 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock &MBB, RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -302,102 +302,87 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock &MBB, RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned

[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)

@@ -101,6 +101,11 @@ static cl::opt EnableMISchedLoadClustering( cl::desc("Enable load clustering in the machine scheduler"), cl::init(false)); +static cl::opt +EnableSelectOpt("riscv-select-opt", cl::Hidden, topperc wrote: > I think the impact wo

[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)

@@ -1046,6 +1046,14 @@ def FeatureFastUnalignedAccess def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", "UsePostRAScheduler", "true", "Schedule again after register allocation">; +def FeaturePredictableSelectIsExpensive + : SubtargetFeature<"predictabl

[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)

topperc wrote: > > JFYI, I don't find the AArch64 data particularly convincing for RISCV. The > > magnitude of the change even on AArch64 is small, and could easily be swung > > one direction or the other by differences in implementation between the > > backends. > > Yeah! The result will dif

[llvm-branch-commits] [llvm] release/18.x: [Mips] Fix missing sign extension in expansion of sub-word atomic max (#77072) (PR #84566)

@@ -2001,8 +2225,6 @@ define i16 @test_umax_16(ptr nocapture %ptr, i16 signext %val) { ; MIPSELR6-NEXT: $BB6_1: # %entry ; MIPSELR6-NEXT:# =>This Inner Loop Header: Depth=1 ; MIPSELR6-NEXT:ll $2, 0($6) -; MIPSELR6-NEXT:and $2, $2, $8 topperc wrote

[llvm-branch-commits] [llvm] release/18.x: [Mips] Fix missing sign extension in expansion of sub-word atomic max (#77072) (PR #84566)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/84566 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [Mips] Fix missing sign extension in expansion of sub-word atomic max (#77072) (PR #84566)

@@ -2001,8 +2225,6 @@ define i16 @test_umax_16(ptr nocapture %ptr, i16 signext %val) { ; MIPSELR6-NEXT: $BB6_1: # %entry ; MIPSELR6-NEXT:# =>This Inner Loop Header: Depth=1 ; MIPSELR6-NEXT:ll $2, 0($6) -; MIPSELR6-NEXT:and $2, $2, $8 topperc wrote

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

@@ -483,90 +482,16 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB, } // VR->VR copies. - if (RISCV::VRRegClass.contains(DstReg, SrcReg)) { -copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1); -return; - } - - if (RISCV::VRM2Re

[llvm-branch-commits] [RISCV][NFC] Pass LMUL to copyPhysRegVector (PR #84448)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/84448 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/84894 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [Mips] Restore wrong deletion of instruction 'and' in unsigned min/max processing. (#85902) (PR #86424)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/86424 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -212,19 +185,13 @@ body: | ; CHECK-NEXT: $v7 = VMV1R_V $v14 ; CHECK-NEXT: $v8 = VMV1R_V $v15 ; CHECK-NEXT: $v9 = VMV1R_V $v16 -; CHECK-NEXT: $v4 = VMV1R_V $v10 -; CHECK-NEXT: $v5 = VMV1R_V $v11 -; CHECK-NEXT: $v6 = VMV1R_V $v12 -; CHEC

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -212,19 +185,13 @@ body: | ; CHECK-NEXT: $v7 = VMV1R_V $v14 ; CHECK-NEXT: $v8 = VMV1R_V $v15 ; CHECK-NEXT: $v9 = VMV1R_V $v16 -; CHECK-NEXT: $v4 = VMV1R_V $v10 -; CHECK-NEXT: $v5 = VMV1R_V $v11 -; CHECK-NEXT: $v6 = VMV1R_V $v12 -; CHEC

[llvm-branch-commits] [RISCV] Use the thread local stack protector for Android targets (PR #87672)

topperc wrote: > s/master/main/ in the url to get the current version. (master "works" but > it's frozen in time; main will track future changes.) > > otherwise lgtm... Probably someone should update AArch64 which has the same comment? https://github.com/llvm/llvm-project/pull/87672 _

[llvm-branch-commits] [llvm] Revert "[Mips] Fix missing sign extension in expansion of sub-word atomic max (#77072)" (PR #88818)

topperc wrote: > > Hi @nikic (or anyone else). If you would like to add a note about this fix > > in the release notes (completely optional). Please reply to this comment > > with a one or two sentence description of the fix. > > I'm not sure if this description is accurate: Fix the issue wher

[llvm-branch-commits] [llvm] release/18.x: [X86] Fix miscompile in combineShiftRightArithmetic (PR #86728)

topperc wrote: > > @phoebewang What do you think about backporting this? > > I didn't review on it. Maybe @topperc can evaluate it. I think this is ok to backport. https://github.com/llvm/llvm-project/pull/86728 ___ llvm-branch-commits mailing list l

[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)

topperc wrote: > For saturating instructions, they may write vxsat. This is like floating-point instructions that may write fflags, but we don't model floating-point instructions as hasSideEffects=1. That's because floating point instructions use mayRaiseFPExceptions=1. And STRICT_* nodes set d

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

@@ -47,6 +47,12 @@ include "RISCVSchedSiFiveP600.td" include "RISCVSchedSyntacoreSCR1.td" include "RISCVSchedXiangShanNanHu.td" +//===--===// +// RISC-V profiles supported. +//===--

[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/90187 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)

@@ -194,15 +194,12 @@ define void @vpmerge_vpload_store( %passthru, ptr %p, , i64 } @llvm.riscv.vleff.nxv2i32(, ptr, i64) define @vpmerge_vleff( %passthru, ptr %p, %m, i32 zeroext %vl) { ; CHECK-LABEL: vpmerge_vleff: ; CHECK: # %bb.0: -; CHECK-NEXT:vsetvli zero, a

[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/90049 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [RISCV][ISel] Fix types in `tryFoldSelectIntoOp` (#90659) (PR #90682)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/90682 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [X86] Enable EVEX512 when host CPU has AVX512 (#90479) (PR #90545)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/90545 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)

topperc wrote: @AtariDreams This bug has existed since at least LLVM 10. What makes it a candidate for backporting? https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.l

[llvm-branch-commits] [clang] [llvm] Backport "riscv-isa" module metadata to 18.x (PR #91514)

https://github.com/topperc milestoned https://github.com/llvm/llvm-project/pull/91514 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] Backport "riscv-isa" module metadata to 18.x (PR #91514)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/91514 Resolves #91513 >From f45df1cf1b74957e2f9609b982e964654f9af824 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 13 Feb 2024 16:17:50 -0800 Subject: [PATCH 1/3] [RISCV] Add canonical ISA string as Module me

[llvm-branch-commits] [clang] [llvm] Backport "riscv-isa" module metadata to 18.x (PR #91514)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/91514 >From ee109e3627e5b93297bfc7908f684eedb5feb5ec Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 13 Feb 2024 16:17:50 -0800 Subject: [PATCH 1/3] [RISCV] Add canonical ISA string as Module metadata in IR. (#

[llvm-branch-commits] [clang] [llvm] Backport "riscv-isa" module metadata to 18.x (PR #91514)

topperc wrote: > Can you briefly summarize why this is important to backport? At first glance, > this is only relevant for LTO with mixed architecture specifications, > which... I can see someone might want it, I guess, but it seems pretty easy > to work around not having it. It's not just mi

[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

https://github.com/topperc milestoned https://github.com/llvm/llvm-project/pull/92143 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/92143 Backport 9067070d91e9d8cdd8509ffa56a076f08a3d7281 for #92134 >From 5c5c57534751621f775dca5776af10e1870e6eb8 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 16 Apr 2024 15:40:32 -0700 Subject: [PATCH] [RIS

[llvm-branch-commits] [llvm] release/18.x: [X86][Driver] Do not add `-evex512` for `-march=native` when the target doesn't support AVX512 (#91694) (PR #91705)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/91705 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

topperc wrote: > Note that backporting this may require changes for LLVM users (I know that it > will require rustc changes at least). This may not be a good candidate for > the last 18.1 point release. Can you point me to the relevant rust code? I found this line which looks like it wasn't u

[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

topperc wrote: > > Note that backporting this may require changes for LLVM users (I know that > > it will require rustc changes at least). This may not be a good candidate > > for the last 18.1 point release. > > Can you point me to the relevant rust code? I found this line which looks > like

[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)

topperc wrote: > @topperc Do you have any strong objections to backporting this? This looks > small to me and I think it's OK to fix long-standing bugs. No objection. https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing li

[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

topperc wrote: Maybe I could make fast-unaligned-access only apply to scalar to avoid a name change. And give a new flag for vector? There's not a lot of RISC-V vector hardware available yet. One of the CPUs that is available only supports unaligned scalars and not vectors. https://github.com

[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

topperc wrote: > I don't think we need to backport this at all. None of the in tree cpus fall > into the category where the distinction is important, and I don't feel we > have any obligation to backport support for our of tree forks. There's no out of tree fork involved here. The bug reporter

[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

topperc wrote: > I'm not strongly opposed to this or anything, but it feels questionable to be > doing a backport to change the target-feature syntax. My understand is that > these are purely internal names. This isn't a documented public interface. It isn't documented, but some users were usi

[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/92143 >From e18e442947da7801c915c04e34e397464eca5034 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 16 May 2024 12:27:05 -0700 Subject: [PATCH] [RISCV] Add a unaligned-scalar-mem feature like we had in clang 1

[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/92143 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

topperc wrote: > @topperc Can this be merged as is? There might not be time to get an updated > patch merged before the last release. I just pushed a modified patch. What is the timeline for the last release? https://github.com/llvm/llvm-project/pull/92143 _

[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

topperc wrote: > @topperc (or anyone else). If you would like to add a note about this fix in > the release notes (completely optional). Please reply to this comment with a > one or two sentence description of the fix. When you are done, please add the > release:note label to this PR. `-Xclan

[llvm-branch-commits] [llvm] e99ee06 - [X86] Reject fpsr in inline asm constraints other than clobber.

Author: Craig Topper Date: 2023-11-22T18:59:41-08:00 New Revision: e99ee06400404d3058e6f379465b9ac50aedb74c URL: https://github.com/llvm/llvm-project/commit/e99ee06400404d3058e6f379465b9ac50aedb74c DIFF: https://github.com/llvm/llvm-project/commit/e99ee06400404d3058e6f379465b9ac50aedb74c.diff

[llvm-branch-commits] [llvm] dc683d2 - [X86] Remove unused IES_IDENTIFIER state from IntelExprState. NFC

Author: Craig Topper Date: 2023-11-22T19:49:52-08:00 New Revision: dc683d2e66de79bbea786f51788961eec5d0b793 URL: https://github.com/llvm/llvm-project/commit/dc683d2e66de79bbea786f51788961eec5d0b793 DIFF: https://github.com/llvm/llvm-project/commit/dc683d2e66de79bbea786f51788961eec5d0b793.diff

[llvm-branch-commits] [llvm] e99ee06 - [X86] Reject fpsr in inline asm constraints other than clobber.

Author: Craig Topper Date: 2023-11-22T18:59:41-08:00 New Revision: e99ee06400404d3058e6f379465b9ac50aedb74c URL: https://github.com/llvm/llvm-project/commit/e99ee06400404d3058e6f379465b9ac50aedb74c DIFF: https://github.com/llvm/llvm-project/commit/e99ee06400404d3058e6f379465b9ac50aedb74c.diff

[llvm-branch-commits] [llvm] dc683d2 - [X86] Remove unused IES_IDENTIFIER state from IntelExprState. NFC

Author: Craig Topper Date: 2023-11-22T19:49:52-08:00 New Revision: dc683d2e66de79bbea786f51788961eec5d0b793 URL: https://github.com/llvm/llvm-project/commit/dc683d2e66de79bbea786f51788961eec5d0b793 DIFF: https://github.com/llvm/llvm-project/commit/dc683d2e66de79bbea786f51788961eec5d0b793.diff

[llvm-branch-commits] [llvm] e99ee06 - [X86] Reject fpsr in inline asm constraints other than clobber.

Author: Craig Topper Date: 2023-11-22T18:59:41-08:00 New Revision: e99ee06400404d3058e6f379465b9ac50aedb74c URL: https://github.com/llvm/llvm-project/commit/e99ee06400404d3058e6f379465b9ac50aedb74c DIFF: https://github.com/llvm/llvm-project/commit/e99ee06400404d3058e6f379465b9ac50aedb74c.diff

[llvm-branch-commits] [llvm] dc683d2 - [X86] Remove unused IES_IDENTIFIER state from IntelExprState. NFC

Author: Craig Topper Date: 2023-11-22T19:49:52-08:00 New Revision: dc683d2e66de79bbea786f51788961eec5d0b793 URL: https://github.com/llvm/llvm-project/commit/dc683d2e66de79bbea786f51788961eec5d0b793 DIFF: https://github.com/llvm/llvm-project/commit/dc683d2e66de79bbea786f51788961eec5d0b793.diff

[llvm-branch-commits] [llvm] b92bf0d - [RISCV] Disable clang-format around the RISCVISD opcode enum. NFC

Author: Craig Topper Date: 2023-11-29T14:01:30-08:00 New Revision: b92bf0dad6ec9760e008a0fa22d7dbd0b045c776 URL: https://github.com/llvm/llvm-project/commit/b92bf0dad6ec9760e008a0fa22d7dbd0b045c776 DIFF: https://github.com/llvm/llvm-project/commit/b92bf0dad6ec9760e008a0fa22d7dbd0b045c776.diff

[llvm-branch-commits] [clang] PR for llvm/llvm-project#79479 (PR #79907)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/79907 Resolves https://github.com/llvm/llvm-project/issues/79479. >From 8fb154776db1627da75e6d67cf468d5b55868e93 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 25 Jan 2024 09:14:52 -0800 Subject: [PATCH 1/2] [

[llvm-branch-commits] [llvm] [RISCV] Backport 5cf9f2cd9888feea23a624c1de3cc37ce8ce8112 to release/18.x (PR #79931)

topperc wrote: @tstellar Backport looks good to me. https://github.com/llvm/llvm-project/pull/79931 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)

@@ -2113,3 +2113,17 @@ bool RISCVTTIImpl::shouldConsiderAddressTypePromotion( } return Considerable; } + +RISCVTTIImpl::TTI::MemCmpExpansionOptions +RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { + TTI::MemCmpExpansionOptions Options; + // FIXME

[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)

@@ -112,42 +104,46 @@ entry: define i32 @bcmp_size_2(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-ALIGNED-RV32-LABEL: bcmp_size_2: ; CHECK-ALIGNED-RV32: # %bb.0: # %entry -; CHECK-ALIGNED-RV32-NEXT:addi sp, sp, -16 -; CHECK-ALIGNED-RV32-NEXT:sw ra, 12(sp) # 4-byte

[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)

@@ -1144,42 +2872,116 @@ entry: define i32 @memcmp_size_4(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV32-LABEL: memcmp_size_4: ; CHECK-ALIGNED-RV32: # %bb.0: # %entry -; CHECK-ALIGNED-RV32-NEXT:addi sp, sp, -16 -; CHECK-ALIGNED-RV32-NEXT:sw ra, 12(sp) # 4-byte

[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/107548 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)

@@ -1144,42 +2872,116 @@ entry: define i32 @memcmp_size_4(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV32-LABEL: memcmp_size_4: ; CHECK-ALIGNED-RV32: # %bb.0: # %entry -; CHECK-ALIGNED-RV32-NEXT:addi sp, sp, -16 -; CHECK-ALIGNED-RV32-NEXT:sw ra, 12(sp) # 4-byte

[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)

topperc wrote: > The run just finished, I'm seeing a 0.75% improvement on 500.perlbench_r on > the BPI F3 (-O3 -mcpu=spacemit-x60), no regressions or improvements on the > other benchmarks as far as I can see. Seems to check out with the number of > memcmps inlined reported for perlbench! Doe

[llvm-branch-commits] [llvm] 147c0c2 - [TargetLowering] Use isOneConstant to simplify some code. NFC

Author: Craig Topper Date: 2021-01-22T19:32:19-08:00 New Revision: 147c0c263d88a9702aba17fbeac62ff83e6c1319 URL: https://github.com/llvm/llvm-project/commit/147c0c263d88a9702aba17fbeac62ff83e6c1319 DIFF: https://github.com/llvm/llvm-project/commit/147c0c263d88a9702aba17fbeac62ff83e6c1319.diff

[llvm-branch-commits] [llvm] d2927f7 - [RISCV] Add isel patterns to remove (and X, 31) from sllw/srlw/sraw shift amounts.

Author: Craig Topper Date: 2021-01-23T15:08:18-08:00 New Revision: d2927f786e877410d90c1e6f0e0c7d99524529c5 URL: https://github.com/llvm/llvm-project/commit/d2927f786e877410d90c1e6f0e0c7d99524529c5 DIFF: https://github.com/llvm/llvm-project/commit/d2927f786e877410d90c1e6f0e0c7d99524529c5.diff

[llvm-branch-commits] [llvm] 5a73daf - [RISCV] Add test cases for SRO/SLO with shift amounts masked to bitwidth-1. NFC

Author: Craig Topper Date: 2021-01-23T15:45:51-08:00 New Revision: 5a73daf907873a8757213932f814361a59f02da5 URL: https://github.com/llvm/llvm-project/commit/5a73daf907873a8757213932f814361a59f02da5 DIFF: https://github.com/llvm/llvm-project/commit/5a73daf907873a8757213932f814361a59f02da5.diff

[llvm-branch-commits] [llvm] 998057e - [RISCV] Add isel patterns to remove masks on SLO/SRO shift amounts.

Author: Craig Topper Date: 2021-01-23T15:57:41-08:00 New Revision: 998057ec06ae7e0fb1e0be0f2702df4d6338a128 URL: https://github.com/llvm/llvm-project/commit/998057ec06ae7e0fb1e0be0f2702df4d6338a128 DIFF: https://github.com/llvm/llvm-project/commit/998057ec06ae7e0fb1e0be0f2702df4d6338a128.diff

[llvm-branch-commits] [llvm] c7d5d8f - [RISCV] Group some Zbs isel patterns together and remove a stale comment. NFC

Author: Craig Topper Date: 2021-01-23T16:45:05-08:00 New Revision: c7d5d8fa33a0f23b262b695d17fdffdefa8dc940 URL: https://github.com/llvm/llvm-project/commit/c7d5d8fa33a0f23b262b695d17fdffdefa8dc940 DIFF: https://github.com/llvm/llvm-project/commit/c7d5d8fa33a0f23b262b695d17fdffdefa8dc940.diff

[llvm-branch-commits] [llvm] c50457f - [RISCV] Make the code in MatchSLLIUW ignore the lower bits of the AND mask where the shift has guaranteed zeros.

Author: Craig Topper Date: 2021-01-24T00:34:45-08:00 New Revision: c50457f3e4209b0cd0d4a6baa881bac30a9d3016 URL: https://github.com/llvm/llvm-project/commit/c50457f3e4209b0cd0d4a6baa881bac30a9d3016 DIFF: https://github.com/llvm/llvm-project/commit/c50457f3e4209b0cd0d4a6baa881bac30a9d3016.diff

[llvm-branch-commits] [llvm] 116177a - [RISCV] Use SRLIWPat in the PACKUW pattern.

Author: Craig Topper Date: 2021-01-24T10:41:58-08:00 New Revision: 116177afcce88d807c1beffcb9221999ad8a69a9 URL: https://github.com/llvm/llvm-project/commit/116177afcce88d807c1beffcb9221999ad8a69a9 DIFF: https://github.com/llvm/llvm-project/commit/116177afcce88d807c1beffcb9221999ad8a69a9.diff

[llvm-branch-commits] [llvm] 60ebf64 - [RISCV] Add test cases for missed opportunities to use fcvt.*.w(u) instructions on RV64 when input is known to be extended from i8/i16.

Author: Craig Topper Date: 2021-01-24T13:48:29-08:00 New Revision: 60ebf6408e965635deb94bcdead8ac9451bf0ee9 URL: https://github.com/llvm/llvm-project/commit/60ebf6408e965635deb94bcdead8ac9451bf0ee9 DIFF: https://github.com/llvm/llvm-project/commit/60ebf6408e965635deb94bcdead8ac9451bf0ee9.diff

[llvm-branch-commits] [llvm] f22aa8f - [RISCV] Add test cases for missed opportunities to use *W instructions for div/rem when inputs are sign/zero extended from i8/16 instead of i32.

Author: Craig Topper Date: 2021-01-24T13:56:38-08:00 New Revision: f22aa8f87931075834f973cebaa84c07ab1a26b1 URL: https://github.com/llvm/llvm-project/commit/f22aa8f87931075834f973cebaa84c07ab1a26b1 DIFF: https://github.com/llvm/llvm-project/commit/f22aa8f87931075834f973cebaa84c07ab1a26b1.diff

[llvm-branch-commits] [llvm] 12d0753 - [RISCV] Use bitsLE instead of strict == MVT::i32 in assertsexti32 and assertzexti32.

Author: Craig Topper Date: 2021-01-24T13:58:14-08:00 New Revision: 12d0753aca22896fda2cf76781b0ee0524d55065 URL: https://github.com/llvm/llvm-project/commit/12d0753aca22896fda2cf76781b0ee0524d55065 DIFF: https://github.com/llvm/llvm-project/commit/12d0753aca22896fda2cf76781b0ee0524d55065.diff

[llvm-branch-commits] [llvm] 4eb4f89 - [RISCV] Use sign extend for i32 arguments and returns in makeLibCall on RV64.

Author: Craig Topper Date: 2021-01-25T09:33:48-08:00 New Revision: 4eb4f8963f1e4998748bca66a512c3298f6d2289 URL: https://github.com/llvm/llvm-project/commit/4eb4f8963f1e4998748bca66a512c3298f6d2289 DIFF: https://github.com/llvm/llvm-project/commit/4eb4f8963f1e4998748bca66a512c3298f6d2289.diff

[llvm-branch-commits] [llvm] 239cfbc - [RISCV] Custom type legalize i8/i16 UDIV/UREM/SDIV on RV64 so we can use divuw/remuw/divw.

Author: Craig Topper Date: 2021-01-25T10:47:22-08:00 New Revision: 239cfbccb0509da1a08d9e746706013b732e646b URL: https://github.com/llvm/llvm-project/commit/239cfbccb0509da1a08d9e746706013b732e646b DIFF: https://github.com/llvm/llvm-project/commit/239cfbccb0509da1a08d9e746706013b732e646b.diff

[llvm-branch-commits] [llvm-branch] r296587 - ReleaseNotes: Add some X86 target bullets.

Author: ctopper Date: Wed Mar 1 02:04:06 2017 New Revision: 296587 URL: http://llvm.org/viewvc/llvm-project?rev=296587&view=rev Log: ReleaseNotes: Add some X86 target bullets. Modified: llvm/branches/release_40/docs/ReleaseNotes.rst Modified: llvm/branches/release_40/docs/ReleaseNotes.rst U

[llvm-branch-commits] [cfe-branch] r299404 - Merging r299346:

Author: ctopper Date: Mon Apr 3 19:28:56 2017 New Revision: 299404 URL: http://llvm.org/viewvc/llvm-project?rev=299404&view=rev Log: Merging r299346: r299346 | ctopper | 2017-04-02 20:41:29 -0700 (Sun, 02 Apr 2017) | 3 lines

[llvm-branch-commits] [cfe-branch] r299405 - Merging r299347:

Author: ctopper Date: Mon Apr 3 19:31:22 2017 New Revision: 299405 URL: http://llvm.org/viewvc/llvm-project?rev=299405&view=rev Log: Merging r299347: r299347 | ctopper | 2017-04-02 20:51:57 -0700 (Sun, 02 Apr 2017) | 1 line

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