Author: Craig Topper Date: 2021-01-24T00:34:45-08:00 New Revision: c50457f3e4209b0cd0d4a6baa881bac30a9d3016
URL: https://github.com/llvm/llvm-project/commit/c50457f3e4209b0cd0d4a6baa881bac30a9d3016 DIFF: https://github.com/llvm/llvm-project/commit/c50457f3e4209b0cd0d4a6baa881bac30a9d3016.diff LOG: [RISCV] Make the code in MatchSLLIUW ignore the lower bits of the AND mask where the shift has guaranteed zeros. This avoids being dependent on SimplifyDemandedBits having cleared those bits. It could make sense to teach SimplifyDemandedBits to keep all lower bits 1 in an AND mask when possible. This could be implemented with slli+srli in the general case rather than needing to materialize the constant. Added: Modified: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index 078ed1b8d8d1..2198b275ec11 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -871,7 +871,7 @@ bool RISCVDAGToDAGISel::MatchSLLIUW(SDNode *N) const { // Immediate range should be enforced by uimm5 predicate. assert(VC2 < 32 && "Unexpected immediate"); - return VC1 == ((uint64_t)0xFFFFFFFF << VC2); + return (VC1 >> VC2) == UINT64_C(0xFFFFFFFF); } bool RISCVDAGToDAGISel::selectVSplat(SDValue N, SDValue &SplatVal) { _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
