Author: Craig Topper Date: 2021-01-24T13:48:29-08:00 New Revision: 60ebf6408e965635deb94bcdead8ac9451bf0ee9
URL: https://github.com/llvm/llvm-project/commit/60ebf6408e965635deb94bcdead8ac9451bf0ee9 DIFF: https://github.com/llvm/llvm-project/commit/60ebf6408e965635deb94bcdead8ac9451bf0ee9.diff LOG: [RISCV] Add test cases for missed opportunities to use fcvt.*.w(u) instructions on RV64 when input is known to be extended from i8/i16. Added: Modified: llvm/test/CodeGen/RISCV/double-convert.ll llvm/test/CodeGen/RISCV/float-convert.ll llvm/test/CodeGen/RISCV/half-convert.ll Removed: ################################################################################ diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll index 7a27a8e569a9..5599775ffd68 100644 --- a/llvm/test/CodeGen/RISCV/double-convert.ll +++ b/llvm/test/CodeGen/RISCV/double-convert.ll @@ -267,3 +267,83 @@ define double @fmv_d_x(i64 %a, i64 %b) nounwind { %3 = fadd double %1, %2 ret double %3 } + +define double @fcvt_d_w_i8(i8 signext %a) nounwind { +; RV32IFD-LABEL: fcvt_d_w_i8: +; RV32IFD: # %bb.0: +; RV32IFD-NEXT: addi sp, sp, -16 +; RV32IFD-NEXT: fcvt.d.w ft0, a0 +; RV32IFD-NEXT: fsd ft0, 8(sp) +; RV32IFD-NEXT: lw a0, 8(sp) +; RV32IFD-NEXT: lw a1, 12(sp) +; RV32IFD-NEXT: addi sp, sp, 16 +; RV32IFD-NEXT: ret +; +; RV64IFD-LABEL: fcvt_d_w_i8: +; RV64IFD: # %bb.0: +; RV64IFD-NEXT: fcvt.d.l ft0, a0 +; RV64IFD-NEXT: fmv.x.d a0, ft0 +; RV64IFD-NEXT: ret + %1 = sitofp i8 %a to double + ret double %1 +} + +define double @fcvt_d_wu_i8(i8 zeroext %a) nounwind { +; RV32IFD-LABEL: fcvt_d_wu_i8: +; RV32IFD: # %bb.0: +; RV32IFD-NEXT: addi sp, sp, -16 +; RV32IFD-NEXT: fcvt.d.wu ft0, a0 +; RV32IFD-NEXT: fsd ft0, 8(sp) +; RV32IFD-NEXT: lw a0, 8(sp) +; RV32IFD-NEXT: lw a1, 12(sp) +; RV32IFD-NEXT: addi sp, sp, 16 +; RV32IFD-NEXT: ret +; +; RV64IFD-LABEL: fcvt_d_wu_i8: +; RV64IFD: # %bb.0: +; RV64IFD-NEXT: fcvt.d.lu ft0, a0 +; RV64IFD-NEXT: fmv.x.d a0, ft0 +; RV64IFD-NEXT: ret + %1 = uitofp i8 %a to double + ret double %1 +} + +define double @fcvt_d_w_i16(i16 signext %a) nounwind { +; RV32IFD-LABEL: fcvt_d_w_i16: +; RV32IFD: # %bb.0: +; RV32IFD-NEXT: addi sp, sp, -16 +; RV32IFD-NEXT: fcvt.d.w ft0, a0 +; RV32IFD-NEXT: fsd ft0, 8(sp) +; RV32IFD-NEXT: lw a0, 8(sp) +; RV32IFD-NEXT: lw a1, 12(sp) +; RV32IFD-NEXT: addi sp, sp, 16 +; RV32IFD-NEXT: ret +; +; RV64IFD-LABEL: fcvt_d_w_i16: +; RV64IFD: # %bb.0: +; RV64IFD-NEXT: fcvt.d.l ft0, a0 +; RV64IFD-NEXT: fmv.x.d a0, ft0 +; RV64IFD-NEXT: ret + %1 = sitofp i16 %a to double + ret double %1 +} + +define double @fcvt_d_wu_i16(i16 zeroext %a) nounwind { +; RV32IFD-LABEL: fcvt_d_wu_i16: +; RV32IFD: # %bb.0: +; RV32IFD-NEXT: addi sp, sp, -16 +; RV32IFD-NEXT: fcvt.d.wu ft0, a0 +; RV32IFD-NEXT: fsd ft0, 8(sp) +; RV32IFD-NEXT: lw a0, 8(sp) +; RV32IFD-NEXT: lw a1, 12(sp) +; RV32IFD-NEXT: addi sp, sp, 16 +; RV32IFD-NEXT: ret +; +; RV64IFD-LABEL: fcvt_d_wu_i16: +; RV64IFD: # %bb.0: +; RV64IFD-NEXT: fcvt.d.lu ft0, a0 +; RV64IFD-NEXT: fmv.x.d a0, ft0 +; RV64IFD-NEXT: ret + %1 = uitofp i16 %a to double + ret double %1 +} diff --git a/llvm/test/CodeGen/RISCV/float-convert.ll b/llvm/test/CodeGen/RISCV/float-convert.ll index c160ae5d8cd5..de4be78f3cf6 100644 --- a/llvm/test/CodeGen/RISCV/float-convert.ll +++ b/llvm/test/CodeGen/RISCV/float-convert.ll @@ -192,3 +192,67 @@ define float @fcvt_s_lu(i64 %a) nounwind { %1 = uitofp i64 %a to float ret float %1 } + +define float @fcvt_s_w_i8(i8 signext %a) nounwind { +; RV32IF-LABEL: fcvt_s_w_i8: +; RV32IF: # %bb.0: +; RV32IF-NEXT: fcvt.s.w ft0, a0 +; RV32IF-NEXT: fmv.x.w a0, ft0 +; RV32IF-NEXT: ret +; +; RV64IF-LABEL: fcvt_s_w_i8: +; RV64IF: # %bb.0: +; RV64IF-NEXT: fcvt.s.l ft0, a0 +; RV64IF-NEXT: fmv.x.w a0, ft0 +; RV64IF-NEXT: ret + %1 = sitofp i8 %a to float + ret float %1 +} + +define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind { +; RV32IF-LABEL: fcvt_s_wu_i8: +; RV32IF: # %bb.0: +; RV32IF-NEXT: fcvt.s.wu ft0, a0 +; RV32IF-NEXT: fmv.x.w a0, ft0 +; RV32IF-NEXT: ret +; +; RV64IF-LABEL: fcvt_s_wu_i8: +; RV64IF: # %bb.0: +; RV64IF-NEXT: fcvt.s.lu ft0, a0 +; RV64IF-NEXT: fmv.x.w a0, ft0 +; RV64IF-NEXT: ret + %1 = uitofp i8 %a to float + ret float %1 +} + +define float @fcvt_s_w_i16(i16 signext %a) nounwind { +; RV32IF-LABEL: fcvt_s_w_i16: +; RV32IF: # %bb.0: +; RV32IF-NEXT: fcvt.s.w ft0, a0 +; RV32IF-NEXT: fmv.x.w a0, ft0 +; RV32IF-NEXT: ret +; +; RV64IF-LABEL: fcvt_s_w_i16: +; RV64IF: # %bb.0: +; RV64IF-NEXT: fcvt.s.l ft0, a0 +; RV64IF-NEXT: fmv.x.w a0, ft0 +; RV64IF-NEXT: ret + %1 = sitofp i16 %a to float + ret float %1 +} + +define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind { +; RV32IF-LABEL: fcvt_s_wu_i16: +; RV32IF: # %bb.0: +; RV32IF-NEXT: fcvt.s.wu ft0, a0 +; RV32IF-NEXT: fmv.x.w a0, ft0 +; RV32IF-NEXT: ret +; +; RV64IF-LABEL: fcvt_s_wu_i16: +; RV64IF: # %bb.0: +; RV64IF-NEXT: fcvt.s.lu ft0, a0 +; RV64IF-NEXT: fmv.x.w a0, ft0 +; RV64IF-NEXT: ret + %1 = uitofp i16 %a to float + ret float %1 +} diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll index 7f4bd333a506..bc9122a7618e 100644 --- a/llvm/test/CodeGen/RISCV/half-convert.ll +++ b/llvm/test/CodeGen/RISCV/half-convert.ll @@ -200,6 +200,30 @@ define half @fcvt_h_si(i16 %a) nounwind { ret half %1 } +define half @fcvt_h_si_signext(i16 signext %a) nounwind { +; RV32IZFH-LABEL: fcvt_h_si_signext: +; RV32IZFH: # %bb.0: +; RV32IZFH-NEXT: fcvt.h.w fa0, a0 +; RV32IZFH-NEXT: ret +; +; RV32IDZFH-LABEL: fcvt_h_si_signext: +; RV32IDZFH: # %bb.0: +; RV32IDZFH-NEXT: fcvt.h.w fa0, a0 +; RV32IDZFH-NEXT: ret +; +; RV64IZFH-LABEL: fcvt_h_si_signext: +; RV64IZFH: # %bb.0: +; RV64IZFH-NEXT: fcvt.h.l fa0, a0 +; RV64IZFH-NEXT: ret +; +; RV64IDZFH-LABEL: fcvt_h_si_signext: +; RV64IDZFH: # %bb.0: +; RV64IDZFH-NEXT: fcvt.h.l fa0, a0 +; RV64IDZFH-NEXT: ret + %1 = sitofp i16 %a to half + ret half %1 +} + define half @fcvt_h_ui(i16 %a) nounwind { ; RV32IZFH-LABEL: fcvt_h_ui: ; RV32IZFH: # %bb.0: @@ -236,6 +260,30 @@ define half @fcvt_h_ui(i16 %a) nounwind { ret half %1 } +define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind { +; RV32IZFH-LABEL: fcvt_h_ui_zeroext: +; RV32IZFH: # %bb.0: +; RV32IZFH-NEXT: fcvt.h.wu fa0, a0 +; RV32IZFH-NEXT: ret +; +; RV32IDZFH-LABEL: fcvt_h_ui_zeroext: +; RV32IDZFH: # %bb.0: +; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0 +; RV32IDZFH-NEXT: ret +; +; RV64IZFH-LABEL: fcvt_h_ui_zeroext: +; RV64IZFH: # %bb.0: +; RV64IZFH-NEXT: fcvt.h.lu fa0, a0 +; RV64IZFH-NEXT: ret +; +; RV64IDZFH-LABEL: fcvt_h_ui_zeroext: +; RV64IDZFH: # %bb.0: +; RV64IDZFH-NEXT: fcvt.h.lu fa0, a0 +; RV64IDZFH-NEXT: ret + %1 = uitofp i16 %a to half + ret half %1 +} + define half @fcvt_h_w(i32 %a) nounwind { ; RV32IZFH-LABEL: fcvt_h_w: ; RV32IZFH: # %bb.0: _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
