================
@@ -71,18 +73,21 @@ vsetvli a2, a0, e32, m8, ta, ma
vsetvli a2, a0, e32, mf2, ta, ma
# CHECK-INST: vsetvli a2, a0, e32, mf2, ta, ma
+# CHECK-WARNING: :[[#@LINE-2]]:17: warning: SEW > 16 may not be compatible
with all RVV implementations{{$}}
# CHECK-ENCODING: [0x57,0x76,0x75,0x0d]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for
Application Processors), 'Zve32x' (Vector Extensions for Embedded
Processors){{$}}
# CHECK-UNKNOWN: 0d757657 <unknown>
vsetvli a2, a0, e32, mf4, ta, ma
# CHECK-INST: vsetvli a2, a0, e32, mf4, ta, ma
+# CHECK-WARNING: :[[#@LINE-2]]:17: warning: SEW > 8 may not be compatible with
all RVV implementations{{$}}
----------------
topperc wrote:
> Ok, that seems reasonable. Should we maybe then reword the LMUL < SEWMIN/ELEN
> case to mention that the encoding is actually reserved, whereas for SEW >
> LMUL * ELEN it may just not be compatible
I don't think it is reserved. This is the paragraph from the spec
```
Implementations must provide fractional LMUL settings that allow the narrowest
supported type to occupy a fraction of a vector register corresponding to the
ratio of the narrowest supported type’s width to that of the largest supported
type’s width. In general, the requirement is to support LMUL ≥ SEWMIN/ELEN,
where SEWMIN is the narrowest supported SEW value and ELEN is the widest
supported SEW value. In the standard extensions, SEWMIN=8. For standard vector
extensions with ELEN=32, fractional LMULs of 1/2 and 1/4 must be supported. For
standard vector extensions with ELEN=64, fractional LMULs of 1/2, 1/4, and 1/8
must be supported.
```
It doesn't say it can't be supported. It only says what must be supported.
https://github.com/llvm/llvm-project/pull/94313
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