if (adjacent_mem_locations (opnd2, opnd) == opnd2)
> + {
> + opnd = adjust_address (opnd2, OOmode, 0);
> + /* Skip the next register, since we're going to
> + load it together with this register. */
> + i++;
> + }
> + }
> + }
I think it is fine now, but please factor the patch and repost. Thanks!
Segher
t; + chomp($gitaddr);
> + if ($gitaddr) {
> + $addr = $gitaddr;
> + }
> +}
"-d .git" is, erm, not so great.
How about something like
sub get_git_config {
my $res = `git config --get @_`;
return undef if $?;
chomp $res;
return $res;
}
Segher
ERPC64"
That's not the correct condition: the carry bit is set based on the 32-bit
carry in 32-bit mode, so the condition has to be TARGET_64BIT.
The adddi3 pattern has !TARGET_POWERPC64 since a 64-bit addition can
be done without addc on a 64-bit machine, no matter what mode the CPU
is in.
> + "*
> +{
Might as well leave out this stuff on new code, just use the braces :-)
Segher
't
run the testsuite (I have no emulator set up).
Thanks,
Segher
gcc/
PR target/60822
2014-04-16 Segher Boessenkool
* config/m68k/m68k.md (extendplussidi): Don't allow memory for
operand 1.
---
gcc/config/m68k/m68k.md | 5 -
1 file changed, 4 insertions(+), 1
On Fri, Sep 29, 2023 at 02:09:12PM -0400, Michael Meissner wrote:
> * config/rs6000/rs6000.md (UNSPEC_COPYSIGN): Delete.
> (copysign3_fcpsg): Use copysign RTL instead of UNSPEC.
(typo, it is _fcpsgn)
Nice to see unnecessary unspecs going away :-)
Segher
PLUGIN_HEADERS.
>
> Fixed thusly, tested on powerpc64le-linux, ok for trunk and 8.2?
Yes please. Thanks!
Segher
> 2018-06-28 Jakub Jelinek
>
> * config/rs6000/t-rs6000: Append rs6000-modes.h to TM_H.
ltivec" } */
This needs p8vector_ok then. Is that correct? What requires p8?
Is VSX (p7) enough for everything here?
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/altivec-2-runnable.c
> @@ -0,0 +1,94 @@
> +/* { dg-do compile { target powerpc*-*-* } } */
> +/* { dg-require-effective-target powerpc_altivec_ok } */
> +/* { dg-options "-mpower8-vector -mvsx" } */
Same here: required target does not match options.
Rest looks fine.
Segher
tting to trunk. This should also go to 8.
Segher
2018-06-26 Segher Boessenkool
PR target/86285
* config/rs6000/rs6000.c (rs6000_init_builtins): Do not set
ieee128_float_type_node to long_double_type_node unless
TARGET_LONG_DOUBLE_128 is set.
---
gcc/c
ine 5429 there's set of align_jumps_max_skip to 15 if not set
> by default.
> At line 5412 align_jumps is set to 8, and align_jumps_max_skip should be
> equal align_jumps - 1.
> That's a discrepancy. Segher can you please take a look?
This is powerpcspe, that's
You should write your patch so that the end result behaves the same as
before, on all targets. If that requires changing (or at least checking)
all targets, then you have a lot of work to do.
If you think the rs6000 backend is doing something wrong, please say
what exactly? I don't see it.
Still confused,
Segher
The target has been removed, so we shouldn't try to build it.
Segher
2018-07-03 Segher Boessenkool
* contrib/config-list.mk: Remove powerpc-linux_paired.
---
contrib/config-list.mk | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/contrib/config-list
On Tue, Jul 03, 2018 at 02:51:27PM +0200, Martin Liška wrote:
> On 07/03/2018 12:58 PM, Segher Boessenkool wrote:
> > On Tue, Jul 03, 2018 at 12:15:48PM +0200, Martin Liška wrote:
> >>> toplev.c already has (in init_alignments):
> >>>
> >>
Hi Carl,
On Tue, Jul 03, 2018 at 02:36:22PM -0700, Carl Love wrote:
> Please let me know if the patch looks OK for GCC mainline. The patch
> also needs to be backported to GCC 8.
Looks great, thanks! Okay for trunk, and also for 8.
Segher
> 2018-07-03 Carl Love
>
>
Other than this thing, the original code was easier to read. What does
this part of the patch improve?
Segher
On Fri, Jul 06, 2018 at 09:38:02AM -0400, Michael Meissner wrote:
> On Fri, Jul 06, 2018 at 06:38:55AM -0500, Segher Boessenkool wrote:
> > On Fri, Jul 06, 2018 at 01:51:37AM -0400, Michael Meissner wrote:
> > > case "$target:$with_long_double_format" in
>
e here.
For cross builds the burden of having compatible versions of everything is
on the user anyhow (I'm not saying this is a good thing, but this is the
status quo).
Maybe some test could be done that mimics what happens 10m into a build
(the build failure)? But Tulio's test should be okay for most cases, too.
Segher
powerpc64le-unknown-linux-gnu (Power 8 LE)
>
> With no regressions.
>
> Please let me know if the patch looks OK for GCC 7.
This is fine. Thanks!
Segher
> Backport from mainline
> 2017-09-07 Carl Love
>
> * config/rs6000/vsx.md (define
patch is fine as far as I can see :-)
Segher
d-vec-unpack-pixel.c: New.
> * gcc.target/powerpc/fold-vec-unpack-short.c: New.
This looks fine. Okay for trunk. Thanks!
Segher
On Mon, Jul 09, 2018 at 02:08:55PM -0500, Will Schmidt wrote:
>Add support for early gimple folding of vec_perm. Testcases are already
> in-tree as
> gcc.target/powerpc/fold-vec-perm-*.c
>
> OK for trunk?
Looks fine to me. Okay if no one else complains :-)
Segher
>
> + {
> + arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
Indent here is wrong.
Segher
P7/P8 BE testing is underway.
> Is that backport okay if testing succeeds?
>
> [BTW, I'm shepherding this patch on behalf of Steve Munroe.]
This looks fine. Okay for trunk. Also okay for 8 (as we discussed, you
probably should check if 8 hasn't diverged from trunk here; it shouldn't
have).
Thanks to both of you,
Segher
ntation, so okay for trunk!
Thanks for working on this.
Segher
> * doc/extend.texi (PowerPC AltiVec Built-in Functions):
> Alphabetize prototypes of built-in functions, separating out
> built-in functions that are listed in this section but should be
> described elsewhere.
tions "-mlong-double-128" { target powerpc-ibm-aix* } }
> */
>
> along with testing for "tc", e.g., bl .__divtc3
Which would you prefer David? (I'd do the former).
Segher
On Fri, Jul 13, 2018 at 04:15:26PM -0700, Carl Love wrote:
> Segher, David:
>
> I reworked the patch per the first option that David gave. The tests
> divkc3-2.c, divkc3-3.c, mulkc3-2.c and mulkc3-3.c pass on Power 9 Linux
> as they did before. The tests are unsupported on Power
before power7 because that is not
supported).
Committing to trunk.
Segher
Segher Boessenkool (6):
rs6000: Use more correct names for some trunc/extend libcalls
rs6000: Use correct names for some trunc/extend libcalls
rs6000: Improve truncifsf2
rs6000: Fix testsuite bug in
The test program for ppc_float128_hw_available would always return
false, since there is a syntax error in that test program.
2018-07-16 Segher Boessenkool
gcc/testsuite/
* lib/target-supports.exp (check_ppc_float128_hw_available): Fix
syntax error.
---
gcc/testsuite/lib
The libcalls for trunc and extend of a decimal float to a binary float,
and vice versa, do not have "2" in the name, although all other such
conversions do.
2018-07-16 Segher Boessenkool
* config/rs6000/rs6000.c (init_float128_ibm): Use the correct names
for c
The current implementation leaves an unnecessary register move. It is
easier to just expand things in the expander already. This patch does
that.
2018-07-16 Segher Boessenkool
* config/rs6000/rs6000.md (truncsf2): Expand truncates of
double-double modes to SFmode directly
This introduces four new selectors for use with Power testcases:
longdouble64, ppc_float128, ppc_float128_insns, powerpc_vsx.
2018-07-16 Segher Boessenkool
gcc/testsuite/
* lib/target-supports.exp (check_effective_target_longdouble64,
check_effective_target_ppc_float128
They had source and destination swapped in the name.
2018-07-16 Segher Boessenkool
* config/rs6000/rs6000.c (init_float128_ibm): Use more correct names
for the conversions between TDmode and IFmode.
(init_float128_ieee): Use more correct names for the conversions
This tests the generated code for all conversions between floating point
point types, binary and decimal.
2018-07-16 Segher Boessenkool
gcc/testsuite/
* gcc.target/powerpc/convert-fp-128.c: New testcase.
* gcc.target/powerpc/convert-fp-64.c: New testcase.
---
gcc/testsuite
On Tue, Jul 17, 2018 at 01:34:18PM -0400, David Edelsohn wrote:
> And another test that needs to be restricted because it assumes 128
> bit long double.
Thanks :-)
Segher
to new subsubsections "PowerPC AltiVec Built-in Functions on ISA 2.06"
and "PowerPC AltiVec Built-in Functions on ISA 2.07".
(I.e., mention old name as well as new, and use imperative instead of
past tense).
Looks fine otherwise. Okay for trunk. Thanks!
Segher
e-unknown-linux-gnu (Power 8 LE)
> powerpc64-unknown-linux-gnu (Power 8 BE)
> AIX 7200-00-01-1543 (Power 8 BE)
>
> With no regressions.
>
> Please let me know if it is OK to apply the patch to the GCC 8 branch.
Sure, it's okay. Thanks!
Segher
> 2018-07
lear to me what this really stands for (not before the patch,
either).
Okay for trunk. Thanks! Please follow up to the above two things.
Segher
2
> && powerpc*-*-linux* } } } } */
Those "." are the dot in a regexp, i.e. they match any character.
You could do something like
/* { dg-final { scan-assembler-times {\mbl \.?__divdi3\M} 2 { target { ilp32
} } } } */
/* { dg-final { scan-assembler-times {\mbl \.?__udivdi3\M} 2 { target { ilp32
} } } } */
to handle both ABIs with and without dots.
But, current patch is okay for trunk as well. Thanks!
Segher
pieces.
This patch adds a splitter to make combine handle this case.
Tested on powerpc64-linux {-m32,-m64} and on powerpc64le-linux; committing.
Segher
2018-07-23 Segher Boessenkool
* config/rs6000/rs6000.md (splitters for rldimi and rlwimi with the
zero_extend argument
This changes vsx_init_v4si to be an expander. That way, no special
cases are needed anymore for special arguments: the normal RTL passes
can deal with it.
Tested as usual; committing.
Segher
2018-07-23 Segher Boessenkool
* config/rs6000/rs6000-p8swap.c (rtx_is_swappable_p
lting insns to be a
move instruction. But that is actually a very good thing to have, as
should have been obvious).
Tested for many months; tested on about 30 targets.
I'll commit this later this week if there are no objections.
Segher
2018-07-24 Segher Boessenkool
PR rtl-op
rc
> ;;
> +csky*-*-*)
> + cpu_type=csky
> + ;;
> arm*-*-*)
> cpu_type=arm
> ;;
This long list was alphabetic before (except x86_64 and tic6x, alas);
let's not make things worse?
Segher
On Tue, Jul 24, 2018 at 12:19:30PM -0600, Sandra Loosemore wrote:
> On 07/24/2018 12:10 PM, Segher Boessenkool wrote:
> >On Mon, Jul 23, 2018 at 10:26:35PM -0600, Sandra Loosemore wrote:
> >>diff --git a/libgcc/config.host b/libgcc/config.host
> >>index 18cabaf..b2ee
On Wed, Jul 25, 2018 at 10:28:30AM +0200, Richard Biener wrote:
> On Tue, Jul 24, 2018 at 7:18 PM Segher Boessenkool
> wrote:
> >
> > This patch allows combine to combine two insns into two. This helps
> > in many cases, by reducing instruction path length, and a
e
is_just_move (XVECEXP (newpat, 0, 0))
etc.; during most of combine you do not have instructions, just patterns.
Segher
value written to the DImode is not the same as that
written to the lowest-numbered QImode!
This patch fixes it. Committing. Will backport later, too.
Segher
2018-07-26 Segher Boessenkool
PR rtl-optimization/85805
* combine.c (reg_nonzero_bits_for_combine): Only use the last
On Thu, Jul 26, 2018 at 01:16:42PM +0200, Richard Biener wrote:
> On Thu, Jul 26, 2018 at 12:12 PM Segher Boessenkool
> wrote:
> >
> > The current code in reg_nonzero_bits_for_combine allows using the
> > reg_stat info when last_set_mode is a different integer mode. This
Looks good, thanks! Most (all?) of these functions are not documented
in the ABI, but this is a step forward anyway. Okay for trunk.
What do things like error messages involving these functions look like?
What types do those say?
Segher
and failure for excess errors. Fixed by calling the
> standard name.
>
> Verified the testcase now passes, ok for trunk?
I thought you pasted this strangely, but nope, the testcase is really
like that.
Okay for trunk and all branches. Thanks!
Segher
In arm_block_set_aligned_vect 8-bit constants are generated as zero-
extended const_ints, not sign-extended as required. Fix that.
Tamar tested the patch (see PR); no problems were found. Is this okay
for trunk?
Segher
2018-07-30 Segher Boessenkool
PR target/86640
Committing.
Segher
2018-07-30 Segher Boessenkool
gcc/testsuite/
PR rtl-optimization/85160
* gcc.target/powerpc/combine-2-2.c: New testcase.
---
gcc/testsuite/gcc.target/powerpc/combine-2-2.c | 17 +
1 file changed, 17 insertions(+)
create mode 100644 gcc
On Tue, Jul 24, 2018 at 05:18:41PM +, Segher Boessenkool wrote:
> This patch allows combine to combine two insns into two. This helps
> in many cases, by reducing instruction path length, and also allowing
> further combinations to happen. PR85160 is a typical example of code
>
On Mon, Jul 30, 2018 at 03:55:30PM +0100, Kyrill Tkachov wrote:
> Hi Segher,
>
> On 30/07/18 14:14, Segher Boessenkool wrote:
> >In arm_block_set_aligned_vect 8-bit constants are generated as zero-
> >extended const_ints, not sign-extended as required. Fix that.
> >
On Fri, Jul 27, 2018 at 10:07:20AM -0500, Kelvin Nilsen wrote:
> On 7/26/18 9:54 AM, Segher Boessenkool wrote:
> > On Thu, Jul 26, 2018 at 08:40:01AM -0500, Kelvin Nilsen wrote:
> >> To improve internal consistency and to improve consistency with published
> >> ABI doc
On Tue, Jul 31, 2018 at 09:02:56AM +0100, Kyrill Tkachov wrote:
> Hi Segher,
>
> On 30/07/18 18:37, Segher Boessenkool wrote:
> >On Mon, Jul 30, 2018 at 03:55:30PM +0100, Kyrill Tkachov wrote:
> >>Hi Segher,
> >>
> >>On 30/07/18 14:14, Segher Boessenkool
Hi Kyrill,
As before, untested. Is this okay for trunk, or will you handle it
yourself (or will someone else do it?)
Segher
2018-07-31 Segher Boessenkool
gcc/testsuite/
PR target/86640
* gcc.target/arm/pr86640.c: New testcase.
---
gcc/testsuite/gcc.target/arm/pr86640.c
, sorry. Richard says they look like
improvements, and exactly of the expected kind. :-)
Segher
%rip)
> vcvtps2pd f+16(%rip), %ymm0
> vmovaps %xmm0, d+32(%rip)
> vextractf128 $0x1, %ymm0, d+48(%rip)
> vcvtps2pd f+32(%rip), %ymm0
> vextractf128 $0x1, %ymm0, d+80(%rip)
> vmovaps %xmm0, d+64(%rip)
> vcvtps2pd f+48(%rip), %ymm0
> vextractf128 $0x1, %ymm0, d+112(%rip)
> vmovaps %xmm0, d+96(%rip)
> vzeroupper
> ret
> .cfi_endproc
I cannot really read AVX, but that looks like better code alright :-)
Segher
someone has tested it by now, too ;-)
Okay for trunk. Thanks!
Segher
> > * config/rs6000/rs6000.md (speculation_barrier): Renamed from
> > rs6000_speculation_barrier.
> > * config/rs6000/rs6000.c (rs6000_expand_builtin): Adjust for
> > new barrier pattern name.
On Wed, Aug 01, 2018 at 10:27:31AM +0200, Christophe Lyon wrote:
> On Tue, 31 Jul 2018 at 15:57, Segher Boessenkool
> wrote:
> > On Tue, Jul 31, 2018 at 02:34:06PM +0200, Christophe Lyon wrote:
> > > Since this was committed, I've noticed regressions
> >
quot;lwz", etc.)
> +# np -- enum non_prefixed_form for memory type
> +# constraint -- constraint to use
> +# mem_pred -- predicate for the memory operation
If you need a huge block comment for your sub argument, that is a
not-so-subtle hint that you need to refactor. Or if this was supposed
to be a refactoring, that something went terribly wrong :-(
Segher
e to use. For LWA, use the special LWA_OPERAND.
Explain *why*? It is obvious *what*!
Maybe just split the series into more patches?
> @@ -0,0 +1,26 @@
> +/* { dg-do assemble } */
> +/* { dg-require-effective-target lp64 } */
> +/* { dg-require-effective-target power10_ok } */
power10_ok should no longer exist, btw. Technical debt has to be
repaid :-/
This patch is readable btw. Thanks :-)
Segher
;words[0] == info->words[1]
> && info->words[0] == info->words[2]
> && info->words[0] == info->words[3]);
Thanks! Okay for trunk. Also okay for all backports, no need to wait
if unexpected problems in trunk show up. But still, backport to 13
first, then 12, then 11, only stop when it stops applying (or there are
no open release branches left) :-)
Segher
ot;s or "qw" for lists of constants.
2023-06-06 Segher Boessenkool
* config/rs6000/genfusion.pl (gen_ld_cmpi_p10_one): New, rewritten and
split out from...
(gen_ld_cmpi_p10): ... this.
---
gcc/config/rs6000/genfusion.pl | 185 +++
2023-06-06 Segher Boessenkool
* config/rs6000/genfusion.pl: Delete some dead code.
---
gcc/config/rs6000/genfusion.pl | 3 ---
1 file changed, 3 deletions(-)
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index 2851bb7..82e8f86 100755
--- a/gcc/config
uot;X - N * M" does
> not cross zero and does not wrap/overflow/underflow.
Is it ever valid semi-generally when N does not divide X?
Say X=5, N=2, M=3. Then the original expression evaluates to 0, but the
new one to -1. Whenever one of the divisions rounds up and the other
rounds down you have this problem.
Segher
r8 -mtune=power9 (this is a setting that is really used,
or was a few years ago anyway) you *do* want fmr insns generated.
So don't do this via the isa attribute at all, just add some insn
condition (testing the tune setting)?
Segher
>
> Thanks a lot for your quick review!! And sorry for the sending this patch
> in a hurry. I would update the patch accordingly.
> > This generally looks correct and consistent with other ports. I want
> > to give Segher a chance to double check it, if he wishes.
The doc
Dmode, p);
I have a hard time to see how this could ever be seen as clearer or more
obvious or anything like that :-(
Segher
will need to create a new
> target hook for const anchoring, this is the "complete rework" I meant.
This might make const anchor useful for way more targets maybe,
including rs6000, yes :-)
Segher
Hi!
On Wed, Jun 14, 2023 at 12:06:29PM +0800, Jiufu Guo wrote:
> Segher Boessenkool writes:
> I'm also thinking about other solutions:
> 1. "set (mem/c:BLK (reg/f:DI 1 1) (const_int 0 [0])"
> This is the existing pattern. It may be read as an action
> to clea
em:BLK (const_int 0))) (clobber all memory).
"clobber" is nicer than the set to (const_int 0). Does it work though?
All this code is always fragile :-/ I'm all for this change, don't get
me wrong, but preferably things stay in working order.
We use "stack_tie" as a last resort heavy hammer anyway, in all normal
cases we explain the actual data flow explicitly and correctly, also
between the various registers used in the *logues.
Segher
would still work, just would generate pretty lousy code. But
at least CSE and DSE (and everything else purely dataflow) would still
work :-)
Segher
up leads to hard to debug problems. Which
had happened time and time again over the years.
It just is hard to deal with variable sized stack adjustments and the
like. As long as we only use stack ties in such unusual cases, all is
fine. There are worse things, like what we have the
frame_pointer_needed_indeed thing for :-)
Segher
Some epilogue insns can do, of
course, but we expand to separate insns during expand already.
Segher
therwise) whereas a clobber
> can validly be dropped. So for something like stack_tie, a set
> seems more correct than a clobber.
No, the latter can be removed as well, under exactly the same
conditions: if no code after it reads what was written. This happens in
branches marked dead.
Segher
ce portable way to avoid needing this we haven't found
it yet -- or a non-portable way even, and it doesn't have to be all that
nice either come to think of it :-)
Segher
7;tie_operand' checks UNPSEC_TIE, then the insn
> with UNPSEC_TIE is 'a special insn'. Or interpret
> the semantic of this insn as: this insn stack_ite
> indicates "set/operate a zero size block".
tie_operand is a predicate. The predicate of an insn has to return 1,
or the insn is not recognised. You can do the same in insn conditions
always (in principle anyway).
Segher
eally shouldn't have -mpower9-minmax selectable independently of
-mcpu=power9, but that is a different thing.
Thanks,
Segher
you say that? Yes, we regressed some time ago, we
generate too many insns in many cases, but that is *bad*.
> /* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1692 { target ilp32 }
> } } */
> -/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1666 { target lp64 } }
> } */
> +/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1692 { target lp64 } }
> } */
This needs an explanation (and then the 32-bit and 64-bit checks can be
merged).
This probably needs changes after 4306339798b6 (if it is still wanted?)
Segher
is 100% true. We cannot simplify any MODE_CC comparison
without having more context. The combiner does have that context when
it tries to combine the CC setter with the CC consumer, for example.
Do you have some piece of motivating example code?
Segher
; in combination with my previous rs6000.md patch (with the obvious
> change of reload_completed to combine_completed) to confirm
> that it fixes the problems you were seeing.
>
> Segher/Richard, would this sort of patch be considered acceptable?
> Or is there a better approach/solution?
The
inal { scan-assembler "stc" } } */
This checks if the substring "stc" occurs anywhere in the generated
assembler code. More robust is to use scan-assembler-times, and to use
\mstc\M (same as \ in some other languages, or \bstc\b in Perl).
Segher
e "regular"
numbers. But this is too slow to test in normal testsuite runs :-)
It is wrong to pretend the current state makes the wanted code, these
testcases are meant to show exactly when we make suboptimal machine
code :-)
Segher
of generated insns:
/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 3 } } */
(three, not two, because of the blr insn at the end).
If possible, we should simply not do :TI ops on older systems at all,
and only on the newer systems that have instructions for it (and that
does not fix PR100694 btw, the problems there have to be solved, not
side-stepped :-( )
Segher
(vstril_code_): Rename to...
(vstril_internal_): ... this.
It often is a good idea to say "... for VIshort" and similar btw.
I'm not a fan of "internal" either, it doesn't say anything. At least
put it at the very end of the names please?
Okay for trunk with that changed. Thanks!
Segher
On Wed, Jul 13, 2022 at 04:14:11PM -0500, will schmidt wrote:
> On Wed, 2022-07-13 at 14:39 -0500, Segher Boessenkool wrote:
> > I'm not a fan of "internal" either, it doesn't say anything. At
> > least
> > put it at the very end of the names please?
&
SSOR_POWER10)
> rs6000_isa_flags |= OPTION_MASK_BLOCK_OPS_VECTOR_PAIR;
>else
> rs6000_isa_flags &= ~OPTION_MASK_BLOCK_OPS_VECTOR_PAIR;
The TARGET_MMA in that should not be there. Please fix that (that
probably needs more changes).
This statement does the opposite of what the comment says.
Please fix this. On trunk, first.
Segher
On Thu, Jul 14, 2022 at 05:49:57PM -0400, Michael Meissner wrote:
> On Thu, Jul 14, 2022 at 04:12:14PM -0500, Segher Boessenkool wrote:
> > You never posted the trunk version of this, so that never was approved
> > either.
>
> I did post the trunk version on June 10th, and
On Tue, Jul 19, 2022 at 03:14:52PM -0500, will schmidt wrote:
> This cleans up some of the naming around the vstrir and vstril
> instruction definitions, with some cosmetic changes for consistency.
Okay for trunk. Thanks!
Segher
gs like that. I suspect
you see it in other cases, and those are actual bugs then, that need
actual fixing instead of sweeping under the carper.
The testcase suggests this is with a compiler configured with
--with-cpu= --with-tune=, which should just work, and -mcpu= should
override both of those!
Segher
SK_BLOCK_OPS_VECTOR_PAIR;
> -}
How does this implement what the changelog says it does? With what it
does the changelog should instead say to not touch it at all (your patch
also disables the code that disables it!)
It isn't clear what you intended: what your changelog says, or what the
code does.
Segher
target_ppc_float128 { } {
> #ifndef __FLOAT128__
> nope no good
> #endif
> + int dummy;
At least put it in #else then? Or just do things a bit more elegantly
(do a dummy function around this for example).
Segher
Hi!
On Fri, Jul 22, 2022 at 08:41:43AM +0800, Kewen.Lin wrote:
> Hi Segher,
>
> Thanks for the comments!
Always.
> >> This patch is to fix empty TUs with one dummy variable definition
> >> accordingly.
> >
> > You can also use
> > enum{a};
> &
On Fri, Jul 22, 2022 at 10:22:51AM +0800, Kewen.Lin wrote:
> on 2022/7/22 02:48, Segher Boessenkool wrote:
> > On Wed, Jul 20, 2022 at 05:31:11PM +0800, Kewen.Lin wrote:
> >> As PR106345 shows, some test cases should be updated with
> >> -mdejagnu-tune, since their t
valid
since there is no way to know in what mode the comparison is to be
performed; the comparison must either be folded during the compilation
or the first operand must be loaded into a register while its mode is
still known.
Segher
rpc is target powerpc* always.
> +/* { dg-options "-O1 -mdejagnu-cpu=power10" } */
> +/* (high:DI (symbol_ref:DI ("var_48")..))) should not cause ICE. */
Ah, so there is an ICE, I see. Please open a PR, and mention that in
the testcase as well as in the commit message and changelog.
I agree with what the patch does, it just needs a little more work :-)
Segher
fore.
> If you don't believe that op0 and op1 can ever both be const_int
> in this function, perhaps consider it harmless dead code and humor
> me.
They can be, as clearly documented (and obvious from the code), but you
can not ever have that in the RTL stream, which is needed for your patch
to do anything.
I consider it harmful, and not dead. Sorry.
Do you have comments on the rest?
Segher
s PR106101. Unfortunately many targets violate this.
Segher
(GET_MODE (op), &op_mode)
> + && GET_MODE_PRECISION (int_mode) <= HOST_BITS_PER_WIDE_INT
> + && GET_MODE_PRECISION (op_mode) < GET_MODE_PRECISION (int_mode)
> + && (nonzero_bits (SUBREG_REG (op), mode)
> + & ~GET_MODE_MASK (op_mode)) == 0)
> + return SUBREG_REG (op);
This has that same problem.
Segher
+ (any_extend:TI
> + (match_operand:DI 3 "gpc_reg_operand" "r")))
> + 8))]
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(subreg:DI
(plus:TI
(mult:TI (any_extend:TI (match_operand:DI 1 "gpc_reg_operand" "r"))
(any_extend:TI (match_operand:DI 2 "gpc_reg_operand" "r")))
(any_extend:TI (match_operand:DI 3 "gpc_reg_operand" "r")))
8))]
(and similar for _le of course).
Segher
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