Hi!
On Fri, Jun 29, 2018 at 07:38:39AM -0700, Carl Love wrote:
> +;; Unpack high elements of float vector to vector of doubles
> +(define_expand "altivec_unpackh_v4sf"
> + [(set (match_operand:V2DF 0 "register_operand" "=v")
> + (match_operand:V4SF 1 "register_operand" "v"))]
> + "TARGET_VSX"
> +{
> + emit_insn (gen_doublehv4sf2 (operands[0], operands[1]));
> + DONE;
> +}
> + [(set_attr "type" "veccomplex")])
I wondered if these mactually work for all VSX registers, not just the VMX
registers (i.e. "wa" or similar instead of "v"). But constraints in
define_expand are meaningless anyway; just leave them out please.
Does it help to define these altivec_unpackh_v4sf, when all it does is
expand as doublehv4sf2? Can't you more easily put the latter in the tables?
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/altivec-1-runnable.c
> @@ -0,0 +1,257 @@
> +/* { dg-do compile { target powerpc*-*-* } } */
> +/* { dg-require-effective-target powerpc_altivec_ok } */
> +/* { dg-options "-mpower8-vector -maltivec" } */
This needs p8vector_ok then. Is that correct? What requires p8?
Is VSX (p7) enough for everything here?
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/altivec-2-runnable.c
> @@ -0,0 +1,94 @@
> +/* { dg-do compile { target powerpc*-*-* } } */
> +/* { dg-require-effective-target powerpc_altivec_ok } */
> +/* { dg-options "-mpower8-vector -mvsx" } */
Same here: required target does not match options.
Rest looks fine.
Segher
