From: Ju-Zhe Zhong
This patch adds sanity tests for basic enabling auto-vectorization.
We should make sure compiler enable auto-vectorization strictly according
to '-march'
For example, '-march=rv32gc_zve32x' can not allow INT64 auto-vectorization.
Since SEW = 64 RVV instructions are illegal ins
From: Ju-Zhe Zhong
PATCH 1: Add compile option for RVV auto-vectorization.
PATCH 2: Enable basic RVV auto-vectorization.
PATCH 3: Add sanity testcases.
*** BLURB HERE ***
Ju-Zhe Zhong (3):
RISC-V: Add auto-vectorization compile option for RVV
RISC-V: Enable basic auto-vectorization for RVV
c.md b/gcc/config/riscv/autovec.md
new file mode 100644
index 000..b5d46ff57ab
--- /dev/null
+++ b/gcc/config/riscv/autovec.md
@@ -0,0 +1,49 @@
+;; Machine description for auto-vectorization using RVV for GNU compiler.
+;; Copyright (C) 2023 Free Software Foundation, Inc.
+;; Contributed by J
From: Ju-Zhe Zhong
This patch is adding 2 compile option for RVV auto-vectorization.
1. -param=riscv-autovec-preference=
This option is to specify the auto-vectorization approach for RVV.
Currently, we only support scalable and fixed-vlmax.
- scalable means VLA auto-vectorization.
From: Ju-Zhe Zhong
This patch adds sanity tests for basic enabling auto-vectorization.
We should make sure compiler enable auto-vectorization strictly according
to '-march'
For example, '-march=rv32gc_zve32x' can not allow INT64 auto-vectorization.
Since SEW = 64 RVV instructions are illegal ins
From: Juzhe-Zhong
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (fold_fault_load): New
function.
(class vlseg): New class.
(class vsseg): Ditto.
(class vlsseg): Ditto.
(class vssseg): Ditto.
(class seg_indexed_load): Ditto
From: Juzhe-Zhong
PR 108270
Fix issue: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108270.
Consider the following testcase:
void f (void * restrict in, void * restrict out, int l, int n, int m)
{
for (int i = 0; i < l; i++){
for (int j = 0; j < m; j++){
for (int k
From: Juzhe-Zhong
PR 108270
Fix issue: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108270.
Consider the following testcase:
void f (void * restrict in, void * restrict out, int l, int n, int m)
{
for (int i = 0; i < l; i++){
for (int j = 0; j < m; j++){
for (int k
From: Juzhe-Zhong
Fix issue: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108270.
Consider the following testcase:
void f (void * restrict in, void * restrict out, int l, int n, int m)
{
for (int i = 0; i < l; i++){
for (int j = 0; j < m; j++){
for (int k = 0; k
From: Juzhe-Zhong
Fix issue: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108270.
Consider the following testcase:
void f (void * restrict in, void * restrict out, int l, int n, int m)
{
for (int i = 0; i < l; i++){
for (int j = 0; j < m; j++){
for (int k = 0; k
From: Juzhe-Zhong
V2 patch for:
https://patchwork.sourceware.org/project/gcc/patch/20230330012804.110539-1-juzhe.zh...@rivai.ai/
which has been reviewed.
This patch address Jeff's comment, refine ChangeLog to give more
clear information.
gcc/ChangeLog:
* config/riscv/v
From: Juzhe-Zhong
Address Jeff's comment:
https://patchwork.sourceware.org/project/gcc/patch/20230330012804.110539-1-juzhe.zh...@rivai.ai/
Add a function comment.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::pre_vsetvl): Add function
comment for cleanup_
From: Juzhe-Zhong
This patch is the V2
patch:https://patchwork.sourceware.org/project/gcc/patch/20230328010124.235703-1-juzhe.zh...@rivai.ai/
Address comments from Jeff. Add comments for all_avail_in_compatible_p and
refine comments of codes.
gcc/ChangeLog:
* config/riscv/riscv
From: Juzhe-Zhong
This patch is the V2
patch:https://patchwork.sourceware.org/project/gcc/patch/20230328010124.235703-1-juzhe.zh...@rivai.ai/
Address comments from Jeff. Add comments for all_avail_in_compatible_p and
refine comments of codes.
gcc/ChangeLog:
* config/riscv/riscv
From: Juzhe-Zhong
Hi, this is the most important patch for RVV auto-vectorization support.
It supports WHILE_LEN pattern to not only decrement Loop control IV counter,
but also adjust data reference address pointer by WHILE_LEN.
1. Single control loop (vec_num == 1 && ncopies == 1):
in
Jon Ziegler
Roman Zippel
Josef Zlomek
+Juzhe Zhong
Bug database only accounts
--
2.36.3
From: Juzhe-Zhong
This patch address all comments from Richard && Bernhard.
Fix all codes following their comments:
1. Remove ifn-specific handling of WHILE_LEN, so there is no change
in internal-fn.cc in this patch.
2. Add comments for changing interface of "create_iv&
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/vector.md: Refine vmadc/vmsbc RA constraint.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/narrow_constraint-13.c: New test.
* gcc.target/riscv/rvv/base/narrow_constraint-14.c: New test.
* gcc.target/riscv/
From: Juzhe-Zhong
This patch is fix patch of V2:
https://patchwork.sourceware.org/project/gcc/patch/20230419164214.1032017-3-juzhe.zh...@rivai.ai/.
Address comments from Kito && Robin, and fix issues && add testcases for them.
gcc/ChangeLog:
* config/risc
From: Ju-Zhe Zhong
This patch is fixing V3 patch:
https://patchwork.sourceware.org/project/gcc/patch/20230407014741.139387-1-juzhe.zh...@rivai.ai/
Fix issues according to Richard Sandiford && Richard Biener.
1. Rename WHILE_LEN pattern into SELECT_VL according to Richard Sandiford.
2. Support m
From: Juzhe-Zhong
Before this patch:
...
.L2:
addia4,a1,100
add t1,a0,a2
mv t0,a0
beq a2,zero,.L1
vsetvli zero,a3,e8,mf8,tu,mu
.L4:
addia6,t0,100
addia7,a4,-100
vle8.v v1,0(t0)
addit0,t0,1
From: Juzhe-Zhong
This patch is to fix following case:
void f (int8_t * restrict in, int8_t * restrict out, int n, int m, int cond)
{
size_t vl = 101;
if (cond)
vl = m * 2;
else
vl = m * 2 * vl;
for (size_t i = 0; i < n; i++)
{
vint8mf8_t v = __riscv_vle8_v_i8mf8
From: Juzhe-Zhong
This patch is fixing my recent optimization patch:
https://github.com/gcc-mirror/gcc/commit/d51f2456ee51bd59a79b4725ca0e488c25260bbf
In that patch, the new_info = parse_insn (i) is not correct.
Since consider the following case:
vsetvli a5,a4, e8,m1
..
vsetvli zero,a5
From: Juzhe-Zhong
This patch is depending on
https://patchwork.sourceware.org/project/gcc/patch/20230504054544.203366-1-juzhe.zh...@rivai.ai/
Fix codes according to comments of Kito.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_get_arg_info): Move RVV type argument
handling outside
From: Juzhe-Zhong
This patch is fixing my recent optimization patch:
https://github.com/gcc-mirror/gcc/commit/d51f2456ee51bd59a79b4725ca0e488c25260bbf
In that patch, the new_info = parse_insn (i) is not correct.
Since consider the following case:
vsetvli a5,a4, e8,m1
..
vsetvli zero,a5
From: Juzhe-Zhong
Address comments from Robin.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (preferred_simd_mode): Fix comments.
* config/riscv/riscv.cc (riscv_get_arg_info): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c: Fix function name
From: Juzhe-Zhong
gcc/ChangeLog:
* config/riscv/riscv-protos.h (preferred_simd_mode): New function.
* config/riscv/riscv-v.cc (autovec_use_vlmax_p): Ditto.
(preferred_simd_mode): Ditto.
* config/riscv/riscv.cc (riscv_get_arg_info): Handle RVV type in
function
From: Juzhe-Zhong
gcc/ChangeLog:
* config/riscv/riscv-protos.h (preferred_simd_mode): New function.
* config/riscv/riscv-v.cc (autovec_use_vlmax_p): Ditto.
(preferred_simd_mode): Ditto.
* config/riscv/riscv.cc (riscv_get_arg_info): Handle RVV type in
function
From: Juzhe-Zhong
gcc/ChangeLog:
* config/riscv/riscv-protos.h (preferred_simd_mode): New function.
* config/riscv/riscv-v.cc (autovec_use_vlmax_p): Ditto.
(preferred_simd_mode): Ditto.
* config/riscv/riscv.cc (riscv_get_arg_info): Handle RVV type in
function
From: Juzhe-Zhong
This patch is fixing: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109743.
This issue happens is because we are currently very conservative in
optimization of user vsetvli.
Consider this following case:
bb 1:
vsetvli a5,a4... (demand AVL = a4).
bb 2:
RVV insn use a5
From: Juzhe-Zhong
1. Add movmisalign pattern for TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
targethook, current RISC-V has supported this target hook, we can't make
it supported without movmisalign pattern.
2. Remove global extern of get_mask_policy_no_pred && get_tail_p
From: Juzhe-Zhong
This patch is fixing: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109743.
This issue happens is because we are currently very conservative in
optimization of user vsetvli.
Consider this following case:
bb 1:
vsetvli a5,a4... (demand AVL = a4).
bb 2:
RVV insn use a5
From: Juzhe-Zhong
Rebase to trunk and send V3 patch for:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617821.html
This patch is fixing: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109743.
This issue happens is because we are currently very conservative in
optimization of user vsetvli
From: Juzhe-Zhong
This patch is fix dead loop in vsetvl intrinsic avl checking.
vsetvli->get_def () has vsetvli->get_def () has vsetvli.
Then it will keep looping in the vsetvli avl checking which is a dead loop.
PR target/109773
gcc/ChangeLog:
* config/riscv
From: Juzhe-Zhong
This incorrect codes blocks the scalable RVV auto-vectorization.
Take a look at this target hook implementation of aarch64.
They only have the similiar handling on TARGET_SIMD.
They let movmisalign to handle scalable vector of SVE.
For RVV, we should follow the same
From: Juzhe-Zhong
This incorrect codes blocks the scalable RVV auto-vectorization.
Take a look at this target hook implementation of aarch64.
They only have the similiar handling on TARGET_SIMD.
They let movmisalign to handle scalable vector of SVE.
For RVV, we should follow the same
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c: Fix testcase check.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vsetvl-18.c: Ditto.
---
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_mul
From: Ju-Zhe Zhong
---
gcc/config/riscv/vector.md | 20
1 file changed, 20 deletions(-)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 8c60eb20d72..4319266974d 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -208,26 +2
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/predicates.md (pmode_reg_or_0_operand): New predicate.
* config/riscv/riscv-vector-builtins-bases.cc (class loadstore):
Support vlse/vsse.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-protos.h (get_vector_mode): New function.
* config/riscv/riscv-v.cc (get_vector_mode): Ditto.
* config/riscv/riscv-vector-builtins-bases.cc (enum lst_type): New enum.
(class loadstore): Adjust for indexed load
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/avl_single-72.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-76.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-77.c: New test.
---
.../riscv/rvv/vsetvl/avl_single-72.c | 27
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vlxei-vsxei-constraint-1.c: New test.
---
.../riscv/rvv/base/vlxei-vsxei-constraint-1.c | 121 ++
1 file changed, 121 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/vlxei
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vsoxei16-1.C: New test.
* g++.target/riscv/rvv/base/vsoxei16-2.C: New test.
* g++.target/riscv/rvv/base/vsoxei16-3.C: New test.
* g++.target/riscv/rvv/base/vsoxei8-1.C: New test.
* g++
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vsoxei32-1.C: New test.
* g++.target/riscv/rvv/base/vsoxei32-2.C: New test.
* g++.target/riscv/rvv/base/vsoxei32-3.C: New test.
* g++.target/riscv/rvv/base/vsoxei64-1.C: New test.
* g+
From: Ju-Zhe Zhong
---
gcc/config/riscv/constraints.md | 10 +
gcc/config/riscv/iterators.md | 14 +-
gcc/config/riscv/predicates.md| 15 ++
.../riscv/riscv-vector-builtins-bases.cc | 48 +
.../riscv/riscv-vector-builtins-bases.h |
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vsrl_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vsrl_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vsrl_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vsrl_vv_m-1.c: New test.
* gcc.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vsra_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vsra_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vsra_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vsra_vv_m-1.c: New test.
* gcc.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/binop_vv_constraint-1.c: New test.
---
.../riscv/rvv/base/binop_vv_constraint-1.c| 132 ++
1 file changed, 132 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vsrl_vv-1.C: New test.
* g++.target/riscv/rvv/base/vsrl_vv-2.C: New test.
* g++.target/riscv/rvv/base/vsrl_vv-3.C: New test.
* g++.target/riscv/rvv/base/vsrl_vv_mu-1.C: New test.
* g++
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vsra_vv-1.C: New test.
* g++.target/riscv/rvv/base/vsra_vv-2.C: New test.
* g++.target/riscv/rvv/base/vsra_vv-3.C: New test.
* g++.target/riscv/rvv/base/vsra_vv_mu-1.C: New test.
* g++
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/predicates.md (pmode_reg_or_uimm5_operand): New
predicate.
* config/riscv/riscv-vector-builtins-bases.cc: New class.
* config/riscv/riscv-vector-builtins-functions.def (vsll): Ditto.
(vsra): Ditto.
(vsrl):
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vsrl_vx-1.c: New test.
* gcc.target/riscv/rvv/base/vsrl_vx-2.c: New test.
* gcc.target/riscv/rvv/base/vsrl_vx-3.c: New test.
* gcc.target/riscv/rvv/base/vsrl_vx_m-1.c: New test.
* gcc.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vsra_vx-1.c: New test.
* gcc.target/riscv/rvv/base/vsra_vx-2.c: New test.
* gcc.target/riscv/rvv/base/vsra_vx-3.c: New test.
* gcc.target/riscv/rvv/base/vsra_vx_m-1.c: New test.
* gcc.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: New test.
---
.../riscv/rvv/base/shift_vx_constraint-1.c| 133 ++
1 file changed, 133 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vsrl_vx-1.C: New test.
* g++.target/riscv/rvv/base/vsrl_vx-2.C: New test.
* g++.target/riscv/rvv/base/vsrl_vx-3.C: New test.
* g++.target/riscv/rvv/base/vsrl_vx_mu-1.C: New test.
* g++
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vsra_vx-1.C: New test.
* g++.target/riscv/rvv/base/vsra_vx-2.C: New test.
* g++.target/riscv/rvv/base/vsra_vx-3.C: New test.
* g++.target/riscv/rvv/base/vsra_vx_mu-1.C: New test.
* g++
From: Ju-Zhe Zhong
Current constraint configuration will generate:
vadd.vv v0,v24,v25,v0.t
vsll.vx v0,v24,a5,v0.t
They are incorrect according to RVV ISA.
This patch fix this obvious issue.
gcc/ChangeLog:
* config/riscv/vector-iterators.md (sll.vi): Fix constraint bug.
(sll.vv)
From: Ju-Zhe Zhong
Hi, this patch is present for GCC 14 since I understand it's not appropriate
to land it in GCC 13.
NUM_FIXED_BLOCKS = 2 since GCC define each function has aleast 2 blocks
one is entry block, the other is exit block.
So according this code, the function will not do cprop optimi
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/constraints.md (Wdm): Adjust constraint.
(Wbr): New constraint.
* config/riscv/predicates.md (reg_or_int_operand): New predicate.
* config/riscv/riscv-protos.h (emit_pred_op): Remove function.
(emit_vlmax_op
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/iterators.md: Add neg and not.
* config/riscv/riscv-vector-builtins-bases.cc (class unop): New class.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vnot_v-1.c: New test.
* gcc.target/riscv/rvv/base/vnot_v-2.c: New test.
* gcc.target/riscv/rvv/base/vnot_v-3.c: New test.
* gcc.target/riscv/rvv/base/vnot_v_m-1.c: New test.
* gcc.targ
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vneg_v-1.c: New test.
* gcc.target/riscv/rvv/base/vneg_v-2.c: New test.
* gcc.target/riscv/rvv/base/vneg_v-3.c: New test.
* gcc.target/riscv/rvv/base/vneg_v_m-1.c: New test.
* gcc.targ
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/unop_v_constraint-1.c: New test.
---
.../riscv/rvv/base/unop_v_constraint-1.c | 132 ++
1 file changed, 132 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_con
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vnot_v-1.C: New test.
* g++.target/riscv/rvv/base/vnot_v-2.C: New test.
* g++.target/riscv/rvv/base/vnot_v-3.C: New test.
* g++.target/riscv/rvv/base/vnot_v_mu-1.C: New test.
* g++.tar
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vneg_v-1.C: New test.
* g++.target/riscv/rvv/base/vneg_v-2.C: New test.
* g++.target/riscv/rvv/base/vneg_v-3.C: New test.
* g++.target/riscv/rvv/base/vneg_v_mu-1.C: New test.
* g++.tar
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::compute_probabilities):
Skip exit block.
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/exception-1.C: New test.
---
gcc/config/riscv/riscv-vsetvl.cc | 10 +--
.../g++.targe
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/iterators.md: Add saturating Addition && Subtraction.
* config/riscv/riscv-v.cc (has_vi_variant_p): Ditto.
* config/riscv/riscv-vector-builtins-bases.cc (BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h:
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/binop_vx_constraint-100.c: New test.
* gcc.target/riscv/rvv/base/binop_vx_constraint-101.c: New test.
* gcc.target/riscv/rvv/base/binop_vx_constraint-102.c: New test.
* gcc.target/riscv/rvv/ba
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vsadd_vv-1.C: New test.
* g++.target/riscv/rvv/base/vsadd_vv-2.C: New test.
* g++.target/riscv/rvv/base/vsadd_vv-3.C: New test.
* g++.target/riscv/rvv/base/vsadd_vv_mu-1.C: New test.
*
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vsaddu_vv-1.C: New test.
* g++.target/riscv/rvv/base/vsaddu_vv-2.C: New test.
* g++.target/riscv/rvv/base/vsaddu_vv-3.C: New test.
* g++.target/riscv/rvv/base/vsaddu_vv_mu-1.C: New test.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vssub_vv-1.C: New test.
* g++.target/riscv/rvv/base/vssub_vv-2.C: New test.
* g++.target/riscv/rvv/base/vssub_vv-3.C: New test.
* g++.target/riscv/rvv/base/vssub_vv_mu-1.C: New test.
*
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vssubu_vv-1.C: New test.
* g++.target/riscv/rvv/base/vssubu_vv-2.C: New test.
* g++.target/riscv/rvv/base/vssubu_vv-3.C: New test.
* g++.target/riscv/rvv/base/vssubu_vv_mu-1.C: New test.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vssubu_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vssubu_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vssubu_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vssubu_vv_m-1.c: New test.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vssub_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vssub_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vssub_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vssub_vv_m-1.c: New test.
*
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vsaddu_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vsaddu_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vsaddu_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vsaddu_vv_m-1.c: New test.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vsadd_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vsadd_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vsadd_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vsadd_vv_m-1.c: New test.
*
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/iterators.md: Add sign_extend/zero_extend.
* config/riscv/riscv-vector-builtins-bases.cc (class ext): New class.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Add vsext/vzext support.
* config
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vzext_vf8-1.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf8-2.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf8-3.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf8_m-1.c: New test.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vzext_vf4-1.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf4-2.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf4-3.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf4_m-1.c: New test.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vzext_vf2-1.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf2-2.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf2-3.c: New test.
* gcc.target/riscv/rvv/base/vzext_vf2_m-1.c: New test.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vsext_vf8-1.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf8-2.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf8-3.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf8_m-1.c: New test.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vsext_vf4-1.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf4-2.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf4-3.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf4_m-1.c: New test.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vsext_vf2-1.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf2-2.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf2-3.c: New test.
* gcc.target/riscv/rvv/base/vsext_vf2_m-1.c: New test.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/unop_v_constraint-2.c: New test.
---
.../riscv/rvv/base/unop_v_constraint-2.c | 132 ++
1 file changed, 132 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_con
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vzext_vf8-1.C: New test.
* g++.target/riscv/rvv/base/vzext_vf8-2.C: New test.
* g++.target/riscv/rvv/base/vzext_vf8-3.C: New test.
* g++.target/riscv/rvv/base/vzext_vf8_mu-1.C: New test.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vzext_vf4-1.C: New test.
* g++.target/riscv/rvv/base/vzext_vf4-2.C: New test.
* g++.target/riscv/rvv/base/vzext_vf4-3.C: New test.
* g++.target/riscv/rvv/base/vzext_vf4_mu-1.C: New test.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vzext_vf2-1.C: New test.
* g++.target/riscv/rvv/base/vzext_vf2-2.C: New test.
* g++.target/riscv/rvv/base/vzext_vf2-3.C: New test.
* g++.target/riscv/rvv/base/vzext_vf2_mu-1.C: New test.
From: Ju-Zhe Zhong
Co-authored-by: kito-cheng
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add flag for 'V' extension.
* config/riscv/riscv-vector-builtins-bases.cc (class vmulh): New class.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: D
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vmulhu_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vmulhu_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vmulhu_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vmulhu_vv_m-1.c: New test.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vmulhsu_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vmulhsu_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vmulhsu_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vmulhsu_vv_m-1.c: New test.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vmulh_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vmulh_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vmulh_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vmulh_vv_m-1.c: New test.
*
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vmulhsu_vv-1.C: New test.
* g++.target/riscv/rvv/base/vmulhsu_vv-2.C: New test.
* g++.target/riscv/rvv/base/vmulhsu_vv-3.C: New test.
* g++.target/riscv/rvv/base/vmulhsu_vv_mu-1.C: New test.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vmulh_vv-1.C: New test.
* g++.target/riscv/rvv/base/vmulh_vv-2.C: New test.
* g++.target/riscv/rvv/base/vmulh_vv-3.C: New test.
* g++.target/riscv/rvv/base/vmulh_vv_mu-1.C: New test.
*
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (class widen_binop): New
class.
(class vwmulsu): Ditto.
(class vwcvt): Ditto.
(BASE): Add integer widening support.
* config/riscv/riscv-vector-builtins-bases.h: Ditto
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vwsubu_wx-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wx-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wx-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wx_m-1.c: New test.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vwsubu_wv-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_m-1.c: New test.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vwsubu_vx-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vx-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vx-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vx_m-1.c: New test.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vwsubu_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vv_m-1.c: New test.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vwsub_wx-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wx-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wx-3.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wx_m-1.c: New test.
*
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vwsub_wv-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wv-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wv-3.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wv_m-1.c: New test.
*
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