From: Ju-Zhe Zhong <juzhe.zh...@rivai.ai>
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vsaddu_vv-1.C: New test.
* g++.target/riscv/rvv/base/vsaddu_vv-2.C: New test.
* g++.target/riscv/rvv/base/vsaddu_vv-3.C: New test.
* g++.target/riscv/rvv/base/vsaddu_vv_mu-1.C: New test.
* g++.target/riscv/rvv/base/vsaddu_vv_mu-2.C: New test.
* g++.target/riscv/rvv/base/vsaddu_vv_mu-3.C: New test.
* g++.target/riscv/rvv/base/vsaddu_vv_tu-1.C: New test.
* g++.target/riscv/rvv/base/vsaddu_vv_tu-2.C: New test.
* g++.target/riscv/rvv/base/vsaddu_vv_tu-3.C: New test.
* g++.target/riscv/rvv/base/vsaddu_vv_tum-1.C: New test.
* g++.target/riscv/rvv/base/vsaddu_vv_tum-2.C: New test.
* g++.target/riscv/rvv/base/vsaddu_vv_tum-3.C: New test.
* g++.target/riscv/rvv/base/vsaddu_vv_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vsaddu_vv_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vsaddu_vv_tumu-3.C: New test.
---
.../g++.target/riscv/rvv/base/vsaddu_vv-1.C | 314 ++++++++++++++++++
.../g++.target/riscv/rvv/base/vsaddu_vv-2.C | 314 ++++++++++++++++++
.../g++.target/riscv/rvv/base/vsaddu_vv-3.C | 314 ++++++++++++++++++
.../riscv/rvv/base/vsaddu_vv_mu-1.C | 160 +++++++++
.../riscv/rvv/base/vsaddu_vv_mu-2.C | 160 +++++++++
.../riscv/rvv/base/vsaddu_vv_mu-3.C | 160 +++++++++
.../riscv/rvv/base/vsaddu_vv_tu-1.C | 160 +++++++++
.../riscv/rvv/base/vsaddu_vv_tu-2.C | 160 +++++++++
.../riscv/rvv/base/vsaddu_vv_tu-3.C | 160 +++++++++
.../riscv/rvv/base/vsaddu_vv_tum-1.C | 160 +++++++++
.../riscv/rvv/base/vsaddu_vv_tum-2.C | 160 +++++++++
.../riscv/rvv/base/vsaddu_vv_tum-3.C | 160 +++++++++
.../riscv/rvv/base/vsaddu_vv_tumu-1.C | 160 +++++++++
.../riscv/rvv/base/vsaddu_vv_tumu-2.C | 160 +++++++++
.../riscv/rvv/base/vsaddu_vv_tumu-3.C | 160 +++++++++
15 files changed, 2862 insertions(+)
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_mu-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_mu-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_mu-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tu-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tu-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tu-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tum-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tum-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tum-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tumu-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tumu-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tumu-3.C
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv-1.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv-1.C
new file mode 100644
index 00000000000..91e0dd7710b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv-1.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vsaddu(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsaddu(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsaddu(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsaddu(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsaddu(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsaddu(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsaddu(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsaddu(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsaddu(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsaddu(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsaddu(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsaddu(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsaddu(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsaddu(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsaddu(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsaddu(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsaddu(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsaddu(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsaddu(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsaddu(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsaddu(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsaddu(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vsaddu(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsaddu(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsaddu(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsaddu(vbool8_t mask,vuint8m1_t op1,vuint8m1_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsaddu(vbool4_t mask,vuint8m2_t op1,vuint8m2_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsaddu(vbool2_t mask,vuint8m4_t op1,vuint8m4_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsaddu(vbool1_t mask,vuint8m8_t op1,vuint8m8_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsaddu(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsaddu(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsaddu(vbool16_t mask,vuint16m1_t op1,vuint16m1_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsaddu(vbool8_t mask,vuint16m2_t op1,vuint16m2_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsaddu(vbool4_t mask,vuint16m4_t op1,vuint16m4_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsaddu(vbool2_t mask,vuint16m8_t op1,vuint16m8_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsaddu(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsaddu(vbool32_t mask,vuint32m1_t op1,vuint32m1_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsaddu(vbool16_t mask,vuint32m2_t op1,vuint32m2_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsaddu(vbool8_t mask,vuint32m4_t op1,vuint32m4_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsaddu(vbool4_t mask,vuint32m8_t op1,vuint32m8_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsaddu(vbool64_t mask,vuint64m1_t op1,vuint64m1_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsaddu(vbool32_t mask,vuint64m2_t op1,vuint64m2_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsaddu(vbool16_t mask,vuint64m4_t op1,vuint64m4_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsaddu(vbool8_t mask,vuint64m8_t op1,vuint64m8_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv-2.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv-2.C
new file mode 100644
index 00000000000..b2ead9c566e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv-2.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vsaddu(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsaddu(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsaddu(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsaddu(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsaddu(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsaddu(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsaddu(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsaddu(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsaddu(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsaddu(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsaddu(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsaddu(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsaddu(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsaddu(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsaddu(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsaddu(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsaddu(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsaddu(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsaddu(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsaddu(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsaddu(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsaddu(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vsaddu(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsaddu(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsaddu(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsaddu(vbool8_t mask,vuint8m1_t op1,vuint8m1_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsaddu(vbool4_t mask,vuint8m2_t op1,vuint8m2_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsaddu(vbool2_t mask,vuint8m4_t op1,vuint8m4_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsaddu(vbool1_t mask,vuint8m8_t op1,vuint8m8_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsaddu(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsaddu(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsaddu(vbool16_t mask,vuint16m1_t op1,vuint16m1_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsaddu(vbool8_t mask,vuint16m2_t op1,vuint16m2_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsaddu(vbool4_t mask,vuint16m4_t op1,vuint16m4_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsaddu(vbool2_t mask,vuint16m8_t op1,vuint16m8_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsaddu(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsaddu(vbool32_t mask,vuint32m1_t op1,vuint32m1_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsaddu(vbool16_t mask,vuint32m2_t op1,vuint32m2_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsaddu(vbool8_t mask,vuint32m4_t op1,vuint32m4_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsaddu(vbool4_t mask,vuint32m8_t op1,vuint32m8_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsaddu(vbool64_t mask,vuint64m1_t op1,vuint64m1_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsaddu(vbool32_t mask,vuint64m2_t op1,vuint64m2_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsaddu(vbool16_t mask,vuint64m4_t op1,vuint64m4_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsaddu(vbool8_t mask,vuint64m8_t op1,vuint64m8_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv-3.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv-3.C
new file mode 100644
index 00000000000..db39e2e2320
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv-3.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vsaddu(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsaddu(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsaddu(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsaddu(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsaddu(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsaddu(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsaddu(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsaddu(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsaddu(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsaddu(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsaddu(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsaddu(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsaddu(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsaddu(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsaddu(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsaddu(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsaddu(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsaddu(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsaddu(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsaddu(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsaddu(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsaddu(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu(op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vsaddu(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsaddu(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsaddu(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsaddu(vbool8_t mask,vuint8m1_t op1,vuint8m1_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsaddu(vbool4_t mask,vuint8m2_t op1,vuint8m2_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsaddu(vbool2_t mask,vuint8m4_t op1,vuint8m4_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsaddu(vbool1_t mask,vuint8m8_t op1,vuint8m8_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsaddu(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsaddu(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsaddu(vbool16_t mask,vuint16m1_t op1,vuint16m1_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsaddu(vbool8_t mask,vuint16m2_t op1,vuint16m2_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsaddu(vbool4_t mask,vuint16m4_t op1,vuint16m4_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsaddu(vbool2_t mask,vuint16m8_t op1,vuint16m8_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsaddu(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsaddu(vbool32_t mask,vuint32m1_t op1,vuint32m1_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsaddu(vbool16_t mask,vuint32m2_t op1,vuint32m2_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsaddu(vbool8_t mask,vuint32m4_t op1,vuint32m4_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsaddu(vbool4_t mask,vuint32m8_t op1,vuint32m8_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsaddu(vbool64_t mask,vuint64m1_t op1,vuint64m1_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsaddu(vbool32_t mask,vuint64m2_t op1,vuint64m2_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsaddu(vbool16_t mask,vuint64m4_t op1,vuint64m4_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsaddu(vbool8_t mask,vuint64m8_t op1,vuint64m8_t
op2,size_t vl)
+{
+ return __riscv_vsaddu(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_mu-1.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_mu-1.C
new file mode 100644
index 00000000000..29b36bf1ef7
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_mu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vsaddu_mu(vbool64_t mask,vuint8mf8_t
merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsaddu_mu(vbool32_t mask,vuint8mf4_t
merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsaddu_mu(vbool16_t mask,vuint8mf2_t
merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsaddu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t
op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsaddu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t
op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsaddu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t
op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsaddu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t
op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsaddu_mu(vbool64_t mask,vuint16mf4_t
merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsaddu_mu(vbool32_t mask,vuint16mf2_t
merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsaddu_mu(vbool16_t mask,vuint16m1_t
merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsaddu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t
op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsaddu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t
op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsaddu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t
op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsaddu_mu(vbool64_t mask,vuint32mf2_t
merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsaddu_mu(vbool32_t mask,vuint32m1_t
merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsaddu_mu(vbool16_t mask,vuint32m2_t
merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsaddu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t
op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsaddu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t
op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsaddu_mu(vbool64_t mask,vuint64m1_t
merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsaddu_mu(vbool32_t mask,vuint64m2_t
merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsaddu_mu(vbool16_t mask,vuint64m4_t
merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsaddu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t
op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_mu-2.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_mu-2.C
new file mode 100644
index 00000000000..fc6d1f987a2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_mu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vsaddu_mu(vbool64_t mask,vuint8mf8_t
merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsaddu_mu(vbool32_t mask,vuint8mf4_t
merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsaddu_mu(vbool16_t mask,vuint8mf2_t
merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsaddu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t
op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsaddu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t
op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsaddu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t
op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsaddu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t
op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsaddu_mu(vbool64_t mask,vuint16mf4_t
merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsaddu_mu(vbool32_t mask,vuint16mf2_t
merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsaddu_mu(vbool16_t mask,vuint16m1_t
merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsaddu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t
op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsaddu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t
op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsaddu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t
op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsaddu_mu(vbool64_t mask,vuint32mf2_t
merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsaddu_mu(vbool32_t mask,vuint32m1_t
merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsaddu_mu(vbool16_t mask,vuint32m2_t
merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsaddu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t
op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsaddu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t
op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsaddu_mu(vbool64_t mask,vuint64m1_t
merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsaddu_mu(vbool32_t mask,vuint64m2_t
merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsaddu_mu(vbool16_t mask,vuint64m4_t
merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsaddu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t
op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_mu-3.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_mu-3.C
new file mode 100644
index 00000000000..1e6d875c5f4
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_mu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vsaddu_mu(vbool64_t mask,vuint8mf8_t
merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsaddu_mu(vbool32_t mask,vuint8mf4_t
merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsaddu_mu(vbool16_t mask,vuint8mf2_t
merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsaddu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t
op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsaddu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t
op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsaddu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t
op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsaddu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t
op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsaddu_mu(vbool64_t mask,vuint16mf4_t
merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsaddu_mu(vbool32_t mask,vuint16mf2_t
merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsaddu_mu(vbool16_t mask,vuint16m1_t
merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsaddu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t
op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsaddu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t
op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsaddu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t
op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsaddu_mu(vbool64_t mask,vuint32mf2_t
merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsaddu_mu(vbool32_t mask,vuint32m1_t
merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsaddu_mu(vbool16_t mask,vuint32m2_t
merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsaddu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t
op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsaddu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t
op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsaddu_mu(vbool64_t mask,vuint64m1_t
merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsaddu_mu(vbool32_t mask,vuint64m2_t
merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsaddu_mu(vbool16_t mask,vuint64m4_t
merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsaddu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t
op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tu-1.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tu-1.C
new file mode 100644
index 00000000000..75206ab5312
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vsaddu_tu(vuint8mf8_t merge,vuint8mf8_t
op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsaddu_tu(vuint8mf4_t merge,vuint8mf4_t
op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsaddu_tu(vuint8mf2_t merge,vuint8mf2_t
op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsaddu_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t
op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsaddu_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t
op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsaddu_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t
op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsaddu_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t
op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsaddu_tu(vuint16mf4_t merge,vuint16mf4_t
op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsaddu_tu(vuint16mf2_t merge,vuint16mf2_t
op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsaddu_tu(vuint16m1_t merge,vuint16m1_t
op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsaddu_tu(vuint16m2_t merge,vuint16m2_t
op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsaddu_tu(vuint16m4_t merge,vuint16m4_t
op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsaddu_tu(vuint16m8_t merge,vuint16m8_t
op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsaddu_tu(vuint32mf2_t merge,vuint32mf2_t
op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsaddu_tu(vuint32m1_t merge,vuint32m1_t
op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsaddu_tu(vuint32m2_t merge,vuint32m2_t
op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsaddu_tu(vuint32m4_t merge,vuint32m4_t
op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsaddu_tu(vuint32m8_t merge,vuint32m8_t
op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsaddu_tu(vuint64m1_t merge,vuint64m1_t
op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsaddu_tu(vuint64m2_t merge,vuint64m2_t
op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsaddu_tu(vuint64m4_t merge,vuint64m4_t
op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsaddu_tu(vuint64m8_t merge,vuint64m8_t
op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tu-2.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tu-2.C
new file mode 100644
index 00000000000..075176a52ba
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vsaddu_tu(vuint8mf8_t merge,vuint8mf8_t
op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsaddu_tu(vuint8mf4_t merge,vuint8mf4_t
op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsaddu_tu(vuint8mf2_t merge,vuint8mf2_t
op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsaddu_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t
op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsaddu_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t
op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsaddu_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t
op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsaddu_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t
op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsaddu_tu(vuint16mf4_t merge,vuint16mf4_t
op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsaddu_tu(vuint16mf2_t merge,vuint16mf2_t
op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsaddu_tu(vuint16m1_t merge,vuint16m1_t
op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsaddu_tu(vuint16m2_t merge,vuint16m2_t
op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsaddu_tu(vuint16m4_t merge,vuint16m4_t
op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsaddu_tu(vuint16m8_t merge,vuint16m8_t
op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsaddu_tu(vuint32mf2_t merge,vuint32mf2_t
op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsaddu_tu(vuint32m1_t merge,vuint32m1_t
op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsaddu_tu(vuint32m2_t merge,vuint32m2_t
op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsaddu_tu(vuint32m4_t merge,vuint32m4_t
op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsaddu_tu(vuint32m8_t merge,vuint32m8_t
op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsaddu_tu(vuint64m1_t merge,vuint64m1_t
op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsaddu_tu(vuint64m2_t merge,vuint64m2_t
op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsaddu_tu(vuint64m4_t merge,vuint64m4_t
op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsaddu_tu(vuint64m8_t merge,vuint64m8_t
op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tu-3.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tu-3.C
new file mode 100644
index 00000000000..74067020fbb
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vsaddu_tu(vuint8mf8_t merge,vuint8mf8_t
op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsaddu_tu(vuint8mf4_t merge,vuint8mf4_t
op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsaddu_tu(vuint8mf2_t merge,vuint8mf2_t
op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsaddu_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t
op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsaddu_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t
op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsaddu_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t
op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsaddu_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t
op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsaddu_tu(vuint16mf4_t merge,vuint16mf4_t
op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsaddu_tu(vuint16mf2_t merge,vuint16mf2_t
op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsaddu_tu(vuint16m1_t merge,vuint16m1_t
op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsaddu_tu(vuint16m2_t merge,vuint16m2_t
op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsaddu_tu(vuint16m4_t merge,vuint16m4_t
op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsaddu_tu(vuint16m8_t merge,vuint16m8_t
op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsaddu_tu(vuint32mf2_t merge,vuint32mf2_t
op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsaddu_tu(vuint32m1_t merge,vuint32m1_t
op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsaddu_tu(vuint32m2_t merge,vuint32m2_t
op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsaddu_tu(vuint32m4_t merge,vuint32m4_t
op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsaddu_tu(vuint32m8_t merge,vuint32m8_t
op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsaddu_tu(vuint64m1_t merge,vuint64m1_t
op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsaddu_tu(vuint64m2_t merge,vuint64m2_t
op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsaddu_tu(vuint64m4_t merge,vuint64m4_t
op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsaddu_tu(vuint64m8_t merge,vuint64m8_t
op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tum-1.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tum-1.C
new file mode 100644
index 00000000000..9d1d5dc490b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tum-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vsaddu_tum(vbool64_t mask,vuint8mf8_t
merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsaddu_tum(vbool32_t mask,vuint8mf4_t
merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsaddu_tum(vbool16_t mask,vuint8mf2_t
merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsaddu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t
op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsaddu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t
op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsaddu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t
op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsaddu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t
op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsaddu_tum(vbool64_t mask,vuint16mf4_t
merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsaddu_tum(vbool32_t mask,vuint16mf2_t
merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsaddu_tum(vbool16_t mask,vuint16m1_t
merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsaddu_tum(vbool8_t mask,vuint16m2_t
merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsaddu_tum(vbool4_t mask,vuint16m4_t
merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsaddu_tum(vbool2_t mask,vuint16m8_t
merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsaddu_tum(vbool64_t mask,vuint32mf2_t
merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsaddu_tum(vbool32_t mask,vuint32m1_t
merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsaddu_tum(vbool16_t mask,vuint32m2_t
merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsaddu_tum(vbool8_t mask,vuint32m4_t
merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsaddu_tum(vbool4_t mask,vuint32m8_t
merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsaddu_tum(vbool64_t mask,vuint64m1_t
merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsaddu_tum(vbool32_t mask,vuint64m2_t
merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsaddu_tum(vbool16_t mask,vuint64m4_t
merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsaddu_tum(vbool8_t mask,vuint64m8_t
merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tum-2.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tum-2.C
new file mode 100644
index 00000000000..209c9b37c81
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tum-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vsaddu_tum(vbool64_t mask,vuint8mf8_t
merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsaddu_tum(vbool32_t mask,vuint8mf4_t
merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsaddu_tum(vbool16_t mask,vuint8mf2_t
merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsaddu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t
op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsaddu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t
op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsaddu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t
op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsaddu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t
op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsaddu_tum(vbool64_t mask,vuint16mf4_t
merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsaddu_tum(vbool32_t mask,vuint16mf2_t
merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsaddu_tum(vbool16_t mask,vuint16m1_t
merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsaddu_tum(vbool8_t mask,vuint16m2_t
merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsaddu_tum(vbool4_t mask,vuint16m4_t
merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsaddu_tum(vbool2_t mask,vuint16m8_t
merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsaddu_tum(vbool64_t mask,vuint32mf2_t
merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsaddu_tum(vbool32_t mask,vuint32m1_t
merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsaddu_tum(vbool16_t mask,vuint32m2_t
merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsaddu_tum(vbool8_t mask,vuint32m4_t
merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsaddu_tum(vbool4_t mask,vuint32m8_t
merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsaddu_tum(vbool64_t mask,vuint64m1_t
merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsaddu_tum(vbool32_t mask,vuint64m2_t
merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsaddu_tum(vbool16_t mask,vuint64m4_t
merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsaddu_tum(vbool8_t mask,vuint64m8_t
merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tum-3.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tum-3.C
new file mode 100644
index 00000000000..bd307c1bb9e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tum-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vsaddu_tum(vbool64_t mask,vuint8mf8_t
merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsaddu_tum(vbool32_t mask,vuint8mf4_t
merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsaddu_tum(vbool16_t mask,vuint8mf2_t
merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsaddu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t
op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsaddu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t
op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsaddu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t
op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsaddu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t
op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsaddu_tum(vbool64_t mask,vuint16mf4_t
merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsaddu_tum(vbool32_t mask,vuint16mf2_t
merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsaddu_tum(vbool16_t mask,vuint16m1_t
merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsaddu_tum(vbool8_t mask,vuint16m2_t
merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsaddu_tum(vbool4_t mask,vuint16m4_t
merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsaddu_tum(vbool2_t mask,vuint16m8_t
merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsaddu_tum(vbool64_t mask,vuint32mf2_t
merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsaddu_tum(vbool32_t mask,vuint32m1_t
merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsaddu_tum(vbool16_t mask,vuint32m2_t
merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsaddu_tum(vbool8_t mask,vuint32m4_t
merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsaddu_tum(vbool4_t mask,vuint32m8_t
merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsaddu_tum(vbool64_t mask,vuint64m1_t
merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsaddu_tum(vbool32_t mask,vuint64m2_t
merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsaddu_tum(vbool16_t mask,vuint64m4_t
merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsaddu_tum(vbool8_t mask,vuint64m8_t
merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tumu-1.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tumu-1.C
new file mode 100644
index 00000000000..7bd1286ddcc
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tumu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vsaddu_tumu(vbool64_t mask,vuint8mf8_t
merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsaddu_tumu(vbool32_t mask,vuint8mf4_t
merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsaddu_tumu(vbool16_t mask,vuint8mf2_t
merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsaddu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t
op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsaddu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t
op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsaddu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t
op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsaddu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t
op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsaddu_tumu(vbool64_t mask,vuint16mf4_t
merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsaddu_tumu(vbool32_t mask,vuint16mf2_t
merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsaddu_tumu(vbool16_t mask,vuint16m1_t
merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsaddu_tumu(vbool8_t mask,vuint16m2_t
merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsaddu_tumu(vbool4_t mask,vuint16m4_t
merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsaddu_tumu(vbool2_t mask,vuint16m8_t
merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsaddu_tumu(vbool64_t mask,vuint32mf2_t
merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsaddu_tumu(vbool32_t mask,vuint32m1_t
merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsaddu_tumu(vbool16_t mask,vuint32m2_t
merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsaddu_tumu(vbool8_t mask,vuint32m4_t
merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsaddu_tumu(vbool4_t mask,vuint32m8_t
merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsaddu_tumu(vbool64_t mask,vuint64m1_t
merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsaddu_tumu(vbool32_t mask,vuint64m2_t
merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsaddu_tumu(vbool16_t mask,vuint64m4_t
merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsaddu_tumu(vbool8_t mask,vuint64m8_t
merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tumu-2.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tumu-2.C
new file mode 100644
index 00000000000..9d7f5ed5e37
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tumu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vsaddu_tumu(vbool64_t mask,vuint8mf8_t
merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsaddu_tumu(vbool32_t mask,vuint8mf4_t
merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsaddu_tumu(vbool16_t mask,vuint8mf2_t
merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsaddu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t
op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsaddu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t
op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsaddu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t
op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsaddu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t
op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsaddu_tumu(vbool64_t mask,vuint16mf4_t
merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsaddu_tumu(vbool32_t mask,vuint16mf2_t
merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsaddu_tumu(vbool16_t mask,vuint16m1_t
merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsaddu_tumu(vbool8_t mask,vuint16m2_t
merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsaddu_tumu(vbool4_t mask,vuint16m4_t
merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsaddu_tumu(vbool2_t mask,vuint16m8_t
merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsaddu_tumu(vbool64_t mask,vuint32mf2_t
merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsaddu_tumu(vbool32_t mask,vuint32m1_t
merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsaddu_tumu(vbool16_t mask,vuint32m2_t
merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsaddu_tumu(vbool8_t mask,vuint32m4_t
merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsaddu_tumu(vbool4_t mask,vuint32m8_t
merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsaddu_tumu(vbool64_t mask,vuint64m1_t
merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsaddu_tumu(vbool32_t mask,vuint64m2_t
merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsaddu_tumu(vbool16_t mask,vuint64m4_t
merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsaddu_tumu(vbool8_t mask,vuint64m8_t
merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tumu-3.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tumu-3.C
new file mode 100644
index 00000000000..b6342c7722c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tumu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vsaddu_tumu(vbool64_t mask,vuint8mf8_t
merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsaddu_tumu(vbool32_t mask,vuint8mf4_t
merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsaddu_tumu(vbool16_t mask,vuint8mf2_t
merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsaddu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t
op1,vuint8m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsaddu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t
op1,vuint8m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsaddu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t
op1,vuint8m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsaddu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t
op1,vuint8m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsaddu_tumu(vbool64_t mask,vuint16mf4_t
merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsaddu_tumu(vbool32_t mask,vuint16mf2_t
merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsaddu_tumu(vbool16_t mask,vuint16m1_t
merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsaddu_tumu(vbool8_t mask,vuint16m2_t
merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsaddu_tumu(vbool4_t mask,vuint16m4_t
merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsaddu_tumu(vbool2_t mask,vuint16m8_t
merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsaddu_tumu(vbool64_t mask,vuint32mf2_t
merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsaddu_tumu(vbool32_t mask,vuint32m1_t
merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsaddu_tumu(vbool16_t mask,vuint32m2_t
merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsaddu_tumu(vbool8_t mask,vuint32m4_t
merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsaddu_tumu(vbool4_t mask,vuint32m8_t
merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsaddu_tumu(vbool64_t mask,vuint64m1_t
merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsaddu_tumu(vbool32_t mask,vuint64m2_t
merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsaddu_tumu(vbool16_t mask,vuint64m4_t
merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsaddu_tumu(vbool8_t mask,vuint64m8_t
merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+ return __riscv_vsaddu_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
1 } } */
--
2.36.1
