[PATCH] RISC-V: Add vsub.vv C++ API tests

[juzhe . zhong]

From: Ju-Zhe Zhong <juzhe.zh...@rivai.ai>

gcc/testsuite/ChangeLog:

        * g++.target/riscv/rvv/base/vssub_vv-1.C: New test.
        * g++.target/riscv/rvv/base/vssub_vv-2.C: New test.
        * g++.target/riscv/rvv/base/vssub_vv-3.C: New test.
        * g++.target/riscv/rvv/base/vssub_vv_mu-1.C: New test.
        * g++.target/riscv/rvv/base/vssub_vv_mu-2.C: New test.
        * g++.target/riscv/rvv/base/vssub_vv_mu-3.C: New test.
        * g++.target/riscv/rvv/base/vssub_vv_tu-1.C: New test.
        * g++.target/riscv/rvv/base/vssub_vv_tu-2.C: New test.
        * g++.target/riscv/rvv/base/vssub_vv_tu-3.C: New test.
        * g++.target/riscv/rvv/base/vssub_vv_tum-1.C: New test.
        * g++.target/riscv/rvv/base/vssub_vv_tum-2.C: New test.
        * g++.target/riscv/rvv/base/vssub_vv_tum-3.C: New test.
        * g++.target/riscv/rvv/base/vssub_vv_tumu-1.C: New test.
        * g++.target/riscv/rvv/base/vssub_vv_tumu-2.C: New test.
        * g++.target/riscv/rvv/base/vssub_vv_tumu-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vssub_vv-1.C    | 314 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vssub_vv-2.C    | 314 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vssub_vv-3.C    | 314 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vssub_vv_mu-1.C | 160 +++++++++
 .../g++.target/riscv/rvv/base/vssub_vv_mu-2.C | 160 +++++++++
 .../g++.target/riscv/rvv/base/vssub_vv_mu-3.C | 160 +++++++++
 .../g++.target/riscv/rvv/base/vssub_vv_tu-1.C | 160 +++++++++
 .../g++.target/riscv/rvv/base/vssub_vv_tu-2.C | 160 +++++++++
 .../g++.target/riscv/rvv/base/vssub_vv_tu-3.C | 160 +++++++++
 .../riscv/rvv/base/vssub_vv_tum-1.C           | 160 +++++++++
 .../riscv/rvv/base/vssub_vv_tum-2.C           | 160 +++++++++
 .../riscv/rvv/base/vssub_vv_tum-3.C           | 160 +++++++++
 .../riscv/rvv/base/vssub_vv_tumu-1.C          | 160 +++++++++
 .../riscv/rvv/base/vssub_vv_tumu-2.C          | 160 +++++++++
 .../riscv/rvv/base/vssub_vv_tumu-3.C          | 160 +++++++++
 15 files changed, 2862 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tumu-3.C

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv-1.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv-1.C
new file mode 100644
index 00000000000..dddc6e2b578
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv-1.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssub(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vssub(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vssub(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vssub(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vssub(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vssub(vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vssub(vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vssub(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vssub(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vssub(vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vssub(vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vssub(vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vssub(vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vssub(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vssub(vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vssub(vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vssub(vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vssub(vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vssub(vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vssub(vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vssub(vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vssub(vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,vl);
+}
+
+
+vint8mf8_t test___riscv_vssub(vbool64_t mask,vint8mf8_t op1,vint8mf8_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vssub(vbool32_t mask,vint8mf4_t op1,vint8mf4_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vssub(vbool16_t mask,vint8mf2_t op1,vint8mf2_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vssub(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t 
vl)
+{
+    return __riscv_vssub(mask,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vssub(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t 
vl)
+{
+    return __riscv_vssub(mask,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vssub(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t 
vl)
+{
+    return __riscv_vssub(mask,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vssub(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t 
vl)
+{
+    return __riscv_vssub(mask,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vssub(vbool64_t mask,vint16mf4_t op1,vint16mf4_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vssub(vbool32_t mask,vint16mf2_t op1,vint16mf2_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vssub(vbool16_t mask,vint16m1_t op1,vint16m1_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vssub(vbool8_t mask,vint16m2_t op1,vint16m2_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vssub(vbool4_t mask,vint16m4_t op1,vint16m4_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vssub(vbool2_t mask,vint16m8_t op1,vint16m8_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vssub(vbool64_t mask,vint32mf2_t op1,vint32mf2_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vssub(vbool32_t mask,vint32m1_t op1,vint32m1_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vssub(vbool16_t mask,vint32m2_t op1,vint32m2_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vssub(vbool8_t mask,vint32m4_t op1,vint32m4_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vssub(vbool4_t mask,vint32m8_t op1,vint32m8_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vssub(vbool64_t mask,vint64m1_t op1,vint64m1_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vssub(vbool32_t mask,vint64m2_t op1,vint64m2_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vssub(vbool16_t mask,vint64m4_t op1,vint64m4_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vssub(vbool8_t mask,vint64m8_t op1,vint64m8_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv-2.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv-2.C
new file mode 100644
index 00000000000..2ef1b533e22
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv-2.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssub(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vssub(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vssub(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vssub(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vssub(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vssub(vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vssub(vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vssub(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vssub(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vssub(vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vssub(vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vssub(vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vssub(vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vssub(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vssub(vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vssub(vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vssub(vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vssub(vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vssub(vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vssub(vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vssub(vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vssub(vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,31);
+}
+
+
+vint8mf8_t test___riscv_vssub(vbool64_t mask,vint8mf8_t op1,vint8mf8_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vssub(vbool32_t mask,vint8mf4_t op1,vint8mf4_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vssub(vbool16_t mask,vint8mf2_t op1,vint8mf2_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vssub(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t 
vl)
+{
+    return __riscv_vssub(mask,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vssub(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t 
vl)
+{
+    return __riscv_vssub(mask,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vssub(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t 
vl)
+{
+    return __riscv_vssub(mask,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vssub(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t 
vl)
+{
+    return __riscv_vssub(mask,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vssub(vbool64_t mask,vint16mf4_t op1,vint16mf4_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vssub(vbool32_t mask,vint16mf2_t op1,vint16mf2_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vssub(vbool16_t mask,vint16m1_t op1,vint16m1_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vssub(vbool8_t mask,vint16m2_t op1,vint16m2_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vssub(vbool4_t mask,vint16m4_t op1,vint16m4_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vssub(vbool2_t mask,vint16m8_t op1,vint16m8_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vssub(vbool64_t mask,vint32mf2_t op1,vint32mf2_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vssub(vbool32_t mask,vint32m1_t op1,vint32m1_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vssub(vbool16_t mask,vint32m2_t op1,vint32m2_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vssub(vbool8_t mask,vint32m4_t op1,vint32m4_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vssub(vbool4_t mask,vint32m8_t op1,vint32m8_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vssub(vbool64_t mask,vint64m1_t op1,vint64m1_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vssub(vbool32_t mask,vint64m2_t op1,vint64m2_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vssub(vbool16_t mask,vint64m4_t op1,vint64m4_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vssub(vbool8_t mask,vint64m8_t op1,vint64m8_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv-3.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv-3.C
new file mode 100644
index 00000000000..ce19718c19e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv-3.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssub(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vssub(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vssub(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vssub(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vssub(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vssub(vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vssub(vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vssub(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vssub(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vssub(vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vssub(vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vssub(vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vssub(vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vssub(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vssub(vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vssub(vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vssub(vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vssub(vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vssub(vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vssub(vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vssub(vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vssub(vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vssub(op1,op2,32);
+}
+
+
+vint8mf8_t test___riscv_vssub(vbool64_t mask,vint8mf8_t op1,vint8mf8_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vssub(vbool32_t mask,vint8mf4_t op1,vint8mf4_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vssub(vbool16_t mask,vint8mf2_t op1,vint8mf2_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vssub(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t 
vl)
+{
+    return __riscv_vssub(mask,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vssub(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t 
vl)
+{
+    return __riscv_vssub(mask,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vssub(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t 
vl)
+{
+    return __riscv_vssub(mask,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vssub(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t 
vl)
+{
+    return __riscv_vssub(mask,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vssub(vbool64_t mask,vint16mf4_t op1,vint16mf4_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vssub(vbool32_t mask,vint16mf2_t op1,vint16mf2_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vssub(vbool16_t mask,vint16m1_t op1,vint16m1_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vssub(vbool8_t mask,vint16m2_t op1,vint16m2_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vssub(vbool4_t mask,vint16m4_t op1,vint16m4_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vssub(vbool2_t mask,vint16m8_t op1,vint16m8_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vssub(vbool64_t mask,vint32mf2_t op1,vint32mf2_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vssub(vbool32_t mask,vint32m1_t op1,vint32m1_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vssub(vbool16_t mask,vint32m2_t op1,vint32m2_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vssub(vbool8_t mask,vint32m4_t op1,vint32m4_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vssub(vbool4_t mask,vint32m8_t op1,vint32m8_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vssub(vbool64_t mask,vint64m1_t op1,vint64m1_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vssub(vbool32_t mask,vint64m2_t op1,vint64m2_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vssub(vbool16_t mask,vint64m4_t op1,vint64m4_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vssub(vbool8_t mask,vint64m8_t op1,vint64m8_t 
op2,size_t vl)
+{
+    return __riscv_vssub(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_mu-1.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_mu-1.C
new file mode 100644
index 00000000000..3f28d1221f1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_mu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t 
op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vssub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t 
op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vssub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t 
op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vssub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t 
op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vssub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t 
op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vssub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t 
op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vssub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t 
op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vssub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t 
op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vssub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t 
op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vssub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t 
op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vssub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t 
op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vssub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t 
op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vssub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t 
op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vssub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t 
op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vssub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t 
op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vssub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t 
op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vssub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t 
op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vssub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t 
op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vssub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t 
op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vssub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t 
op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vssub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t 
op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vssub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t 
op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_mu-2.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_mu-2.C
new file mode 100644
index 00000000000..7feb2d527f3
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_mu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t 
op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vssub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t 
op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vssub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t 
op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vssub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t 
op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vssub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t 
op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vssub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t 
op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vssub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t 
op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vssub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t 
op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vssub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t 
op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vssub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t 
op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vssub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t 
op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vssub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t 
op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vssub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t 
op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vssub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t 
op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vssub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t 
op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vssub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t 
op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vssub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t 
op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vssub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t 
op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vssub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t 
op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vssub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t 
op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vssub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t 
op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vssub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t 
op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_mu-3.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_mu-3.C
new file mode 100644
index 00000000000..5f1fb2667f6
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_mu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t 
op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vssub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t 
op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vssub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t 
op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vssub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t 
op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vssub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t 
op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vssub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t 
op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vssub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t 
op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vssub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t 
op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vssub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t 
op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vssub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t 
op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vssub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t 
op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vssub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t 
op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vssub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t 
op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vssub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t 
op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vssub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t 
op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vssub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t 
op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vssub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t 
op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vssub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t 
op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vssub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t 
op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vssub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t 
op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vssub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t 
op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vssub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t 
op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vssub_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tu-1.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tu-1.C
new file mode 100644
index 00000000000..243e0b0da0d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssub_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vssub_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vssub_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vssub_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vssub_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vssub_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vssub_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vssub_tu(vint16mf4_t merge,vint16mf4_t 
op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vssub_tu(vint16mf2_t merge,vint16mf2_t 
op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vssub_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vssub_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vssub_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vssub_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vssub_tu(vint32mf2_t merge,vint32mf2_t 
op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vssub_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vssub_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vssub_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vssub_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vssub_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vssub_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vssub_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vssub_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tu-2.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tu-2.C
new file mode 100644
index 00000000000..d8778ccdcc1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssub_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vssub_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vssub_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vssub_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vssub_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vssub_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vssub_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vssub_tu(vint16mf4_t merge,vint16mf4_t 
op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vssub_tu(vint16mf2_t merge,vint16mf2_t 
op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vssub_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vssub_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vssub_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vssub_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vssub_tu(vint32mf2_t merge,vint32mf2_t 
op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vssub_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vssub_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vssub_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vssub_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vssub_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vssub_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vssub_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vssub_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tu-3.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tu-3.C
new file mode 100644
index 00000000000..d47a3a106a9
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssub_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vssub_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vssub_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vssub_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vssub_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vssub_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vssub_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vssub_tu(vint16mf4_t merge,vint16mf4_t 
op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vssub_tu(vint16mf2_t merge,vint16mf2_t 
op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vssub_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vssub_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vssub_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vssub_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vssub_tu(vint32mf2_t merge,vint32mf2_t 
op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vssub_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vssub_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vssub_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vssub_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vssub_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vssub_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vssub_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vssub_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t 
op2,size_t vl)
+{
+    return __riscv_vssub_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tum-1.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tum-1.C
new file mode 100644
index 00000000000..19fc4c3215b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tum-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t 
op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vssub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t 
op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vssub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t 
op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vssub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t 
op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vssub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t 
op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vssub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t 
op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vssub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t 
op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vssub_tum(vbool64_t mask,vint16mf4_t 
merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vssub_tum(vbool32_t mask,vint16mf2_t 
merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vssub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t 
op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vssub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t 
op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vssub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t 
op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vssub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t 
op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vssub_tum(vbool64_t mask,vint32mf2_t 
merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vssub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t 
op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vssub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t 
op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vssub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t 
op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vssub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t 
op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vssub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t 
op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vssub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t 
op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vssub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t 
op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vssub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t 
op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tum-2.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tum-2.C
new file mode 100644
index 00000000000..21dc75064db
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tum-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t 
op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vssub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t 
op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vssub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t 
op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vssub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t 
op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vssub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t 
op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vssub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t 
op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vssub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t 
op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vssub_tum(vbool64_t mask,vint16mf4_t 
merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vssub_tum(vbool32_t mask,vint16mf2_t 
merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vssub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t 
op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vssub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t 
op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vssub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t 
op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vssub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t 
op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vssub_tum(vbool64_t mask,vint32mf2_t 
merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vssub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t 
op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vssub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t 
op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vssub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t 
op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vssub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t 
op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vssub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t 
op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vssub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t 
op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vssub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t 
op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vssub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t 
op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tum-3.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tum-3.C
new file mode 100644
index 00000000000..2e0f61f9a9b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tum-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t 
op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vssub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t 
op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vssub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t 
op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vssub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t 
op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vssub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t 
op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vssub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t 
op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vssub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t 
op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vssub_tum(vbool64_t mask,vint16mf4_t 
merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vssub_tum(vbool32_t mask,vint16mf2_t 
merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vssub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t 
op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vssub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t 
op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vssub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t 
op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vssub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t 
op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vssub_tum(vbool64_t mask,vint32mf2_t 
merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vssub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t 
op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vssub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t 
op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vssub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t 
op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vssub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t 
op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vssub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t 
op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vssub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t 
op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vssub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t 
op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vssub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t 
op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vssub_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tumu-1.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tumu-1.C
new file mode 100644
index 00000000000..8581219d51c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tumu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t 
op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vssub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t 
op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vssub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t 
op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vssub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t 
op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vssub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t 
op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vssub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t 
op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vssub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t 
op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vssub_tumu(vbool64_t mask,vint16mf4_t 
merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vssub_tumu(vbool32_t mask,vint16mf2_t 
merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vssub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t 
op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vssub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t 
op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vssub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t 
op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vssub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t 
op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vssub_tumu(vbool64_t mask,vint32mf2_t 
merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vssub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t 
op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vssub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t 
op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vssub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t 
op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vssub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t 
op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vssub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t 
op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vssub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t 
op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vssub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t 
op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vssub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t 
op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tumu-2.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tumu-2.C
new file mode 100644
index 00000000000..d13ccc6bd28
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tumu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t 
op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vssub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t 
op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vssub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t 
op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vssub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t 
op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vssub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t 
op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vssub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t 
op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vssub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t 
op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vssub_tumu(vbool64_t mask,vint16mf4_t 
merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vssub_tumu(vbool32_t mask,vint16mf2_t 
merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vssub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t 
op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vssub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t 
op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vssub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t 
op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vssub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t 
op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vssub_tumu(vbool64_t mask,vint32mf2_t 
merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vssub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t 
op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vssub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t 
op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vssub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t 
op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vssub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t 
op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vssub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t 
op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vssub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t 
op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vssub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t 
op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vssub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t 
op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tumu-3.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tumu-3.C
new file mode 100644
index 00000000000..3107229b510
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tumu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t 
op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vssub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t 
op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vssub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t 
op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vssub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t 
op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vssub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t 
op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vssub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t 
op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vssub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t 
op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vssub_tumu(vbool64_t mask,vint16mf4_t 
merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vssub_tumu(vbool32_t mask,vint16mf2_t 
merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vssub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t 
op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vssub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t 
op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vssub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t 
op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vssub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t 
op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vssub_tumu(vbool64_t mask,vint32mf2_t 
merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vssub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t 
op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vssub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t 
op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vssub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t 
op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vssub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t 
op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vssub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t 
op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vssub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t 
op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vssub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t 
op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vssub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t 
op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vssub_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+}
 1 } } */
-- 
2.36.1