在 2025/3/16 3:54, Jeff Law 写道:
On 3/14/25 2:29 PM, Vineet Gupta wrote:
Hi,
On 12/3/24 03:02, Jiawei wrote:
This patch series introduces support for RISC-V Profiles RV20, RV22[1],
and RV23[2][3].The updates enhance compatibility and streamline the
process
of leveraging RISC-V Profiles
This patch introduces support for RISC-V Profiles RV20 and RV22 [1],
enabling developers to utilize these profiles through the -march option.
[1] https://github.com/riscv/riscv-profiles/releases/tag/v1.0
Version log:
Using lowercase letters to present Profiles.
Using '_' as divsor between Profile
This patch introduces support for RISC-V Profiles RV23A and RV23B [1],
enabling developers to utilize these profiles through the -march option.
[1]
https://github.com/riscv/riscv-profiles/releases/tag/rva23-rvb23-v0.7-ratification-vote
Version log:
Update the testcases, using lowercase letter.
.
Jiawei (2):
RISC-V: Support RISC-V Profiles 20/22.
RISC-V: Support RISC-V Profiles 23.
gcc/common/config/riscv/riscv-common.cc | 91 +++-
gcc/config/riscv/riscv-subset.h | 2 +
gcc/testsuite/gcc.target/riscv/arch-45.c | 5 ++
gcc/testsuite/gcc.target/riscv/arch-46.c
在 2024/12/15 23:50, Jeff Law 写道:
On 12/3/24 4:02 AM, Jiawei wrote:
This patch introduces support for RISC-V Profiles RV20 and RV22 [1],
enabling developers to utilize these profiles through the -march option.
[1] https://github.com/riscv/riscv-profiles/releases/tag/v1.0
gcc/ChangeLog
From: Liao Shihua
Update Sifive Xsfvqmacc and Xsfvfnrclip extension's testcases.
version log:
Update synchronize LMUL settings with return type.
gcc/ChangeLog:
* config/riscv/vector.md: New attr set.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/xsfvector/sf_vfnrcli
Update implementation of Xsfvfnrclip, using return type as iterator.
gcc/ChangeLog:
* config/riscv/genrvv-type-indexer.cc (expand_floattype): New func.
(main): New type.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_XFQF_OPS): New
def.
(vint8mf8_t): Ditt
From: Liao Shihua
---
gcc/config/riscv/vector.md| 7 ++-
.../riscv/rvv/xsfvector/sf_vfnrclip_x_f_qf.c | 60 ++
.../riscv/rvv/xsfvector/sf_vfnrclip_xu_f_qf.c | 63 ++-
.../riscv/rvv/xsfvector/sf_vqmacc_2x8x2.c | 16 +
.../riscv/rvv/xsf
gcc/ChangeLog:
* config/riscv/genrvv-type-indexer.cc (expand_floattype): New func.
(main):
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_XFQF_OPS):
(vint8mf8_t):
(vint8mf4_t):
(vint8mf2_t):
(vint8m1_t):
(vint8m2_t):
pliant systems
introduces significant maintenance burdens and risks diluting the
clarity of the standard. Instead, allowing such issues to result in
crashes might serve to emphasize the importance of compliance with
RVA22/23 requirements.
Do you have any suggestions or thoughts on how we shou
This patch introduces support for RISC-V Profiles RV23A and RV23B [1],
enabling developers to utilize these profiles through the -march option.
[1]
https://github.com/riscv/riscv-profiles/releases/tag/rva23-rvb23-v0.7-ratification-vote
gcc/ChangeLog:
* common/config/riscv/riscv-common.c
This patch introduces support for RISC-V Profiles RV20 and RV22 [1],
enabling developers to utilize these profiles through the -march option.
[1] https://github.com/riscv/riscv-profiles/releases/tag/v1.0
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (struct riscv_profiles): New
s
/
Jiawei (2):
RISC-V: Support RISC-V Profiles RV20/22.
RISC-V: Support RISC-V Profiles RVA/B23.
gcc/common/config/riscv/riscv-common.cc | 91 +++-
gcc/config/riscv/riscv-subset.h | 2 +
gcc/testsuite/gcc.target/riscv/arch-45.c | 5 ++
gcc/testsuite/gcc.target
CC_HOST_HOOKS_H */ />/-- />/2.45.2 />
Thanks, committed into trunk.
Jiawei
definition, different cores need to be configured with
corresponding tuning in `riscv-cores.def`, so we can reuse the core name
in '-mtune' option.
BR,
Jiawei
在 2024/8/21 3:23, Palmer Dabbelt 写道:
On Mon, 19 Aug 2024 21:53:54 PDT (-0700), jia...@iscas.ac.cn wrote:
Supports RISC-V profiles[1] in -march option.
Default input set the profile before other formal extensions.
V2: Fixes some format errors and adds code comments for parse function
Thanks f
Supports RISC-V profiles[1] in -march option.
Default input set the profile before other formal extensions.
V2: Fixes some format errors and adds code comments for parse function
Thanks for Jeff Law's review and comments.
V3: Update testcases and profiles extensions support.Remove S/M mode Profi
---
gcc/common/config/riscv/riscv-common.cc | 75 +++-
gcc/config/riscv/riscv-subset.h | 2 +
gcc/testsuite/gcc.target/riscv/arch-44.c | 5 ++
gcc/testsuite/gcc.target/riscv/arch-45.c | 12
gcc/testsuite/gcc.target/riscv/arch-46.c | 12
5 files changed, 10
在 2024/8/5 23:16, Jeff Law 写道:
On 7/15/24 10:08 PM, Jiawei wrote:
在 2024/07/16 8:28, Jeff Law 写道:
IIRC these fails are dependent upon whether or not the statements
turn into vector stores or not.
So to remove the xfail don't you have to know if vector is enabled/
disabled?
I a
在 2024/8/5 23:21, Jeff Law 写道:
On 8/5/24 6:26 AM, Jiawei wrote:
The test has been observed to pass on most architectures including
RISC-V:
https://godbolt.org/z/8nYEvW6n1
Origin issue see:
https://gcc.gnu.org/PR79356#c11
Update RISC-V target to to pass list.
gcc/testsuite/ChangeLog
在 2024/8/5 22:15, Jeff Law 写道:
On 8/4/24 8:20 PM, Jiawei wrote:
在 2024/8/5 8:45, Jeff Law 写道:
On 8/2/24 9:32 AM, Jiawei wrote:
https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: New extension.
* config
The test has been observed to pass on most architectures including RISC-V:
https://godbolt.org/z/8nYEvW6n1
Origin issue see:
https://gcc.gnu.org/PR79356#c11
Update RISC-V target to to pass list.
gcc/testsuite/ChangeLog:
* gcc.dg/attr-alloc_size-11.c: Add RISC-V to the list
of ta
在 2024/8/5 8:45, Jeff Law 写道:
On 8/2/24 9:32 AM, Jiawei wrote:
https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: New extension.
* config/riscv/riscv.opt: New mask.
gcc/testsuite/ChangeLog:
* gcc.target
在 2024/8/1 21:54, Christoph Müllner 写道:
On Mon, Jul 29, 2024 at 5:26 AM Jiawei wrote:
This patch adds support for RISC-V RVA23 and RVB23 Profiles[1],
which depend on the base RISC-V Profiles support[2].
[1]
https://github.com/riscv/riscv-profiles/releases/tag/rva23-v0.4-rvb23-v0.1-internal
https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: New extension.
* config/riscv/riscv.opt: New mask.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-42.c: New test.
* gcc.target/riscv/arch-43
在 2024/8/1 21:54, Christoph Müllner 写道:
On Mon, Jul 29, 2024 at 5:26 AM Jiawei wrote:
This patch adds support for RISC-V RVA23 and RVB23 Profiles[1],
which depend on the base RISC-V Profiles support[2].
[1]
https://github.com/riscv/riscv-profiles/releases/tag/rva23-v0.4-rvb23-v0.1-internal
在 2024/7/31 4:48, Jeff Law 写道:
On 7/28/24 9:24 PM, Jiawei wrote:
This patch adds support for RISC-V RVA23 and RVB23 Profiles[1],
which depend on the base RISC-V Profiles support[2].
[1]
https://github.com/riscv/riscv-profiles/releases/tag/rva23-v0.4-rvb23-v0.1-internal-review
[2] https
This patch adds support for RISC-V RVA23 and RVB23 Profiles[1],
which depend on the base RISC-V Profiles support[2].
[1]
https://github.com/riscv/riscv-profiles/releases/tag/rva23-v0.4-rvb23-v0.1-internal-review
[2] https://gcc.gnu.org/pipermail/gcc-patches/2024-July/658082.html
gcc/ChangeLog:
Supports RISC-V profiles[1] in -march option.
Default input set the profile before other formal extensions.
V2: Fixes some format errors and adds code comments for parse function
Thanks for Jeff Law's review and comments.
V3: Update testcases and profiles extensions support.Remove S/M mode Profi
/18 15:05, Richard Biener 写道:
On Thu, 18 Jul 2024, Jiawei wrote:
This patch improves SLP reduction handling by ensuring proper processing
even for a single reduction statement.Vectorization instances are now built
only when there are multiple scalar statements to combine into an SLP
reduction
This patch improves SLP reduction handling by ensuring proper processing
even for a single reduction statement.Vectorization instances are now built
only when there are multiple scalar statements to combine into an SLP
reduction.
An example see https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110632
在 2024/07/16 8:28, Jeff Law 写道:
IIRC these fails are dependent upon whether or not the statements turn
into vector stores or not.
So to remove the xfail don't you have to know if vector is
enabled/disabled?
I am not sure, I tried to enable with RVV, but it still pass the test:
https://go
Update warning test info for RISC-V target, compared on godbolt:
https://godbolt.org/z/Mexd3dfcc
gcc/testsuite/ChangeLog:
* gcc.dg/Wstringop-overflow-47.c: Remove xfail target.
---
gcc/testsuite/gcc.dg/Wstringop-overflow-47.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Return NULL_TREE when genop3 equal EXACT_DIV_EXPR.
https://gcc.gnu.org/pipermail/gcc-patches/2024-May/652641.html
version log v3: remove additional POLY_INT_CST check.
https://gcc.gnu.org/pipermail/gcc-patches/2024-May/652795.html
gcc/ChangeLog:
* tree-ssa-pre.cc (create_component_ref_by
Return NULL_TREE when match the POLY_INT case.
https://gcc.gnu.org/pipermail/gcc-patches/2024-May/652641.html
gcc/ChangeLog:
* tree-ssa-pre.cc (create_component_ref_by_pieces_1): New
* conditions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/pr115214.c: New tes
On 2024/5/24 20:33, Richard Biener wrote:
On Fri, May 24, 2024 at 1:49 PM Jiawei wrote:
An ICE bug reported in
https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1071140.
https://godbolt.org/z/WE9aGYvoo
Return NULL_TREE when TREE_CODE(op) not equal to SSA_NAME.
The assert is on purpose
An ICE bug reported in
https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1071140.
https://godbolt.org/z/WE9aGYvoo
Return NULL_TREE when TREE_CODE(op) not equal to SSA_NAME.
gcc/ChangeLog:
* tree-ssa-pre.cc (find_or_generate_expression): Remove assert.
gcc/testsuite/ChangeLog:
*
> -原始邮件-
> 发件人: "Jeff Law"
> 发送时间: 2024-03-19 10:54:09 (星期二)
> 收件人: Jiawei , gcc-patches@gcc.gnu.org
> 抄送: kito.ch...@sifive.com, pal...@dabbelt.com,
christoph.muell...@vrull.eu, wuwei2...@iscas.ac.cn, shi...@iscas.ac.cn,
shiyul...@iscas.ac.cn, chenyix...@isc
From: Chen Jiawei
Co-Authored by: Lin Jiawei
This patch add XiangShan Nanhu cpu microarchitecture,
Nanhu is a 6-issue, superscalar, out-of-order processor.
More details see: https://xiangshan-doc.readthedocs.io/zh-cn/latest/arch
gcc/ChangeLog:
* config/riscv/riscv-cores.def
> -原始邮件-
> 发件人: "Jeff Law"
> 发送时间: 2023-12-12 00:15:44 (星期二)
> 收件人: Jiawei , gcc-patches@gcc.gnu.org
> 抄送: kito.ch...@sifive.com, pal...@dabbelt.com, christoph.muell...@vrull.eu
> 主题: Re: [RFC] RISC-V: Support RISC-V Profiles in -march option.
>
>
&g
Supports RISC-V profiles[1] in -march option.
Default input set the profile is before other formal extensions.
V2: Fixes some format errors and adds code comments for parse function
Thanks for Jeff Law's review and comments.
[1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc
gcc
Supports RISC-V profiles[1] in -march option.
Default input set the profile is before other formal extensions.
[1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (struct riscv_profiles):
New struct.
(
Add ZC* extensions march args tests for error input cases.
Co-Authored by: Nandni Jamnadas
Co-Authored by: Jiawei
Co-Authored by: Mary Bennett
Co-Authored by: Simon Cook
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-22.c: New test.
* gcc.target/riscv/arch-23.c: New test
This patch enables the compressible features with ZC* extensions.
Since all ZC* extension depends on the Zca extension, it's sufficient to only
add the target Zca to extend the target RVC.
Co-Authored by: Mary Bennett
Co-Authored by: Nandni Jamnadas
Co-Authored by: Simon Cook
gcc/ChangeLog:
This patch is the minimal support for ZC* extensions, include the extension
name, mask and target defination. Also define the dependencies with Zca
and Zce extension. Notes that all ZC* extensions depend on the Zca extension.
Zce includes all relevant ZC* extensions for microcontrollers using. Zce
dd ZC* test for march args being passed.
Jiawei (3):
RISC-V: Minimal support for ZC* extensions.
RISC-V: Enable compressible features when use ZC* extensions.
RISC-V: Add ZC* test for failed march args being passed.
gcc/common/config/riscv/riscv-common.cc | 38 +++
g
Seems there are some indent format problems in the patch, could you fix them :)
```
patch:509: indent with spaces.
x_save_size = riscv_stack_align (num_multi_push * UNITS_PER_WORD);
error: patch failed: gcc/config/riscv/riscv.cc:5652
error: gcc/config/riscv/riscv.cc: patch does not apply
Sorry for the late, I will send the binutils patch within this week.
- Original Message -
From: "Kito Cheng"
To: "Fei Gao"
Cc: gcc-patches@gcc.gnu.org, pal...@dabbelt.com, jeffreya...@gmail.com,
sinan@linux.alibaba.com, jia...@iscas.ac.cn
Sent: Mon, 5 Jun 2023 16:31:29 +0800
Su
> ---
> htdocs/gcc-13/changes.html | 31 ++-
> 1 file changed, 30 insertions(+), 1 deletion(-)
>
> diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
> index f6941534..5427f805 100644
> --- a/htdocs/gcc-13/changes.html
> +++ b/htdocs/gcc-13/changes.ht
Add Zcmp extension testcases, zcmpe means Zcmp with RVE extension.
Co-Authored by: Nandni Jamnadas
Co-Authored by: Yulong Shi
Co-Authored by: Shihua Liao
Co-Authored by: Sinan Lin
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zc-zcmp-push-pop-1.c: New test.
* gcc.target/riscv/z
This patch is the minimal support for ZC* extensions, include the extension
name, mask and target defination. Also define the dependencies with Zca
and Zce extension. Notes that all ZC* extensions depend on the Zca extension.
Zce includes all relevant ZC* extensions for microcontrollers using. Zce
Add Zcmp extension instructions support. Generate push/pop
with follow steps:
1. preprocessing:
1.1. if there is no push rtx, then just return. e.g.
(note 5 1 22 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn/f 22 5 23 2 (set (reg/f:SI 2 sp)
(plus:SI (reg/f:SI 2 sp)
(const_int -
RISC-V Code Size Reduction(ZC*) extensions is a group of extensions
which define subsets of the existing C extension (Zca, Zcd, Zcf) and new
extensions(Zcb, Zcmp, Zcmt) which only contain 16-bit encodings.[1]
The implementation of the RISC-V Code Size Reduction extension in GCC is
an important st
From: Charlie Keaney
Add all ZC* extensions march args tests.
Co-Authored by: Nandni Jamnadas
Co-Authored by: Jiawei
Co-Authored by: Mary Bennett
Co-Authored by: Simon Cook
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-20.c: New test.
* gcc.target/riscv/arch-21.c: New
This patch enables the compressible features with ZC* extensions.
Since all ZC* extension depends on the Zca extension, it's sufficient to only
add the target Zca to extend the target RVC.
Co-Authored by: Mary Bennett
Co-Authored by: Nandni Jamnadas
Co-Authored by: Simon Cook
gcc/ChangeLog:
> -原始邮件-
> 发件人: "Jeff Law"
> 发送时间: 2023-04-05 09:30:43 (星期三)
> 收件人: "Hans-Peter Nilsson" , Jiawei
> 抄送: gcc-patches@gcc.gnu.org, kito.ch...@sifive.com, pal...@dabbelt.com,
christoph.muell...@vrull.eu, wuwei2...@iscas.ac.cn
> 主题: Re: [PATCH v2] R
Z*inx is conflict with float extensions, add incompatible check when
z*inx and f extension both enabled.
Since all float extension imply f extension and all z*inx extension
imply zfinx extension, so we just need to check f with zfinx extension
as the base case.
Co-Authored by: Kito Cheng
gcc/
arget. Maybe we can add new check function in
the new
version :)
> -原始邮件-
> 发件人: "Kito Cheng"
> 发送时间: 2023-03-27 16:15:00 (星期一)
> 收件人: Jiawei
> 抄送: gcc-patches@gcc.gnu.org, kito.ch...@sifive.com, pal...@dabbelt.com,
christoph.muell...@vrull.eu, wuwei2...@iscas.
Z*inx is conflict with float extensions, add incompatible check when
z*inx and hard_float both enabled.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_option_override): New check.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-19.c: New test.
---
gcc/config/riscv/riscv.cc
Z*inx is conflict with float extensions, add incompatible check when
z*inx and hard_float both enabled.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_option_override): New check.
---
gcc/config/riscv/riscv.cc | 4
1 file changed, 4 insertions(+)
diff --git a/gcc/config/riscv/riscv
H) in
> TargetVariable(riscv_zk_subext)> +> +Mask(ZKR) in
> TargetVariable(riscv_zk_subext)> +> +Mask(ZKSED) in
> TargetVariable(riscv_zk_subext)> +> +Mask(ZKSH) in
> TargetVariable(riscv_zk_subext)> +> +Mask(ZKT) in
> TargetVariable(riscv_zk_subext)> +&
6B) in TargetVariable(riscv_zvl_flags)
+
TargetVariable
int riscv_zicmo_subext
+Mask(ZICBOZ) in TargetVariable(riscv_zicmo_subext)
+
+Mask(ZICBOM) in TargetVariable(riscv_zicmo_subext)
+
+Mask(ZICBOP) in TargetVariable(riscv_zicmo_subext)
+
TargetVariable
int riscv_zf_subext
+Mask(ZFHMIN) in TargetVariable(
> -原始邮件-
> 发件人: "Jeff Law"
> 发送时间: 2022-11-21 23:26:37 (星期一)
> 收件人: "juzhe.zh...@rivai.ai" , schwab
> 抄送: gcc-patches , "monk.chiang"
, "kito.cheng" , jiawei
> 主题: Re: [PATCH] RISC-V: Add RVV registers register spil
This testcase mix exist spill-1.c and adding new fun to check if
there have redundant addi intructions. Idea provided by Jeff Law.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/spill-sp-adjust.c: New test.
---
.../gcc.target/riscv/rvv/base/spill-sp-adjust.c | 13 +
Sometimes "step1 -= scalable_frame" will cause adjust equal to
zero. And it will generate additional redundant instruction
"addi sp,sp,0". Add checking segement to skip that case.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_expand_epilogue):
al to zero, remove redundant insn gen.
```
csrrt0,vlenb
sllit1,t0,1
add sp,sp,t1
ld s0,24(sp)
addisp,sp,32
jr ra
```
Thanks for Kito and Jeff's suggestion, add testcase and fix code format.
jiawei (2):
RISC-V: Add spill
> -原始邮件-
> 发件人: "Kito Cheng"
> 发送时间: 2022-11-15 09:48:26 (星期二)
> 收件人: jiawei
> 抄送: gcc-patches@gcc.gnu.org, kito.ch...@sifive.com, pal...@rivosinc.com,
juzhe.zh...@rivai.ai, christoph.muell...@vrull.eu, philipp.toms...@vrull.eu,
wuwei2...@iscas.ac.cn
> 主题:
Skip add insn generate if the adjust size equal to zero.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_expand_epilogue):
New if control segement.
---
gcc/config/riscv/riscv.cc | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
dif
Add two new function to handle profile input,
"parse_profile" will check if a input into -march is
legal, if it is then "handle_profile" will check the
profile's type[I/M/A], year[20/22] and mode[U/S/M],
set different extensions combine, just deal mandatory
part currently.
gcc/ChangeLog:
Supports RISC-V profiles[1] in -march option, add minimal extension name
supports.
Default input set the profile is before other formal extensions.
Test with -march=RV[I/M/A]2[0/2][U/M/S][64/32]+otherextensions.
[1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc
jiawei (2
This patch just add name support contain in profiles.
Set the extension version as 0.1.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: New extensions.
* config/riscv/riscv-opts.h (MASK_ZICCAMOA): New mask.
(MASK_ZICCIF): Ditto.
(MASK_ZICCLSM): Ditto.
From: Jiawei
Limit z*inx abi support with 'ilp32','ilp32e','lp64' only.
Use GPR instead FPR when 'zfinx' enable, Only use even registers
in RV32 when 'zdinx' enable.
Enable FLOAT16 when Zhinx/Zhinxmin enabled.
Co-Authored-By: Sinan Lin.
gcc
From: Jiawei
Test zhinx/zhinxmin support, same like with zfh/zfhmin testcases
but use gprs and don't use fmv instruction.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/_Float16-zhinx-1.c: New test.
* gcc.target/riscv/_Float16-zhinx-2.c: New test.
* gcc.target/
From: Jiawei
Support 'TARGET_ZFINX' with float instruction pattern and builtin function.
Reuse 'TARGET_HADR_FLOAT', 'TARGET_DOUBLE_FLOAT' and 'TARGET_ZHINX' patterns.
gcc/ChangeLog:
* config/riscv/iterators.md (TARGET_ZFINX):N
e zfh/zfhmin.
Jiawei (4):
RISC-V: Minimal support of z*inx extension.
RISC-V: Target support for z*inx extension.
RISC-V: Limit regs use for z*inx extension.
RISC-V: Add zhinx/zhinxmin testcases.
gcc/common/config/riscv/riscv-common.cc | 18 +
gcc/config/riscv/arch-canonic
From: Jiawei
Minimal support of z*inx extension, include 'zfinx'， 'zdinx' and
'zhinx/zhinxmin'
corresponding to 'f', 'd' and 'zfh/zfhmin', the 'zdinx' will imply 'zfinx'
same as 'd' imply 'f', &
LGTM, Maybe we can try is after RVV supported.> We don't yet support
vectorization on RISC-V.
> > gcc/testsuite/ChangeLog> > * gcc.dg/tree-ssa/gen-vect-34.c: Skip RISC-V
> > targets.> ---> gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c | 2 +-> 1 file
> > changed, 1 insertion(+), 1 deletion(-)> >
From: Jiawei
Add -m[no]-csr-check option in gcc part, when enable -mcsr-check option,
it will add csr-check in .option section and pass this to assembler.
V2: Add assembler support check info for -mcsr-check. Thanks for Kito's
suggestions.
gcc/ChangeLog:
* config.in: Ne
From: Jiawei
Add -m[no]-csr-check option in gcc part, when enable -mcsr-check option,
it will add csr-check in .option section and pass this to assembler.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_file_start): New .option.
* config/riscv/riscv.opt: New options
> -原始邮件-
> 发件人: "Richard Biener"
> 发送时间: 2022-07-28 15:45:27 (星期四)
> 收件人: jiawei
> 抄送: gcc-patches@gcc.gnu.org, ja...@redhat.com, pal...@rivosinc.com,
kito.ch...@gmail.com, jim.wilson@gmail.com, wuwei2...@iscas.ac.cn
> 主题: Re: [PATCH] testsuite: Add
This patch adds the additional options on RISC-V target.
"-fprefetch-loop-arrays" option needs enable prefetch instruction,
for RISC-V that contained in "zicbop" extension.
Use "-march" with "zicbop" will enable this feature.
gcc/testsuite/ChangeLog:
* gcc.dg/pr106397.c: New dg-additional
> gcc/ChangeLog
>
> * config.gcc (riscv): Accept rv64e and lp64e.
> * config/riscv/arch-canonicalize: Likewise.
> * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Likewise.
> * config/riscv/riscv-opts.h (riscv_abi_type): Likewise.
> * config/riscv/riscv.cc (riscv_option_override): Likewi
From: Jia-wei Chen
In rv32 regression test, this cases will report an error:
"cc1: error: ABI requires '-march=rv32'"
Add '-mabi' option will fix this.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr105666.c: New options.
---
gcc/testsuite/gcc.target/riscv/pr105666.c | 2 +-
1 file c
x27;s comment, add Changelog part in patches, update imply
info in riscv-common.c, remove useless check and update annotation in
riscv.c.
v3: Update with new isa-spec version 20191213, make zfinx imply zicsr as
default, fix the lack of fcsr use in zfinx.
jiawei (3):
RISC-V: Minimal support of
From: Jia-Wei Chen
Support 'TARGET_ZFINX' with float instruction pattern and builtin function.
Reuse 'TARGET_HADR_FLOAT' and 'TARGET_DOUBLE_FLOAT' patterns.
gcc/ChangeLog:
* config/riscv/riscv-builtins.cc (AVAIL): Add TARGET_ZFINX.
(riscv_atomic_assign_expand_fenv): Ditto.
From: Jia-Wei Chen
Limit zfinx abi support with 'ilp32','ilp32e','lp64' only.
Use GPR instead FPR when 'zfinx' enable, Only use even registers in RV32 when
'zdinx' enable.
gcc/ChangeLog:
* config/riscv/constraints.md (TARGET_HARD_FLOAT ? FP_REGS :
((TARGET_ZFINX || TARGET_ZDI
From: Jia-Wei Chen
Minimal support of zfinx extension, include 'zfinx' and 'zdinx'
corresponding to 'f' and 'd', the 'zdinx' will imply 'zfinx'
same as 'd' imply 'f'.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add z[f/d]inx extension info.
* config/riscv/arch-canonica
x27;s comment, add Changelog part in patches, update imply
info in riscv-common.c, remove useless check and update annotation in
riscv.c.
v3: Update with new isa-spec version 20191213, make zfinx imply zicsr as
default, fix the lack of fcsr use in zfinx.
jiawei (3):
RISC-V: Minimal support of
Similar to patch 593993, RISC-V needs to limit symbols send in sdata.
Thanks for Palmer's help.
gcc/testsuite/ChangeLog:
* g++.dg/opt/const7.C: Don't use small data on RISC-V.
---
gcc/testsuite/g++.dg/opt/const7.C | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/g++.dg/
Some compiler target like arm-linux\riscv\power\s390x\xtensa-gcc handle
char as unsigned char, then there are no warnings occur and got FAIL cases.
Just change the type char into explicit signed char to keep the feature
consistency.
gcc/testsuite/ChangeLog:
* c-c++-common/Wconversion-1.c
The "ftree-parallelize-loops=" imply -pthread option in gcc/gcc.cc,
some target are not support pthread like elf target use newlib,
and will get an error:
"*-*-elf-gcc: error: unrecognized command-line option '-pthread'"
so we add an additional condition "{target pthread}" to make sure the
dg-add
Bump default ISA spec to newer version 20191213, current default ISA spec
is 2.2, but it's already out of date for a long time, sync with binutils
ISA version, convention in toolchain use.
gcc/ChangeLog:
* config.gcc: Modify default isa_spec version.
---
gcc/config.gcc | 8
1 f
Add -msmall-data-limit option to put global and static data into right
section and generate 'btt_info' on RISC-V target.
BTF (BPF Type Format) is the metadata format which encodes the debug info
related to BPF program/map, more details on:
https://www.kernel.org/doc/html/latest/bpf/index.html#bpf
Minimal support of zfinx extension, include 'zfinx' and 'zdinx' corresponding
to 'f' and 'd', the 'zdinx' will imply 'zfinx' same as 'd' imply 'f'.
gcc/ChangeLog:
* common/config/riscv/riscv-common.c(riscv_implied_info_t): Add zdinx
imply zfinx.
(riscv_ext_version_table): Add
Limit zfinx abi support with 'ilp32','ilp32e','lp64' only.
Use GPR instead FPR when 'zfinx' enable, Only use even registers in RV32 when
'zdinx' enable.
gcc/ChangeLog:
* config/riscv/constraints.md
(TARGET_HARD_FLOAT ? FP_REGS : ((TARGET_ZFINX || TARGET_ZDINX) ?
GR_REGS : NO_RE
Support 'TARGET_ZFINX' with float instruction pattern and builtin function.
gcc/ChangeLog:
* config/riscv/riscv-builtins.c (AVAIL): Add TARGET_ZFINX.
(riscv_atomic_assign_expand_fenv): Ditto.
* config/riscv/riscv-c.c (riscv_cpu_cpp_builtins): Add TARGET_ZFINX.
* co
gelog part in patches, update imply info
in riscv-common.c,
remove useless check and update annotation in riscv.c.
jiawei (3):
RISC-V: Minimal support of zfinx extension
RISC-V: Target support for zfinx extension
RISC-V: Limit regs use for zfinx extension
gcc/common/config/riscv/riscv-com
Co-Authored-By: sinan
---
gcc/config/riscv/arch-canonicalize | 1 +
gcc/config/riscv/constraints.md| 3 ++-
gcc/config/riscv/riscv.c | 15 +--
3 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/arch-canonicalize
b/gcc/config/riscv/arch-ca
Co-Authored-By: sinan
---
gcc/config/riscv/riscv-builtins.c | 4 +-
gcc/config/riscv/riscv-c.c| 2 +-
gcc/config/riscv/riscv.md | 72 +++
3 files changed, 39 insertions(+), 39 deletions(-)
diff --git a/gcc/config/riscv/riscv-builtins.c
b/gcc/config/
Co-Authored-By: sinan
---
gcc/common/config/riscv/riscv-common.c | 6 ++
gcc/config/riscv/riscv-opts.h | 6 ++
gcc/config/riscv/riscv.opt | 3 +++
3 files changed, 15 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.c
b/gcc/common/config/riscv/riscv-c
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