Support the Sm/scsrind extensions, which provide indirect access to
machine-level CSRs.
gcc/ChangeLog:
* config/riscv/riscv-ext.def: New extension definition.
* config/riscv/riscv-ext.opt: New extension mask.
* doc/riscv-ext.texi: Document the new extension.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-smcsrind.c: New test.
Signed-off-by: Jiawei <jia...@iscas.ac.cn>
---
gcc/config/riscv/riscv-ext.def | 26 +++++++++++++++++++
gcc/config/riscv/riscv-ext.opt | 4 +++
gcc/doc/riscv-ext.texi | 8 ++++++
.../gcc.target/riscv/arch-smcsrind.c | 5 ++++
4 files changed, 43 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-smcsrind.c
diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index 0d715a163c7..6c122c3987b 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -1701,6 +1701,19 @@ DEFINE_RISCV_EXT(
/* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
/* EXTRA_EXTENSION_FLAGS */ 0)
+DEFINE_RISCV_EXT(
+ /* NAME */ smcsrind,
+ /* UPPERCASE_NAME */ SMCSRIND,
+ /* FULL_NAME */ "Machine-Level Indirect CSR Access",
+ /* DESC */ "",
+ /* URL */ ,
+ /* DEP_EXTS */ ({"zicsr", "sscsrind"}),
+ /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+ /* FLAG_GROUP */ sm,
+ /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+ /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+ /* EXTRA_EXTENSION_FLAGS */ 0)
+
DEFINE_RISCV_EXT(
/* NAME */ smepmp,
/* UPPERCASE_NAME */ SMEPMP,
@@ -1792,6 +1805,19 @@ DEFINE_RISCV_EXT(
/* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
/* EXTRA_EXTENSION_FLAGS */ 0)
+DEFINE_RISCV_EXT(
+ /* NAME */ sscsrind,
+ /* UPPERCASE_NAME */ SSCSRIND,
+ /* FULL_NAME */ "Supervisor-Level Indirect CSR Access",
+ /* DESC */ "",
+ /* URL */ ,
+ /* DEP_EXTS */ ({"zicsr"}),
+ /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+ /* FLAG_GROUP */ ss,
+ /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+ /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+ /* EXTRA_EXTENSION_FLAGS */ 0)
+
DEFINE_RISCV_EXT(
/* NAME */ ssnpm,
/* UPPERCASE_NAME */ SSNPM,
diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index 3e5cbb34898..725dc879349 100644
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -339,6 +339,8 @@ Mask(SMAIA) Var(riscv_sm_subext)
Mask(SMCNTRPMF) Var(riscv_sm_subext)
+Mask(SMCSRIND) Var(riscv_sm_subext)
+
Mask(SMEPMP) Var(riscv_sm_subext)
Mask(SMMPM) Var(riscv_sm_subext)
@@ -353,6 +355,8 @@ Mask(SSAIA) Var(riscv_ss_subext)
Mask(SSCOFPMF) Var(riscv_ss_subext)
+Mask(SSCSRIND) Var(riscv_ss_subext)
+
Mask(SSNPM) Var(riscv_ss_subext)
Mask(SSPM) Var(riscv_ss_subext)
diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index 3e6541ac732..ca7414e0c7a 100644
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -502,6 +502,10 @@
@tab 1.0
@tab Cycle and instret privilege mode filtering
+@item smcsrind
+@tab 1.0
+@tab Machine-Level Indirect CSR Access
+
@item smepmp
@tab 1.0
@tab PMP Enhancements for memory access and execution prevention on Machine
mode
@@ -530,6 +534,10 @@
@tab 1.0
@tab Count overflow & filtering extension
+@item sscsrind
+@tab 1.0
+@tab Supervisor-Level Indirect CSR Access
+
@item ssnpm
@tab 1.0
@tab ssnpm extension
diff --git a/gcc/testsuite/gcc.target/riscv/arch-smcsrind.c
b/gcc/testsuite/gcc.target/riscv/arch-smcsrind.c
new file mode 100644
index 00000000000..4d1c1045399
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-smcsrind.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_smcsrind -mabi=lp64" } */
+int foo()
+{
+}
--
2.43.0
