Support the Sstvecd extension, which allows Supervisor Trap Vector
Base Address register (stvec) to support Direct mode.
gcc/ChangeLog:
* config/riscv/riscv-ext.def: New extension definition.
* config/riscv/riscv-ext.opt: New extension mask.
* doc/riscv-ext.texi: Document the new extension.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-sstvecd.c: New test.
Signed-off-by: Jiawei <jia...@iscas.ac.cn>
---
gcc/config/riscv/riscv-ext.def | 13 +++++++++++++
gcc/config/riscv/riscv-ext.opt | 2 ++
gcc/doc/riscv-ext.texi | 4 ++++
gcc/testsuite/gcc.target/riscv/arch-sstvecd.c | 5 +++++
4 files changed, 24 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-sstvecd.c
diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index 8d8e878d307..7b83d6f944d 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -1922,6 +1922,19 @@ DEFINE_RISCV_EXT(
/* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
/* EXTRA_EXTENSION_FLAGS */ 0)
+DEFINE_RISCV_EXT(
+ /* NAME */ sstvecd,
+ /* UPPERCASE_NAME */ SSTVECD,
+ /* FULL_NAME */ "Stvec supports Direct mode",
+ /* DESC */ "",
+ /* URL */ ,
+ /* DEP_EXTS */ ({"zicsr"}),
+ /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+ /* FLAG_GROUP */ ss,
+ /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+ /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+ /* EXTRA_EXTENSION_FLAGS */ 0)
+
DEFINE_RISCV_EXT(
/* NAME */ ssstrict,
/* UPPERCASE_NAME */ SSSTRICT,
diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index 115a1c5de8d..8eb447c2dc0 100644
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -373,6 +373,8 @@ Mask(SSTC) Var(riscv_ss_subext)
Mask(SSTVALA) Var(riscv_ss_subext)
+Mask(SSTVECD) Var(riscv_ss_subext)
+
Mask(SSSTRICT) Var(riscv_ss_subext)
Mask(SSDBLTRP) Var(riscv_ss_subext)
diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index 075cef2c7d8..fd9cbef1d9d 100644
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -570,6 +570,10 @@
@tab 1.0
@tab Stval provides all needed values
+@item sstvecd
+@tab 1.0
+@tab Stvec supports Direct mode
+
@item ssstrict
@tab 1.0
@tab ssstrict extension
diff --git a/gcc/testsuite/gcc.target/riscv/arch-sstvecd.c
b/gcc/testsuite/gcc.target/riscv/arch-sstvecd.c
new file mode 100644
index 00000000000..e76f78818ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-sstvecd.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_sstvecd -mabi=lp64" } */
+int foo()
+{
+}
--
2.43.0
