[PATCH] RISC-V: Minimal support for Zimop extension.

[Jiawei]

https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc

gcc/ChangeLog:

        * common/config/riscv/riscv-common.cc: New extension.
        * config/riscv/riscv.opt: New mask.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/arch-42.c: New test.
        * gcc.target/riscv/arch-43.c: New test.

---
 gcc/common/config/riscv/riscv-common.cc  | 8 ++++++++
 gcc/config/riscv/riscv.opt               | 7 +++++++
 gcc/testsuite/gcc.target/riscv/arch-42.c | 5 +++++
 gcc/testsuite/gcc.target/riscv/arch-43.c | 5 +++++
 4 files changed, 25 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-42.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-43.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 1944c7785c4..62c6e1dab1f 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -97,6 +97,8 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"zabha", "zaamo"},
   {"zacas", "zaamo"},
 
+  {"zcmop", "zca"},
+
   {"b", "zba"},
   {"b", "zbb"},
   {"b", "zbs"},
@@ -319,6 +321,9 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zicclsm",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"ziccrse",  ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zimop", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcmop", ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"zicntr", ISA_SPEC_CLASS_NONE, 2, 0},
   {"zihpm",  ISA_SPEC_CLASS_NONE, 2, 0},
 
@@ -1629,6 +1634,9 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zicbop", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOP},
   {"zic64b", &gcc_options::x_riscv_zicmo_subext, MASK_ZIC64B},
 
+  {"zimop",    &gcc_options::x_riscv_mop_subext, MASK_ZIMOP},
+  {"zcmop",    &gcc_options::x_riscv_mop_subext, MASK_ZCMOP},
+
   {"zve32x",   &gcc_options::x_target_flags, MASK_VECTOR},
   {"zve32f",   &gcc_options::x_target_flags, MASK_VECTOR},
   {"zve64x",   &gcc_options::x_target_flags, MASK_VECTOR},
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 2e340e5324f..a8758abc918 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -406,6 +406,13 @@ Mask(ZICBOP) Var(riscv_zicmo_subext)
 
 Mask(ZIC64B) Var(riscv_zicmo_subext)
 
+TargetVariable
+int riscv_mop_subext
+
+Mask(ZIMOP) Var(riscv_mop_subext)
+
+Mask(ZCMOP) Var(riscv_mop_subext)
+
 TargetVariable
 int riscv_zf_subext
 
diff --git a/gcc/testsuite/gcc.target/riscv/arch-42.c 
b/gcc/testsuite/gcc.target/riscv/arch-42.c
new file mode 100644
index 00000000000..83f78d28dbe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-42.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zimop -mabi=lp64" } */
+int foo()
+{
+}
diff --git a/gcc/testsuite/gcc.target/riscv/arch-43.c 
b/gcc/testsuite/gcc.target/riscv/arch-43.c
new file mode 100644
index 00000000000..4a300a165fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-43.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zcmop -mabi=lp64" } */
+int foo()
+{
+}
-- 
2.25.1