On 7/18/25 11:03 AM, Artemiy Volkov wrote:
On Wed, Jul 02, 2025 at 08:15:40PM -0600, Jeff Law wrote:
A number of folks have had their fingers in this code and it's going to take
a few submissions to do everything we want to do.
This patch is primarily concerned with avoiding signaling
On 7/18/25 8:37 AM, Georg-Johann Lay wrote:
Ok to apply removal of backends no more present in v13?
Yes.
jeff
On 7/16/25 8:22 AM, pan2...@intel.com wrote:
From: Pan Li
Like the avg3_floor pattern, the avg3_ceil has the
similar issue that lack of the RVV DImode support.
Thus, this patch would like to support the DImode by
the standard name, with the iterator V_VLSI_D.
The below test suites are pass
On 7/16/25 9:20 AM, Stefan Schulze Frielinghaus wrote:
During jump bypassing also consider insns of the form
(insn 25 57 26 9 (parallel [
(set (reg:CCZ 33 %cc)
(compare:CCZ (reg:SI 60 [ _9 ])
(const_int 0 [0])))
(clobber (scratch
On 7/14/25 11:34 PM, Umesh Kalappa wrote:
Updated the test for rv32 accordingly and no regress found for runs like
"runtest --tool gcc
--target_board='riscv-sim/-march=rv32gc_zba_zbb_zbc_zbs/-mabi=ilp32d/-mcmodel=medlow'
riscv.exp" and
"runtest --tool gcc
--target_board='riscv-sim/-march=rv
On 7/10/25 8:44 AM, Dusan Stojkovic wrote:
This peephole pattern combines the following instructions:
bswap8:
rev8a5,a0
-> li a4,-65536
-> sraia5,a5,32
-> and a5,a5,a4
-> roriw a5,a5,16
and a0,a0,a4
or a
On 7/14/25 7:55 AM, Robin Dapp wrote:
Hi,
In PR120297 we fuse
vsetvl e8,mf2,...
vsetvl e64,m1,...
into
vsetvl e64,m4,...
Individually, that's ok but we also change the new vsetvl's demand to
"SEW only" even though the first original one demanded SEW >= 8 and
ratio = 16.
As we forget t
On 7/12/25 8:26 AM, pan2...@intel.com wrote:
From: Pan Li
Per previous discuss with Jeff, we don't do complicated
asm check like scalar saturation alu. It is somehow
not easy to maintain, as well as fragile. Thus, we
remove these function-body check, and introduce the
jmp label asm check i
On 7/12/25 2:58 AM, pan2...@intel.com wrote:
From: Pan Li
Add the run and asm testcase for rv32 SAT_MUL, widen mul from
uint8_t, uint16_t, uint32_t to uint64_t.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat/sat_u_mul-1-u16-from-u64.c: New test.
* gcc.target/riscv/sat/sat_
On 7/14/25 2:52 AM, Robin Dapp wrote:
This pattern enables the combine pass (or late-combine, depending on
the case)
to merge a float_extend'ed vec_duplicate into a plus-mult or minus-
mult RTL
instruction.
Before this patch, we have three instructions, e.g.:
fcvt.s.h fa5,fa5
vfmv
On 7/14/25 2:52 AM, Robin Dapp wrote:
This pattern enables the combine pass (or late-combine, depending on
the case)
to merge a float_extend'ed vec_duplicate into a plus-mult or minus-
mult RTL
instruction.
Before this patch, we have three instructions, e.g.:
fcvt.s.h fa5,fa5
vfmv
On 7/14/25 5:58 AM, Umesh Kalappa wrote:
Hi Jeff and Marco,
Please pass your comments on the below changes and do needful.
The changes fail pre-commit tsting:
https://patchwork.sourceware.org/project/gcc/patch/20250702071624.753431-1-ukalappa.m...@gmail.com/
On 7/10/25 8:37 AM, Jan Dubiec wrote:
On 10.07.2025 15:42, Jeff Law wrote:
[...]
Anyway, this has been repeatedly bootstrapped & regression tested on
aarch64, ppc64le and other targets. It's also been many dozens of
regression testing cycles on the various embedded targets.
Thi
On 7/9/25 11:53 PM, Sebastian Huber wrote:
There are targets, which only offer 32-bit atomic operations (for
example 32-bit RISC-V). For these targets, split the 64-bit atomic
bitwise-or operation into two parts.
For this test case
int a(int i);
int b(int i);
int f(int i)
{
if (i) {
On 2/22/25 8:10 AM, Jan Dubiec wrote:
This patch fixes SFtype to UDWtype (aka float to unsigned long long)
conversion on targets without DFmode like e.g. H8/300H. It solely relies
on SFtype->UWtype and UWtype->UDWtype conversions/casts. The existing code
in line 2218 (counter = a) assigns/cast
On 7/9/25 7:19 PM, Li, Pan2 wrote:
* gcc.target/riscv/sat/sat_u_trunc-run-6-u8.c: Ditto.
Spot checked. Note this uses "RISC-V" so it's not going to be picked up
in the patchwork meeting.
Oops, should be a typo here.
It does seem to be causing some testing problems:
It seems the
On 7/3/25 3:50 PM, Palmer Dabbelt wrote:
This is really Jim's code, but it's been sitting around in Bugzilla for a while
so I've picked it up. All I really did here is add a target hook and mangle
some comments, but I think I understand enough about what's going on to try and
get things movin
On 7/1/25 10:13 PM, Andrew Pinski wrote:
With struct returns, we normally get a decl on the LHS of the call expression
that will be tail called and we can match things up there easy.
With TREE_ADDRESSABLE set on the type, things get more complex.
Instead we get:
```
*_6(D) = get_s (1); [ret
On 7/8/25 11:07 PM, pan2...@intel.com wrote:
From: Pan Li
The sat scalar run test should not require the v extension, thus
take rv32 || rv64 instead of riscv_v for the requirement.
The below test suites are passed for this patch series.
* The rv64gcv fully regression test.
* The rv32gcv ful
On 7/8/25 9:17 AM, Paul-Antoine Arras wrote:
zvfh is not enabled at the testsuite level. It has to be enabled on a testcase
by testcase basis. This was correctly done for compile tests but not for run
tests. This patch fixes it.
Also, to ensure correct results with half-precision floats, MAX_R
On 7/9/25 2:35 AM, Ciyan Pan wrote:
From: panciyan
This patch adjust test data for unsigned vector SAT_SUB to vec_sat_data.h
Passed the rv64gcv regression test.
Signed-off-by: Ciyan Pan
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h: Add
vec_sat_u_s
On 7/9/25 8:00 AM, Richard Sandiford wrote:
Makes me wonder if I should resurrect my aarch64_be RFS. I changed how
those systems worked in the system a few years back to make it work
better with container based testing rather than direct chroots. I never
converted aarch64_be to that setup
This is primarily Daniel's work... He's chasing things in QEMU & LLVM
right now so I'm doing a bit of clean-up and shepherding this patch forward.
--
Instruction fusion is a reasonably common way to improve the performance
of code on many architectures/designs. A few years ago we submitted
On 7/9/25 7:17 AM, Richard Biener wrote:
ISTR the backwards threader simply cancels paths that had blocks in
common with another jump thread (that happened to be materialized
first). But maybe it's less strict than that. It cancels things in too
many places and while it collects all opport
One thing I forgot to bring up in the patchwork meeting yesterday.
Philip or Craig asked if we should add the most basic fusions to the
generic tuning models for the two toolchains.
I'm generally in favor of making that kind of change. I don't think
anyone believes it'd be a major performanc
On 7/9/25 6:53 AM, Richard Biener wrote:
On Wed, Jul 9, 2025 at 2:16 PM Jeff Law wrote:
On 7/9/25 12:27 AM, Richard Biener wrote:
The following changes the percentage that determines how many
stmts are allowed for backwards jump threading from 50 to 54,
enabling the missed jump
On 7/9/25 12:27 AM, Richard Biener wrote:
The following changes the percentage that determines how many
stmts are allowed for backwards jump threading from 50 to 54,
enabling the missed jump threading observed in PR109893.
Bootstrapped and tested on x86_64-unknown-linux-gnu. It seems that
at
On 7/8/25 10:26 AM, Jan Dubiec wrote:
The patch changes order of inclusions, i.e. elfos.h is included before
target specific h8300/h8300.h, in a way similar to a few other targets.
Thanks to this change it is possible to override macros from elfos.h in
h8300/h8300.h, in particular .init/.fini
On 7/9/25 3:11 AM, Robin Dapp wrote:
Also, seems like the CI picked up the patch but didn't run it?
Yea, it's happened with a couple of mine recently, including one
yesterday. If it's not picked up when Paul-Antoine posts an update,
then I'll throw it into my system for some degree of pr
On 7/9/25 4:51 AM, Kito Cheng wrote:
OK if Pan say OK
Note the CI failure is unrelated to Ciyan Pan's work. Looks like
something went goofy in the libstdc++ space. I'm running it through my
tester right now.
jeff
AVL propagation currently assumes that it can propagate a constant AVL
into any vector insn and trips an assert if the insn fails to recognize
after such a propagation.
However, for xtheadvector that is not a correct assumption; xtheadvector
does not allow the vector length to be a constant
On 7/7/25 9:48 PM, Li, Pan2 wrote:
Is that correct? Don't you need to be testing that the platform has
vector in addition to being rv64?
It is riscv.exp test, so I think vector extension is not required here.
Oh, I see. We're not actually turning on RVV anywhere. OK for the trunk.
It lo
On 7/8/25 5:08 AM, Andreas Schwab wrote:
gcc:
PR target/120995
* config/riscv/sync.md (zacas_atomic_cas_value_strong):
Allow op3 to be zero.
gcc/testsuite:
PR target/120995
* gcc.target/riscv/amo/zabha-zacas-atomic-cas.c: New test.
Thanks. I didn't se
On 7/8/25 6:21 AM, Robin Dapp wrote:
Hi,
if a user passes a string that doesn't represent a variable we still try
to compute a hash for its type. Its tree does not represent a type but
just an exceptional, though. This patch just ignores it, leaving the
error to the checking code later.
Re
On 7/8/25 6:21 AM, Robin Dapp wrote:
Hi,
in emit_vlmax_insn_lra we use a vsetivli for an immediate AVL.
XTHeadVector does not support this, so guard appropriately.
Regtested on rv64gcv_zvl512b.
Regards
Robin
PR target/120461
gcc/ChangeLog:
* config/riscv/riscv-v.cc (emit_vlmax_
On 7/7/25 9:24 PM, pan2...@intel.com wrote:
/**/
/* Saturation Add (unsigned and signed)
*/
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c
ommit 477abe67d34f7f8d1b0b12408e08769995b6ca9e
Author: Jeff Law
Date: Mon Jul 7 20:48:17 2025 -0600
[committed] Minor fix to gcc.dg/torture/pr120654.c
I don't recall which port complained, but pr120654.c was failing on one or
more
of the embedded targets due to the use of malloc/free. This change j
k-function-bodies atomic_add_fetch_int_seq_cst
Pushed to the trunk,
jeff
commit 7b1e8e0e85ec6f9d80ceb0d38355b2fcd4785f67
Author: Jeff Law
Date: Mon Jul 7 20:42:04 2025 -0600
[committed][RISC-V] Fix testsuite fallout from check-function-bodies change
Minor fallout from HJ's r
On 7/4/25 10:54 PM, Li, Pan2 wrote:
What you do want to watch out for is constants
Here I want the max value of unsigned scalar based on mode, it could be
UINT8_MAX,
UINT16_MAX, UINT32_MAX and UINT64_MAX.
Understood, but within the compiler HOST_WIDE_INT is how we tend to want
to work on
On 7/4/25 1:43 PM, Vineet Gupta wrote:
Hmm. I'm a little surprised that's needed. But there's new rules in
the era of LRA and define_constraint.
Yeah I was wondering why the fallback reg alternative is not already built-in.
Is that meant to catch bugs in the backends ?
I doubt it's meant
On 7/4/25 1:18 PM, Robin Dapp wrote:
This generally looks OK to me (including the tests).
+ HOST_WIDE_INT max = ((uint64_t)1 << bitsize) - 1;
Wouldn't a uint64_t type for max be clearer? I guess the worst that can
happen is compiling on a 32-bit host for a 64-bit target and get bitsize
On 7/4/25 10:21 AM, Richard Sandiford wrote:
ext-dce had:
if (SUBREG_P (dst) && SUBREG_BYTE (dst).is_constant ())
{
bit = subreg_lsb (dst).to_constant ();
if (bit >= HOST_BITS_PER_WIDE_INT)
bit = HOST_BITS_PER_WIDE_INT - 1;
On 7/3/25 5:19 PM, Vineet Gupta wrote:
Provide a fallback alternaive register contraint for LRA in the light of
the tightened "Q" constraint. Cures the following ICE ...
| gcc/testsuite/gcc.target/riscv/pr118241-b.cc:31:19: error: unable to generate
reloads for:
| 31 | void m() { a.l(); }
On 7/3/25 5:19 PM, Vineet Gupta wrote:
Spotted this by chance as I saw a similar fixup in comments.
From comments, I think this is needed, but I've not hit any issues due
to this.
gcc/ChangeLog:
* config/riscv/predicates.md (prefetch_operand): mack 5 bits.
Signed-off-by: Vineet Gup
This is primarily Shreya's work from a few months back. I just fixed
the formatting, cobbled together the cover letter/ChangeLog.
We were looking to evaluate some changes from Artemiy that improve GCC's
ability to discover fusible instruction pairs. There was no good way to
get any static d
A number of folks have had their fingers in this code and it's going to
take a few submissions to do everything we want to do.
This patch is primarily concerned with avoiding signaling that fusion
can occur in cases where it obviously should not be signaling fusion.
Every DEC based fusion I'm
On 7/2/25 2:16 AM, Robin Dapp wrote:
CI-testing was failed:
https://github.com/ewlu/gcc-precommit-ci/
issues/3585#issuecomment-3022157670
for sat_u_add-5-u32.c and vect-reduc-sad-1.c. These failures are
compile issues
appeared due to afdo-crossmodule-1b.c file. For some reason, in both
case
the set of registers that need promotion state wiped.
And everything is happy after that.
The other cases are similar in nature.
--
This has been bootstrapped and regression tested on x86_64 and aarch64.
Variants have bootstrapped & regression tested on several other
platforms and it's s
On 6/30/25 12:04 AM, Umesh Kalappa wrote:
Thank you @Jeff Law <mailto:jeffreya...@gmail.com> for the comments and
>>I suspect there's something goofy in the indentation in the block above.
like clang-format ,does gcc have a code formatter we can use ?
Not really. Martin
On 6/27/25 12:48 AM, Alexey Merzlyakov wrote:
Fixes incorrect SP-addresses used in CFA notes for the stack probes
unrelative to the frame's top. It applied to the RISC-V targets code
generation when the stack-clash protection is enabled.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_
On 6/30/25 2:18 AM, Richard Biener wrote:
On Sat, 28 Jun 2025, Jeff Law wrote:
On 6/27/25 12:20 PM, Andrew Pinski wrote:
I have been trying to most of the phiopt to over to use match and simplify
(via match.pd patterns). Is there an issue why this can't be a match pattern
in
On 6/12/25 11:03 AM, Alfie Richards wrote:
Add logic for the case of two FMV annotated functions with identical
signature other than the return type.
Previously this was ignored, this changes the behavior to emit a diagnostic.
gcc/cp/ChangeLog:
PR c++/119498
* decl.cc (duplic
On 6/26/25 8:53 AM, Paul-Antoine Arras wrote:
This pattern enables the combine pass (or late-combine, depending on the case)
to merge a vec_duplicate into a (possibly negated) minus-mult RTL instruction.
Before this patch, we have two instructions, e.g.:
vfmv.v.fv6,fa0
vfnmacc.v
On 6/12/25 11:00 AM, Alfie Richards wrote:
Adds the target_version and target_clones attributes to diagnostic messages
for target_version semantics.
This is because the target_version/target_clones attributes affect the identity
of the decls, so need to be represented in diagnostics for them.
On 6/12/25 11:00 AM, Alfie Richards wrote:
This patch introduces the TARGET_REJECT_FUNCTION_CLONE_VERSION hook
which is used to determine if a target_clones version string parses.
If true is returned, a warning is emitted and from then on the version
is ignored.
This is as specified in the A
On 6/12/25 11:00 AM, Alfie Richards wrote:
This is a quick refactor of the riscv target processing code
to take a string_slice rather than a decl.
The reason for this is to enable it to work with target_clones
where merging logic requires reasoning about each version string
individually in th
On 6/27/25 12:16 AM, Andrew Pinski wrote:
Since after a tail call function (even if it is tail called in the end),
the current function does not care about the local memory any more so
there is no reason to do a copy of the argument. This is only true for the
first usage of the decl, the rest
On 6/28/25 6:07 AM, Jin Ma wrote:
The current implementation of this function is somewhat difficult to
understand, as it uses a direct break statement within the for loop,
rendering the loop meaningless. Additionally, during the Coverity check
on the for loop, a warning appeared: "unreachable:
On 6/13/25 9:01 AM, Umesh Kalappa wrote:
Addressed the most of comments and tried to refactor the
riscv_expand_conditional_move() to some extent.
No regressions are found for "runtest --tool gcc
--target_board='riscv-sim/-mabi=lp64d/-mtune=mips-p8700/-O2 ' riscv.exp"
*config/riscv/
On 6/25/25 8:58 PM, Andrew Pinski wrote:
In the case of tailing call with a return of a structure, currently
all large structures are rejected. We can allow the case were the return
of the "tail call" function is setting the return value of the current
function. This allows for the musttail t
On 6/24/25 4:30 AM, Richard Sandiford wrote:
lra-eliminations.cc:move_plus_up tries to:
Transform (subreg (plus reg const)) to (plus (subreg reg) const)
when it is possible.
Most of it is heavily conditional:
if (!paradoxical_subreg_p (x)
&& GET_CODE (subreg_reg) == PLUS
On 6/26/25 1:08 AM, Alexandre Oliva wrote:
dfp.exp tests for dfprt before deciding whether to default to run or
compile, and the PR120631 tests override that without checking for
dfprt. Rework them to avoid attempting to link and run programs
when dfp runtime support isn't available.
Tested
On 6/28/25 2:36 PM, Andrew Pinski wrote:
On Sat, Jun 28, 2025, 1:19 PM Jeff Law <mailto:jeffreya...@gmail.com>> wrote:
On 6/27/25 12:20 PM, Andrew Pinski wrote:
>
>
>
> I have been trying to most of the phiopt to over to use match and
On 6/27/25 12:20 PM, Andrew Pinski wrote:
I have been trying to most of the phiopt to over to use match and
simplify (via match.pd patterns). Is there an issue why this can't be a
match pattern instead? It seems like a good fit too.
It should simplify the code added even.
I can certai
On 6/27/25 10:24 PM, H.J. Lu wrote:
On Sat, Jun 28, 2025 at 12:03 PM Jeff Law wrote:
On 6/27/25 5:34 PM, H.J. Lu wrote:
Add "void debug (tree)" to support:
(gdb) call debug (expr)
unit-size
user align:256 warn_if_not_align:0 symtab:0 alias-set -1
On 6/27/25 5:34 PM, H.J. Lu wrote:
Add "void debug (tree)" to support:
(gdb) call debug (expr)
unit-size
user align:256 warn_if_not_align:0 symtab:0 alias-set -1 canonical-type
0x7fffe99cebd0
fields
XF x.c:2:15
size
unit-
The cherry-picked patch fixes sanitizer builds with musl libc. Which
should fix both ppc and riscv issues using the sanitizer with musl.
Pushed to the trunk.
Jeff
commit 5111ea055f5699ad47605890fb45af5c3db1de4f
Author: Jeff Law
Date: Fri Jun 27 15:11:41 2025 -0600
[sanitizer_common
On 6/27/25 12:30 PM, Andrew Pinski wrote:
On Fri, Jun 27, 2025, 11:06 AM Raphael Moreira Zinsly
mailto:rzin...@ventanamicro.com>> wrote:
Hi all,
For targets that have expensive shifts this may not get a better
sequence right now, specially for AVR and MSP430 according to
On 6/27/25 7:59 AM, Oleg Endo wrote:
On Fri, 2025-06-27 at 10:51 -0300, Raphael Moreira Zinsly wrote:
A right shift of 31 will become 0 or 1, this can be checked for
treg_set_expr_not_const01 to avoid matching addc_t_r as this
can expand to a 3 insn sequence instead.
This improves tests 023
On 6/27/25 7:08 AM, Georg-Johann Lay wrote:
This turns on -mlra per default on avr.
Ok for trunk?
Yes, definitely. The more soak time it gets the better IMHO.
jeff
On 5/5/25 11:56 PM, Bernhard Reutner-Fischer wrote:
On 5 May 2025 20:42:34 CEST, Jeff Law wrote:
diff --git a/gcc/testsuite/gcc.target/riscv/pr119971.c
b/gcc/testsuite/gcc.target/riscv/pr119971.c
new file mode 100644
index 000..c3f23b05ec3
--- /dev/null
+++ b/gcc/testsuite
On 6/26/25 10:51 AM, Stefan Schulze Frielinghaus wrote:
I didn't do any demotion of clobbers since I didn't see any value in it.
If a clobbered register gets accidentally clobbered as e.g. by an
implicitly introduced call, I wouldn't mind.
ACK. I hadn't really thought much about it, just so
On 6/26/25 10:46 AM, Stefan Schulze Frielinghaus wrote:
On Sat, Jun 21, 2025 at 09:18:43AM -0600, Jeff Law wrote:
On 5/20/25 1:22 AM, Stefan Schulze Frielinghaus wrote:
This implements error handling for hard register constraints including
potential conflicts with register asm operands
On 6/26/25 10:38 AM, Stefan Schulze Frielinghaus wrote:
So you need a ChangeLog, but this is OK once the ChangeLog is cobbled
together. I think you should wait to commit until all 4 patches in this
series are ACK'd though.
Thanks for reviewing/commenting all four patches. Very much apprec
On 6/26/25 3:27 AM, Kito Cheng wrote:
Pipeline checker utility for RISC-V architecture that validates processor
pipeline models. This tool analyzes machine description files to ensure all
instruction types are properly handled by pipeline scheduling models.
I write this tool since I am implme
On 6/26/25 7:51 AM, Raphael Moreira Zinsly wrote:
The CFI output for when we do stack probing in a loop were not
accounting for the first sp adjustments, we can fix that by using the
frame's total size.
This is already being tested by g++.dg/torture/pr119610.C.
gcc/ChangeLog:
gcc/conf
Andreas reported openvino failed to build with LTO enabled with gcc-15
on RISC-V. The included .o file was enough for me to reproduce the
problem and it was trivial to then track it down to a fix I'd already
made to the trunk.
commit b93d8873cda88f0892c7782b274904fa8d3751fb
Author: Jef
On 6/23/25 9:12 PM, Ciyan Pan wrote:
From: panciyan
This patch adds testcase for form2, as shown below:
T __attribute__((noinline)) \
sat_s_add_imm_##T##_fmt_2##_##INDEX (T x)\
{
On 6/24/25 3:38 AM, Jiawei wrote:
This patch adds support for the RISC-V Profiles RVA23S64 and RVB23S64.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: New Profiles.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-rva23s.c: New test.
* gcc.target/riscv/arch-
On 6/18/25 7:55 AM, Paul-Antoine Arras wrote:
On 17/06/2025 18:19, Jeff Law wrote:
On 6/17/25 7:15 AM, Paul-Antoine Arras wrote:
This is part of my vector-scalar FMA series. See:
https://gcc.gnu.org/pipermail/gcc-patches/2025-March/679513.html
https://gcc.gnu.org/pipermail/gcc-patches/2025
On 6/23/25 7:07 PM, Kito Cheng wrote:
-riscv_vector::emit_vlmax_insn (code_for_pred_broadcast (mode),
- riscv_vector::UNARY_OP, operands);
+/* We cannot do anything with a Float16 mode apart from converting.
+ So convert to float, broadcast and t
On 5/20/25 1:22 AM, Stefan Schulze Frielinghaus wrote:
Currently a register asm already materializes during expand. This
means, a hard register is allocated for the very first access of a
register asm as e.g. in an assignment. As a consequence this might lead
to suboptimal register allocatio
On 5/20/25 1:22 AM, Stefan Schulze Frielinghaus wrote:
Since genoutput has no information about hard register names we cannot
statically verify those names in constraints of the machine description.
Therefore, we have to do it at runtime. Although verification shouldn't
be too expensive, rest
On 6/7/25 1:04 AM, Andrew Pinski wrote:
Currently expand_constructor when it comes to BLKmode types, we store out
the constructor to memory. But for the zero case, we could just use `const_int
0`
instead for types who are less than or equal to BITS_PER_WORD.
This is only valid if we expanding
This is primarily work from Robin and Shreya. My contribution is just
mentoring for Shreya and writing the ChangeLog. Shreya is busy on a
code generation issue and I expect both new entries in the tuning
structure as well as new instances of the tuning structure in the works
(spacemit x60) co
On 6/23/25 3:56 PM, Peter Bergner wrote:
On 6/20/25 10:38 PM, Jeff Law wrote:
+;; REG or REG+D where D fits in a simm12 and has the low 4 bits
+;; off. The REG+D form can be reloaded into a temporary if needed
+;; after FP elimination if that exposes an invalid offset.
+(define_predicate
On 6/23/25 5:28 PM, Sam James wrote:
Followup to r16-1613-g34e1e5e33ec3eb. remove_reg_equal_equiv_notes's
2nd argument is 'no_rescan' which we accidentally had on, tripping
an assert in combine or ira because we hadn't left things in a consistent
state.
Fix the thinko by enabling rescanning.
gc
On 6/23/25 3:02 AM, KuanLin Chen wrote:
Hi,
This extension defines vector instructions to extract a pair of FP16
data from
a floating-point register. Multiply the top FP16 data with the FP16 elements
and add the result with the bottom FP16 data.
gcc/ChangeLog:
* common/config/ris
On 6/23/25 3:02 AM, KuanLin Chen wrote:
Hi,
This patch adds support for the XAndesperf ISA extension.
The 32-bit AndeStar V5 extension includes branch instructions,
load effective address instructions, and string processing
instructions for performance improvement.
New INSN patterns are added
On 6/23/25 3:02 AM, KuanLin Chen wrote:
Hi,
This is a patch series for Andes vender extension of RISC-V.
These patches are tested by riscv-gnu-toolchain gcc/g++ testsuite. And
the report is the same as without these patches.
= Summary of gcc testsuite =
cc-15 release branch
after simmering on the trunk a bit.
Jeff
commit 34e1e5e33ec3eb475c0c8278800b6fc246a86763
Author: Jeff Law
Date: Sun Jun 22 12:06:08 2025 -0600
[committed][PR rtl-optimization/120550] Drop REG_EQUAL note after ext-dce
transformation
This bug was found by Edwin&
So this is Andrew's patch from the PR. We weren't clean for a 32bit
host in some of the arithmetic for constant synthesis.
I confirmed the bug on a 32bit linux host, then confirmed that Andrew's
patch from the PR fixes the problem, then ran Andrew's patch through my
tester successfully.
Nat
On 5/20/25 1:22 AM, Stefan Schulze Frielinghaus wrote:
This implements error handling for hard register constraints including
potential conflicts with register asm operands.
In contrast to register asm operands, hard register constraints allow
more than just one register per operand. Even mo
On 6/20/25 5:59 AM, Richard Sandiford wrote:
In this PR, we started with:
(subreg:V2DI (reg:DI virtual-reg) 0)
and vregs instantiated the virtual register to the argument pointer.
But:
(subreg:V2DI (reg:DI ap) 0)
is not a sensible subreg, since the argument pointer certainly can'
On 6/12/25 10:53 AM, Alfie Richards wrote:
Previously, the `record` argument in maybe_version_function allowed the
call to cgraph_node::record_function_versions to be skipped. However,
this was only skipped when both decls were already marked as versioned,
in which case we trigger the early e
On 6/21/25 3:52 AM, Robin Dapp wrote:
This patch would like to introduce the combine of vec_dup + vsaddu.vv
into vsaddu.vx on the cost value of GR2VR. The late-combine will take
place if the cost of GR2VR is zero, or reject the combine if non-zero
like 1, 2, 15 in test. There will be two cas
On 5/20/25 1:22 AM, Stefan Schulze Frielinghaus wrote:
Implement hard register constraints of the form {regname} where regname
must be a valid register name for the target. Such constraints may be
used in asm statements as a replacement for register asm and in machine
descriptions.
It is exp
The RISC-V prefetch support is broken in a few ways. This addresses the
data side prefetch problems. I'd mistakenly thought this BZ was a
prefetch.i related (which has deeper problems).
The basic problem is we were accepting any valid address when in fact
there are restrictions. This patch
On 6/20/25 7:04 AM, pan2...@intel.com wrote:
From: Pan Li
The will be one ICE when expand pass, the bt similar as below.
during RTL pass: expand
red.c: In function 'main':
red.c:20:5: internal compiler error: in require, at machmode.h:323
20 | int main() {
| ^~~~
0x2e0b1d6 in
On 6/18/25 3:07 AM, Sosutha Sethuramapandian wrote:
longlong.h for RISCV should define count_leading_zeros and
count_trailing_zeros and COUNT_LEADING_ZEROS_0 when ZBB is enabled.
The following patch patch fixes the bug reported in,
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110181 gcc.gnu
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