On 6/26/25 3:27 AM, Kito Cheng wrote:
Pipeline checker utility for RISC-V architecture that validates processor
pipeline models. This tool analyzes machine description files to ensure all
instruction types are properly handled by pipeline scheduling models.
I write this tool since I am implment vector pipeline stuff for SiFive
core, but it's hard to find which instruction type is not handled by
pipeline scheduling models. This tool will help me to find out which
instruction type is not handled by pipeline scheduling models, so I can
fix them.
And I think it may be useful for other RISC-V core developers, so I
decided to upstream that :)
Sounds fantastic! I'll have to run it internally on our scheduler
models and I'll have Austin do it on the upcoming spacemit x60 model.
Jeff
