On 6/23/25 3:02 AM, KuanLin Chen wrote:
Hi,
This patch adds support for the XAndesperf ISA extension.
The 32-bit AndeStar V5 extension includes branch instructions,
load effective address instructions, and string processing
instructions for performance improvement.
New INSN patterns are added into the new file andes.md
as a seprated vender extension.
gcc/ChangeLog:
* config/riscv/constraints.md (ads_Bz07): New constraint.
(ads_Bext): New constraint.
* config/riscv/iterators.md (ANY32): New iterator.
(sizen): New iterator.
(sh_limit): New iterator.
* config/riscv/predicates.md (branch_bbcs_operand): New predicate.
(branch_bimm_operand): New predicate.
(imm_extract_operand): New predicate.
(extract_size_imm_si): New predicate.
(extract_loc_imm_si): New predicate.
(extract_size_imm_di): New predicate.
(extract_loc_imm_di): New predicate.
* config/riscv/riscv-builtins.cc:
Add new AVAIL andesperf32 and andesperf64.
Add new define RISCV_ATYPE_ULONG and RISCV_ATYPE_LONG.
* config/riscv/riscv-ftypes.def: New DEF_RISCV_FTYPE.
* config/riscv/riscv.cc
(riscv_extend_cost): Cost for pattern 'bfo'.
(riscv_rtx_costs): Cost for XAndesperf extension.
* config/riscv/riscv.md: Add support for XAndesperf to patterns
zero_extendsidi2_internal, zero_extendhi2, extendsidi2_internal,
extend<SHORT:mode><SUPERQI:mode>2, <any_extract:optab><GPR:mode>3
and branch_on_bit.
* config/riscv/vector-iterators.md
(sz): Add sign_extract and zero_extract.
* config/riscv/andes.def: New file for vender Andes.
* config/riscv/andes.md: New file for vender Andes.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xandesperf-1.c: New test.
* gcc.target/riscv/xandesperf-10.c: New test.
* gcc.target/riscv/xandesperf-2.c: New test.
* gcc.target/riscv/xandesperf-3.c: New test.
* gcc.target/riscv/xandesperf-4.c: New test.
* gcc.target/riscv/xandesperf-5.c: New test.
* gcc.target/riscv/xandesperf-6.c: New test.
* gcc.target/riscv/xandesperf-7.c: New test.
* gcc.target/riscv/xandesperf-8.c: New test.
* gcc.target/riscv/xandesperf-9.c: New test.
It doesn't look like the conditional branch patterns support out of
range targets. Or is there something I'm missing?
Long branch handling isn't terribly hard. For most cases it'll end up
generating assembly like this (from the "branch" pattern in riscv.md:
{
if (get_attr_length (insn) == 12)
return "b%r1\t%2,%z3,1f; jump\t%l0,ra; 1:";
return "b%C1\t%2,%z3,%l0";
}
Closely related, I think your "length" attribute is wrong and needs
updating. Length is usually computed by generic code, is that not
working in your case?
One of your cost cases sets *total = 0. That seems quite unexpected.
Is that actually correct? I would have expected COSTS_N_INSNS (1).
For the riscv.md define_insn_and_splits that you changed, changing the
condition seems correct. But I don't think you need to change the split
conditional. When the split condition starts with "&&" it'll use the
main condition && the split condition.
Jeff
