On 7/7/25 9:24 PM, pan2...@intel.com wrote:
/******************************************************************************/
/* Saturation Add (unsigned and signed)
*/
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c
index 395a4cb060c..79f62973af3 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c
@@ -1,4 +1,4 @@
-/* { dg-do run { target { riscv_v } } } */
+/* { dg-do run { target { rv64 } } } */
Is that correct? Don't you need to be testing that the platform has
vector in addition to being rv64?
jeff
