On Mon, Feb 11, 2019 at 2:04 AM H.J. Lu wrote:
>
> On Sun, Feb 10, 2019 at 1:49 PM Uros Bizjak wrote:
> >
> > On Sun, Feb 10, 2019 at 10:45 PM Uros Bizjak wrote:
> >
> > > > > > + [(const_int 0)]
> > > > > > +{
> > > > > > + /* Emulate MMX vec_dupv2si with SSE vec_dupv4si. */
> > > > > > + r
On Mon, Feb 11, 2019 at 3:35 AM Alan Modra wrote:
>
> On Fri, Feb 08, 2019 at 10:51:34AM +0100, Uros Bizjak wrote:
> > On Thu, Feb 7, 2019 at 10:11 PM H.J. Lu wrote:
> > >
> > > OImode and TImode moves must be done in XImode to access upper 16
> > > vector registers without AVX512VL. With AVX512
On February 11, 2019 2:09:30 AM GMT+01:00, Hans-Peter Nilsson
wrote:
>Here's the follow-up, getting rid of the observed
>alignment-padding in execute/930126-1.c: the x parameter in f
>spuriously being runtime-aligned to BITS_PER_WORD. I separated
>this change because this is an older issue, a ch
On Sun, Feb 10, 2019 at 3:41 AM Svante Signell wrote:
>
> On Sat, 2019-02-09 at 23:57 +0100, Svante Signell wrote:
> > On Sat, 2019-02-09 at 14:40 -0800, Ian Lance Taylor wrote:
> > > On Fri, Feb 8, 2019 at 3:07 PM Matthias Klose wrote:
> > > > On 07.02.19 06:04, Ian Lance Taylor wrote:
> > > Wha
On 2/10/19 8:42 PM, Bill Schmidt wrote:
> On 2/10/19 4:05 PM, Segher Boessenkool wrote:
>> Hi Bill,
>>
>> On Sun, Feb 10, 2019 at 10:10:02AM -0600, Bill Schmidt wrote:
>>> I've added executable tests for both shift-right algebraic and shift-right
>>> logical.
>>> Both fail prior to applying the pa
On 2/10/19 4:05 PM, Segher Boessenkool wrote:
> Hi Bill,
>
> On Sun, Feb 10, 2019 at 10:10:02AM -0600, Bill Schmidt wrote:
>> I've added executable tests for both shift-right algebraic and shift-right
>> logical.
>> Both fail prior to applying the patch, and work correctly afterwards.
> Please add
On Fri, Feb 08, 2019 at 10:51:34AM +0100, Uros Bizjak wrote:
> On Thu, Feb 7, 2019 at 10:11 PM H.J. Lu wrote:
> >
> > OImode and TImode moves must be done in XImode to access upper 16
> > vector registers without AVX512VL. With AVX512VL, we can access
> > upper 16 vector registers in OImode and T
Spotted while in a recent gdb session. JFTR, not mine... Committed.
Index: ChangeLog
===
--- ChangeLog (revision 268759)
+++ ChangeLog (revision 268760)
@@ -1,3 +1,8 @@
+2019-02-11 Hans-Peter Nilsson
+
+ * config/cris/c
config/i386/constraints.md has
(define_register_constraint "Yd"
"TARGET_AVX512DQ ? ALL_SSE_REGS : TARGET_SSE4_1 ? SSE_REGS : NO_REGS"
"@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ
target or any SSE register for SSE4_1 target.")
Comments for "Yd" should mention A
> Date: Mon, 11 Feb 2019 02:05:11 +0100
> From: Hans-Peter Nilsson
> Regtested on cris-elf, where it "introduces" gcc.dg/pr84877.c
Correction: "no regressions" (not introduced by this proposed
patch, I misread).
brgds, H-P
Here's the follow-up, getting rid of the observed
alignment-padding in execute/930126-1.c: the x parameter in f
spuriously being runtime-aligned to BITS_PER_WORD. I separated
this change because this is an older issue, a change introduced
in r94104 where BITS_PER_WORD was chosen perhaps because we
> Date: Thu, 10 Jan 2019 00:06:01 +0100
> From: Jakub Jelinek
> 2019-01-09 Jakub Jelinek
>
> PR middle-end/84877
> PR bootstrap/88450
> * function.c (assign_stack_local_1): Revert the 2018-11-21 changes.
> (assign_parm_setup_block): Do the argument slot realignment her
On Sun, Feb 10, 2019 at 1:49 PM Uros Bizjak wrote:
>
> On Sun, Feb 10, 2019 at 10:45 PM Uros Bizjak wrote:
>
> > > > > + [(const_int 0)]
> > > > > +{
> > > > > + /* Emulate MMX vec_dupv2si with SSE vec_dupv4si. */
> > > > > + rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
> > > > > +
On Fri, Feb 08, 2019 at 04:53:44PM -0600, Segher Boessenkool wrote:
> > @@ -37981,7 +37982,7 @@ rs6000_call_sysv (rtx value, rtx func_desc, rtx
> > tlsarg, rtx cookie)
> >func = rs6000_longcall_ref (func_desc, tlsarg);
> >/* If the longcall was implemented using PLT16 relocs, then
On Wed, 28 Nov 2018 at 22:44, Johannes Pfau wrote:
>
> With these backports, these tests now pass for GDC and we don't
> need the special cases in the Makefiles anymore.
>
> --
> Johannes
>
> ---
> libphobos/ChangeLog:
>
> 2018-11-28 Johannes Pfau
>
> * libdruntime/Makefile.am: Test rt.
Hi,
It is a rebase of a patch sent to this mailing list by Johannes, it
has been committed to upstream druntime, and now downstreaming.
Bootstrapped and regression tested on x86_64-linux-gnu.
Committed to trunk as r268755
--
Iain
---
libphobos/ChangeLog:
2019-02-10 Iain Buclaw
* M
Hi,
I am attaching correct patch.
The option is new only in a relative sense - it was added 5 years ago
with the orinal ODR warning infrastructure.
We have -Wodr-type-merging that controls streming data needed for -Wodr
to work and -fno-devirtualize that controls streaming of BINFOs.
I was conce
Hi Bill,
On Sun, Feb 10, 2019 at 10:10:02AM -0600, Bill Schmidt wrote:
> I've added executable tests for both shift-right algebraic and shift-right
> logical.
> Both fail prior to applying the patch, and work correctly afterwards.
Please add a test for left shifts, as well?
> 2019-02-08 Bill S
On Sun, Feb 10, 2019 at 10:45 PM Uros Bizjak wrote:
> > > > + [(const_int 0)]
> > > > +{
> > > > + /* Emulate MMX vec_dupv2si with SSE vec_dupv4si. */
> > > > + rtx op0 = gen_rtx_REG (V4SImode, REGNO (operands[0]));
> > > > + rtx insn = gen_vec_dupv4si (op0, operands[1]);
> > > > + emit_ins
On Sun, Feb 10, 2019 at 10:01 PM H.J. Lu wrote:
>
> On Sun, Feb 10, 2019 at 2:36 AM Uros Bizjak wrote:
> >
> > On 2/10/19, H.J. Lu wrote:
> > > Emulate MMX vec_dupv2si with SSE. Only SSE register source operand is
> > > allowed.
> > >
> > > PR target/89021
> > > * config/i386/mmx.md
On Thu, 29 Nov 2018 at 11:51, Iain Buclaw wrote:
>
> On Wed, 28 Nov 2018 at 22:44, Johannes Pfau wrote:
> >
> > Hashing of complex types where the floating point type used
> > for the real and imaginary parts has padding (such as X86 80 bit reals)
> > has padding, is currently broken in druntime.
On Sun, Feb 10, 2019 at 2:36 AM Uros Bizjak wrote:
>
> On 2/10/19, H.J. Lu wrote:
> > Emulate MMX vec_dupv2si with SSE. Only SSE register source operand is
> > allowed.
> >
> > PR target/89021
> > * config/i386/mmx.md (*vec_dupv2si): Changed to
> > define_insn_and_split and als
Hi Dilyan,
On Sun, Feb 10, 2019 at 02:45:02PM +, Дилян Палаузов wrote:
> Do you share the opinion, that whatever can be done after receiving a
> reminder, can be arranged also without reminder?
Yes. When people have time for it, they can trivially check what PRs are
still open that they ar
On Sun, Feb 10, 2019 at 9:38 PM H.J. Lu wrote:
>
> On Sun, Feb 10, 2019 at 2:26 AM Uros Bizjak wrote:
> >
> > On 2/10/19, H.J. Lu wrote:
> > > Emulate MMX ashr3/3 with SSE. Only SSE register
> > > source operand is allowed.
> > >
> > > PR target/89021
> > > * config/i386/mmx.md (mmx
On Sun, Feb 10, 2019 at 2:26 AM Uros Bizjak wrote:
>
> On 2/10/19, H.J. Lu wrote:
> > Emulate MMX ashr3/3 with SSE. Only SSE register
> > source operand is allowed.
> >
> > PR target/89021
> > * config/i386/mmx.md (mmx_ashr3): Disallow with
> > TARGET_MMX_WITH_SSE.
> > (m
On Fri, Feb 8, 2019 at 1:24 PM Uros Bizjak wrote:
> Attached patch fixes --enable-frame-pointer handling, and this way
> makes a couple of defines in config/i386/sol2.h obsolete.
It turned out that --enable-frame-pointer does not work for multilibs
at all. So, instead of pretending that -m32 on
On February 10, 2019 11:48:01 AM GMT+01:00, Jan Hubicka wrote:
>>
>> This caused:
>>
>> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89272
>
>My apologizes for that. Fixed by the attached patch. This is about ICE
>with -fno-lto-odr-type-merging which is option I think we should drop
>(probably n
Hi,
build_qualified_type adjusts alignment of atomic types to one of minimal
alignment needed for atomic operations (I think it does so). For packed
structures this leads to type variant to be created and alignment to be
updated later.
If you call again build_qualified_type on packed structures, i
> Hi,
> this patch drops test for TYPE_NEEDS_CONSTRUCTING in tree.h and instead
> sets TREE_READONLY to 0 for external vars of this type. For vars
> declared locally we drop TREE_READONLY while expanding constructor.
> Note that I have tried to drop TREE_READONLY always (not only for
> DECL_EXTERNA
Hello, gentle maintainer.
This is a message from the Translation Project robot.
A revised PO file for textual domain 'gcc' has been submitted
by the French team of translators. The file is available at:
https://translationproject.org/latest/gcc/fr.po
(This file, 'gcc-9.1-b20190203.fr.po',
Hi!
We had a problem report for code attempting to implement a vector right-shift
for a
vector long long (V2DImode) type. The programmer noted that we don't have a
vector
splat-immediate for this mode, but cleverly realized he could use a vector char
splat-immediate since only the lower 6 bits
OK. Thanks for the patch.
Paul
On Wed, 6 Feb 2019 at 20:27, Thomas Koenig wrote:
>
> Hello world,
>
> this patch fixes a 7/8/9 regression where we tried to accept invalid
> code, which led to an ICE later on.
>
> The patch is rather straightforward. The reason why I could not
> use gfc_expr_att
Hello,
thanks to Serger and Joseph for the feedback.
Acting primary upon reminders is a general phenomenon in the society, nothing
specific to software teams. Think on
public administration: it acts sometimes much more collaboratively, if a
public/private/famous media reports on the
workflows
Hi,
This patch is the library fix for a thread deadlock that occurred when
libcurl is missing. It is only one half of the fix for the PR, the
other is for the testsuite scripts to check that libcurl exists before
attempting to run the std.net.curl unittest.
Bootstrapped and tested on x86_64-linu
On 2/10/19, H.J. Lu wrote:
> In 64-bit mode, implement V2SF add/sub/mul with SEE. Only SSE register
> source operand is allowed.
>
> gcc/
>
> PR target/89028
> * config/i386/i386.md (comm): Handle mult.
> * config/i386/mmx.md (plusminusmult): New.
> (plusminusmult_insn): L
On 2/10/19, H.J. Lu wrote:
> PR target/89021
> * config/i386/mmx.md (MMXMODE:mov): Also allow
> TARGET_MMX_WITH_SSE.
> (MMXMODE:*mov_internal): Likewise.
> (MMXMODE:movmisalign): Likewise.
OK.
Uros.
> ---
> gcc/config/i386/mmx.md | 6 +++---
> 1 file changed, 3 in
On 2/10/19, H.J. Lu wrote:
> Emulate MMX abs2 with SSE. Only SSE register source operand is
> allowed.
>
> PR target/89021
> * config/i386/sse.md (abs2): Add SSE emulation.
OK.
Uros.
> ---
> gcc/config/i386/sse.md | 15 +--
> 1 file changed, 9 insertions(+), 6 deletion
On 2/10/19, H.J. Lu wrote:
> Emulate MMX ssse3_psign3 with SSE. Only SSE register source operand
> is allowed.
>
> PR target/89021
> * config/i386/sse.md (ssse3_psign3): Add SSE emulation.
OK.
Uros.
> ---
> gcc/config/i386/sse.md | 18 +++---
> 1 file changed, 11 inser
what about testcases? for these
Original message
From: Uros Bizjak
Date: 10/02/2019 12:26 (GMT+00:00)
To: "H.J. Lu"
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [PATCH 29/43] i386: Emulate MMX ssse3_pmaddubsw with SSE
On 2/10/19, H.J. Lu wrote:
> Emulate MMX ssse3_pmaddu
On 2/10/19, H.J. Lu wrote:
> Emulate MMX ssse3_pmulhrswv4hi3 with SSE. Only SSE register source
> operand is allowed.
>
> PR target/89021
> * config/i386/sse.md (*ssse3_pmulhrswv4hi3): Add SSE emulation.
OK.
Uros.
> ---
> gcc/config/i386/sse.md | 20 +---
> 1 file
On 2/10/19, H.J. Lu wrote:
> Emulate MMX ssse3_pmaddubsw with SSE. Only SSE register source operand
> is allowed.
>
> PR target/89021
> * config/i386/sse.md (ssse3_pmaddubsw): Add SSE emulation.
OK.
Uros.
> ---
> gcc/config/i386/sse.md | 18 +++---
> 1 file changed, 11
On 2/10/19, H.J. Lu wrote:
> Emulate MMX ssse3_phdv2si3 with SSE by moving bits
> 64:95 to bits 32:63 in SSE register. Only SSE register source operand
> is allowed.
>
> PR target/89021
> * config/i386/sse.md (ssse3_phdv2si3):
> Changed to define_insn_and_split to support SSE em
On 2/10/19, H.J. Lu wrote:
> Emulate MMX ssse3_phwv4hi3 with SSE by moving bits
> 64:95 to bits 32:63 in SSE register. Only SSE register source operand
> is allowed.
>
> PR target/89021
> * config/i386/sse.md (ssse3_phwv4hi3):
> Changed to define_insn_and_split to support SSE em
On 2/10/19, H.J. Lu wrote:
> Emulate MMX mmx_uavgv8qi3 with SSE. Only SSE register source operand is
> allowed.
>
> PR target/89021
> * config/i386/mmx.md (mmx_uavgv8qi3): Add SSE emulation support.
> (*mmx_uavgv8qi3): Add SSE emulation.
Please change insn conditions here and u
On 2/10/19, H.J. Lu wrote:
> Emulate MMX umulv1siv1di3 with SSE2. Only SSE register source operand
> is allowed.
>
> PR target/89021
> * config/i386/mmx.md (sse2_umulv1siv1di3): Add SSE emulation
> support.
> (*sse2_umulv1siv1di3): Add SSE2 emulation.
OK.
Uros.
> ---
>
On 2/10/19, H.J. Lu wrote:
> Emulate MMX mmx_umulv4hi3_highpart with SSE. Only SSE register source
> operand is allowed.
>
> PR target/89021
> * config/i386/mmx.md (*mmx_umulv4hi3_highpart): Add SSE emulation.
> ---
> gcc/config/i386/mmx.md | 19 ---
> 1 file changed,
On 2/10/19, H.J. Lu wrote:
> Emulate MMX mmx_pmovmskb with SSE by zero-extending result of SSE pmovmskb
> from QImode to SImode. Only SSE register source operand is allowed.
>
> PR target/89021
> * config/i386/mmx.md (mmx_pmovmskb): Changed to
> define_insn_and_split to support
On 2/10/19, H.J. Lu wrote:
> Emulate MMX mmx_pinsrw with SSE. Only SSE register source operand is
> allowed.
>
> PR target/89021
> * config/i386/mmx.md (mmx_pinsrw): Add SSE emulation.
Please change insn condition,
Uros.
> ---
> gcc/config/i386/mmx.md | 30 +---
On Sat, 2019-02-09 at 23:57 +0100, Svante Signell wrote:
> On Sat, 2019-02-09 at 14:40 -0800, Ian Lance Taylor wrote:
> > On Fri, Feb 8, 2019 at 3:07 PM Matthias Klose wrote:
> > > On 07.02.19 06:04, Ian Lance Taylor wrote:
> > What are the lines before that in the log? For some reason libtool is
On 2/10/19, H.J. Lu wrote:
> Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE. Only SSE register source
> operand is allowed.
>
> PR target/89021
> * config/i386/mmx.md (mmx_v4hi3): Add SSE emulation
> support.
> (mmx_v8qi3): Likewise.
> (smaxmin:v4hi3): New.
> (
On 2/10/19, H.J. Lu wrote:
> Emulate MMX mmx_pextrw with SSE. Only SSE register source operand is
> allowed.
>
> PR target/89021
> * config/i386/mmx.md (mmx_pextrw): Add SSE emulation.
> ---
> gcc/config/i386/mmx.md | 16 +---
> 1 file changed, 9 insertions(+), 7 deletion
On 2/10/19, H.J. Lu wrote:
> Emulate MMX pshufw with SSE. Only SSE register source operand is allowed.
>
> PR target/89021
> * config/i386/mmx.md (mmx_pshufw_1): Add SSE emulation.
> (*vec_dupv4hi): Likewise.
> emulation.
> ---
> gcc/config/i386/mmx.md | 33 ++
Am 06.02.19 um 21:27 schrieb Thomas Koenig:
Hello world,
this patch fixes a 7/8/9 regression where we tried to accept invalid
code, which led to an ICE later on.
The patch is rather straightforward. The reason why I could not
use gfc_expr_attr is that it does not actually return the
flags the
Hello world,
this patch fixes the coarray part of PR 71066 - handling of data
statements for coarrays. The PR itself is marked as a 7/8/9
regression.
Regression-tested. OK for trunk and for backporting?
Regards
Thomas
2019-02-10 Thomas Koenig
PR fortran/71066
On Sun, Feb 10, 2019 at 10:42:55AM +0100, Christophe Lyon wrote:
> > 2019-02-08 Jakub Jelinek
> >
> > PR bootstrap/88714
> > * config/arm/ldrdstrd.md (*arm_ldrd, *arm_strd): Use q constraint
> > instead of r.
> >
>
> Both this simple patch or the previous fix all the ICE
On 2/10/19, H.J. Lu wrote:
> Emulate MMX sse_cvtpi2ps with SSE2 cvtdq2ps, preserving upper 64 bits of
> destination XMM register. Only SSE register source operand is allowed.
>
> PR target/89021
> * config/i386/mmx.md (UNSPEC_CVTPI2PS): New.
> (sse_cvtpi2ps): Renamed to ...
>
On 2/10/19, H.J. Lu wrote:
> Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE.
>
> PR target/89021
> * config/i386/mmx.md (sse_cvtps2pi): Add SSE emulation.
> (sse_cvttps2pi): Likewise.
It looks to me that this description is wrong. We don't have V4SF
modes here, but V2SF, so we
>
> This caused:
>
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89272
My apologizes for that. Fixed by the attached patch. This is about ICE
with -fno-lto-odr-type-merging which is option I think we should drop
(probably next stage1 but if it shows to cause troubles, I would not be
against dro
On 2/10/19, H.J. Lu wrote:
> Emulate MMX vec_dupv2si with SSE. Only SSE register source operand is
> allowed.
>
> PR target/89021
> * config/i386/mmx.md (*vec_dupv2si): Changed to
> define_insn_and_split and also allow TARGET_MMX_WITH_SSE to
> support SSE emulation.
>
On 2/10/19, H.J. Lu wrote:
> Emulate MMX mmx_eq/mmx_gt3 with SSE. Only SSE register source
> operand is allowed.
>
> PR target/89021
> * config/i386/mmx.md (mmx_eq3): Also allow
> TARGET_MMX_WITH_SSE.
> (*mmx_eq3): Also allow TARGET_MMX_WITH_SSE. Add SSE
> support.
On 2/9/19, H.J. Lu wrote:
> Emulate MMX 3 with SSE. Only SSE register source
> operand is allowed.
>
> PR target/89021
> * config/i386/mmx.md (any_logic:3): New.
> (any_logic:*mmx_3): Also allow TARGET_MMX_WITH_SSE.
> Add SSE support.
OK.
Uros.
> ---
> gcc/config/i386/
On 2/9/19, H.J. Lu wrote:
> Emulate MMX mmx_andnot3 with SSE. Only SSE register source operand
> is allowed.
>
> PR target/89021
> * config/i386/mmx.md (mmx_andnot3): Also allow
> TARGET_MMX_WITH_SSE. Add SSE support.
OK.
Uros.
> ---
> gcc/config/i386/mmx.md | 18 ++
On 2/10/19, H.J. Lu wrote:
> Emulate MMX ashr3/3 with SSE. Only SSE register
> source operand is allowed.
>
> PR target/89021
> * config/i386/mmx.md (mmx_ashr3): Disallow with
> TARGET_MMX_WITH_SSE.
> (mmx_3): Likewise.
> (ashr3): New.
> (3): Likewise.
Please
On 2/10/19, H.J. Lu wrote:
> Emulate MMX pmaddwd with SSE. Only SSE register source operand is
> allowed.
>
> PR target/89021
> * config/i386/mmx.md (mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE.
> (*mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE. Add SSE support.
OK.
Uros.
>
On 2/10/19, H.J. Lu wrote:
> Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is
> allowed.
>
> PR target/89021
> * config/i386/mmx.md (mmx_smulv4hi3_highpart): Also allow
> TARGET_MMX_WITH_SSE.
> (*mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. Ad
On 2/9/19, H.J. Lu wrote:
> Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is
> allowed.
>
> PR target/89021
> * config/i386/mmx.md (mulv4hi3): New.
> (*mmx_mulv4hi3): Also allow TARGET_MMX_WITH_SSE. Add SSE
> support.
OK.
Uros.
> ---
> gcc/config/i38
On 2/10/19, H.J. Lu wrote:
> Emulate MMX plusminus/sat_plusminus with SSE. Only SSE register source
> operand is allowed.
>
> PR target/89021
> * config/i386/mmx.md (3): New.
> (*mmx_3): Changed to define_insn_and_split
> to support SSE emulation.
> (*mmx_3): Likewis
On 2/10/19, H.J. Lu wrote:
> Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX. For MMX punpckhXX,
> move bits 64:127 to bits 0:63 in SSE register. Only SSE register source
> operand is allowed.
>
> PR target/89021
> * config/i386/i386-protos.h (ix86_split_mmx_punpck): New
> p
On 2/10/19, Uros Bizjak wrote:
> On 2/10/19, H.J. Lu wrote:
>> Emulate MMX packsswb/packssdw/packuswb with SSE
>> packsswb/packssdw/packuswb
>> plus moving bits 64:95 to bits 32:63 in SSE register. Only SSE register
>> source operand is allowed.
>>
>> 2019-02-08 H.J. Lu
>> Uros Bizja
On 2/10/19, H.J. Lu wrote:
> Emulate MMX packsswb/packssdw/packuswb with SSE packsswb/packssdw/packuswb
> plus moving bits 64:95 to bits 32:63 in SSE register. Only SSE register
> source operand is allowed.
>
> 2019-02-08 H.J. Lu
> Uros Bizjak
>
> PR target/89021
> * co
On Fri, 8 Feb 2019 at 12:40, Jakub Jelinek wrote:
>
> On Fri, Feb 08, 2019 at 11:29:10AM +, Matthew Malcomson wrote:
> > I'm pretty sure there's no difference between the iwmmxt target and
> > others so believe your simpler fix of just using 'q' is a good idea.
> > (there's no difference in ga
On 2/10/19, H.J. Lu wrote:
> In 64-bit mode, SSE2 can be used to emulate MMX instructions without
> 3DNOW. We can use SSE2 to support 64-bit vectors.
>
> PR target/89021
> * config/i386/i386.c (ix86_set_reg_reg_cost): Also support
> VALID_MMX_WITH_SSE_REG_MODE.
> (ix86_vec
Hi,
This patch merges the D front-end implementation with dmd upstream
39edbe17e. Only includes a backport from a latter version, fixing PR
d/88989.
Boostrapped and regression tested on x86_64-linux-gnu.
Committed to trunk as r268740.
--
Iain
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diff --git a/gcc/d/dmd/MERGE b/gcc/d/dmd/MERGE
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