On 2/9/19, H.J. Lu <[email protected]> wrote:
> Emulate MMX mmx_andnot<mode>3 with SSE. Only SSE register source operand
> is allowed.
>
> PR target/89021
> * config/i386/mmx.md (mmx_andnot<mode>3): Also allow
> TARGET_MMX_WITH_SSE. Add SSE support.
OK.
Uros.
> ---
> gcc/config/i386/mmx.md | 18 +++++++++++-------
> 1 file changed, 11 insertions(+), 7 deletions(-)
>
> diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
> index fae2e43af24..1e235bfcde4 100644
> --- a/gcc/config/i386/mmx.md
> +++ b/gcc/config/i386/mmx.md
> @@ -1093,14 +1093,18 @@
> ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
>
> (define_insn "mmx_andnot<mode>3"
> - [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
> + [(set (match_operand:MMXMODEI 0 "register_operand" "=y,Yx,Yy")
> (and:MMXMODEI
> - (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand" "0"))
> - (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
> - "TARGET_MMX"
> - "pandn\t{%2, %0|%0, %2}"
> - [(set_attr "type" "mmxadd")
> - (set_attr "mode" "DI")])
> + (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand" "0,0,Yy"))
> + (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym,Yx,Yy")))]
> + "TARGET_MMX || TARGET_MMX_WITH_SSE"
> + "@
> + pandn\t{%2, %0|%0, %2}
> + pandn\t{%2, %0|%0, %2}
> + vpandn\t{%2, %1, %0|%0, %1, %2}"
> + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
> + (set_attr "type" "mmxadd,sselog,sselog")
> + (set_attr "mode" "DI,TI,TI")])
>
> (define_expand "mmx_<code><mode>3"
> [(set (match_operand:MMXMODEI 0 "register_operand")
> --
> 2.20.1
>
>
