On Sun, Feb 10, 2019 at 2:26 AM Uros Bizjak <ubiz...@gmail.com> wrote:
>
> On 2/10/19, H.J. Lu <hjl.to...@gmail.com> wrote:
> > Emulate MMX ashr<mode>3/<shift_insn><mode>3 with SSE. Only SSE register
> > source operand is allowed.
> >
> > PR target/89021
> > * config/i386/mmx.md (mmx_ashr<mode>3): Disallow with
> > TARGET_MMX_WITH_SSE.
> > (mmx_<shift_insn><mode>3): Likewise.
> > (ashr<mode>3): New.
> > (<shift_insn><mode>3): Likewise.
>
> Please merge patterns use mmx_isa attribute.
Currently, MMX pattern names have a "mmx_" prefix. For SSE emulation, we
don't want such a prefix so that the middle-end can detect and use them. If we
remove the "mmx_" prefix from MMX pattern names, won't the middle-end
generate MMX instructions in this case? It it safe to do so?
> Uros.
>
> > ---
> > gcc/config/i386/mmx.md | 38 ++++++++++++++++++++++++++++++++++++--
> > 1 file changed, 36 insertions(+), 2 deletions(-)
> >
> > diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
> > index 2024c75fa78..9e07bf31f81 100644
> > --- a/gcc/config/i386/mmx.md
> > +++ b/gcc/config/i386/mmx.md
> > @@ -995,7 +995,7 @@
> > (ashiftrt:MMXMODE24
> > (match_operand:MMXMODE24 1 "register_operand" "0")
> > (match_operand:DI 2 "nonmemory_operand" "yN")))]
> > - "TARGET_MMX"
> > + "TARGET_MMX && !TARGET_MMX_WITH_SSE"
> > "psra<mmxvecsize>\t{%2, %0|%0, %2}"
> > [(set_attr "type" "mmxshft")
> > (set (attr "length_immediate")
> > @@ -1009,7 +1009,7 @@
> > (any_lshift:MMXMODE248
> > (match_operand:MMXMODE248 1 "register_operand" "0")
> > (match_operand:DI 2 "nonmemory_operand" "yN")))]
> > - "TARGET_MMX"
> > + "TARGET_MMX && !TARGET_MMX_WITH_SSE"
> > "p<vshift><mmxvecsize>\t{%2, %0|%0, %2}"
> > [(set_attr "type" "mmxshft")
> > (set (attr "length_immediate")
> > @@ -1018,6 +1018,40 @@
> > (const_string "0")))
> > (set_attr "mode" "DI")])
> >
> > +(define_insn "ashr<mode>3"
> > + [(set (match_operand:MMXMODE24 0 "register_operand" "=x,Yv")
> > + (ashiftrt:MMXMODE24
> > + (match_operand:MMXMODE24 1 "register_operand" "0,Yv")
> > + (match_operand:DI 2 "nonmemory_operand" "xN,YvN")))]
> > + "TARGET_MMX_WITH_SSE"
> > + "@
> > + psra<mmxvecsize>\t{%2, %0|%0, %2}
> > + vpsra<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
> > + [(set_attr "isa" "noavx,avx")
> > + (set_attr "type" "sseishft,sseishft")
> > + (set (attr "length_immediate")
> > + (if_then_else (match_operand 2 "const_int_operand")
> > + (const_string "1")
> > + (const_string "0")))
> > + (set_attr "mode" "TI")])
> > +
> > +(define_insn "<shift_insn><mode>3"
> > + [(set (match_operand:MMXMODE248 0 "register_operand" "=x,Yv")
> > + (any_lshift:MMXMODE248
> > + (match_operand:MMXMODE248 1 "register_operand" "0,Yv")
> > + (match_operand:DI 2 "nonmemory_operand" "xN,YvN")))]
> > + "TARGET_MMX_WITH_SSE"
> > + "@
> > + p<vshift><mmxvecsize>\t{%2, %0|%0, %2}
> > + vp<vshift><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
> > + [(set_attr "isa" "noavx,avx")
> > + (set_attr "type" "sseishft,sseishft")
> > + (set (attr "length_immediate")
> > + (if_then_else (match_operand 2 "const_int_operand")
> > + (const_string "1")
> > + (const_string "0")))
> > + (set_attr "mode" "TI")])
> > +
> > ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
> > ;;
> > ;; Parallel integral comparisons
> > --
> > 2.20.1
> >
> >
--
H.J.
