On 2/10/19, H.J. Lu <[email protected]> wrote:
> Emulate MMX plusminus/sat_plusminus with SSE. Only SSE register source
> operand is allowed.
>
> PR target/89021
> * config/i386/mmx.md (<plusminus_insn><mode>3): New.
> (*mmx_<plusminus_insn><mode>3): Changed to define_insn_and_split
> to support SSE emulation.
> (*mmx_<plusminus_insn><mode>3): Likewise.
> (mmx_<plusminus_insn><mode>3): Also allow TARGET_MMX_WITH_SSE.
> ---
> gcc/config/i386/mmx.md | 49 +++++++++++++++++++++++++++++-------------
> 1 file changed, 34 insertions(+), 15 deletions(-)
>
> diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
> index ff9c5dc8507..32920343fcf 100644
> --- a/gcc/config/i386/mmx.md
> +++ b/gcc/config/i386/mmx.md
> @@ -698,34 +698,53 @@
> "TARGET_MMX || (TARGET_SSE2 && <MODE>mode == V1DImode)"
> "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
>
> +(define_expand "<plusminus_insn><mode>3"
> + [(set (match_operand:MMXMODEI 0 "register_operand")
> + (plusminus:MMXMODEI
> + (match_operand:MMXMODEI 1 "nonimmediate_operand")
> + (match_operand:MMXMODEI 2 "nonimmediate_operand")))]
> + "TARGET_MMX_WITH_SSE"
> + "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
> +
> (define_insn "*mmx_<plusminus_insn><mode>3"
> - [(set (match_operand:MMXMODEI8 0 "register_operand" "=y")
> + [(set (match_operand:MMXMODEI8 0 "register_operand" "=y,x,Yv")
> (plusminus:MMXMODEI8
> - (match_operand:MMXMODEI8 1 "nonimmediate_operand" "<comm>0")
> - (match_operand:MMXMODEI8 2 "nonimmediate_operand" "ym")))]
> - "(TARGET_MMX || (TARGET_SSE2 && <MODE>mode == V1DImode))
> + (match_operand:MMXMODEI8 1 "nonimmediate_operand" "<comm>0,0,Yv")
> + (match_operand:MMXMODEI8 2 "nonimmediate_operand" "ym,x,Yv")))]
> + "(TARGET_MMX
> + || TARGET_MMX_WITH_SSE
> + || (TARGET_SSE2 && <MODE>mode == V1DImode))
Please change MMXMODEI8 iterator to:
> +(define_mode_iterator MMXMODEI8 [V8QI V4HI V2SI (V1DI "TARGET_SSE2")])
as was done in the previous version and use only
(TARGET_MMX || TARGET_MMX_WITH_SSE) && ...
here.
> && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
> - "p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}"
> - [(set_attr "type" "mmxadd")
> - (set_attr "mode" "DI")])
> + "@
> + p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
> + p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
> + vp<plusminus_mnemonic><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
> + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
> + (set_attr "type" "mmxadd,sseadd,sseadd")
> + (set_attr "mode" "DI,TI,TI")])
>
> (define_expand "mmx_<plusminus_insn><mode>3"
> [(set (match_operand:MMXMODE12 0 "register_operand")
> (sat_plusminus:MMXMODE12
> (match_operand:MMXMODE12 1 "nonimmediate_operand")
> (match_operand:MMXMODE12 2 "nonimmediate_operand")))]
> - "TARGET_MMX"
> + "TARGET_MMX || TARGET_MMX_WITH_SSE"
> "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
>
> (define_insn "*mmx_<plusminus_insn><mode>3"
> - [(set (match_operand:MMXMODE12 0 "register_operand" "=y")
> + [(set (match_operand:MMXMODE12 0 "register_operand" "=y,x,Yv")
> (sat_plusminus:MMXMODE12
> - (match_operand:MMXMODE12 1 "nonimmediate_operand" "<comm>0")
> - (match_operand:MMXMODE12 2 "nonimmediate_operand" "ym")))]
> - "TARGET_MMX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
> - "p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}"
> - [(set_attr "type" "mmxadd")
> - (set_attr "mode" "DI")])
> + (match_operand:MMXMODE12 1 "nonimmediate_operand" "<comm>0,0,Yv")
> + (match_operand:MMXMODE12 2 "nonimmediate_operand" "ym,x,Yv")))]
> + "(TARGET_MMX || TARGET_MMX_WITH_SSE)
> + && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
> + "@
> + p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
> + p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
> + vp<plusminus_mnemonic><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
> + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
> + (set_attr "type" "mmxadd,sseadd,sseadd")
> + (set_attr "mode" "DI,TI,TI")])
>
> (define_expand "mmx_mulv4hi3"
> [(set (match_operand:V4HI 0 "register_operand")
> --
> 2.20.1
>
>
