addhi_operand" "%0 ,rim,r")
>(match_operand:HI 2 "cool_addhi_operand" "rim,0 ,r")))]
> ""
Do you have an option where operand 0 is reg and operand 1 is mem and
operand 2 is reg?
I am not sure what rim is for?
Shafi
--
View this message in context:
http://www.nabble.com/insn-does-not-satisfy-its-constraints-tp19211080p19218836.html
Sent from the gcc - Dev mailing list archive at Nabble.com.
Hello all,
Can anyone tell me where i can find the definition of tree.
One structure is typedef-ed to tree. But i cant find that structure.
I have been hunting it for sometime.
Can some one help me.
Thanks in advance.
Regards,
Shafi
Hello all,
During regression tests if i want to disable some features like trampolines i
can give -DNO_TRAMPOLINES
as an compiler flag.
Do i have similar flags for profiling and PIC?
thanks in advance
Regards,
Shafi
Hello all,
For targets which doesn't have simd hardware support like fr30 , simd stuff is
emulated?
Is there some flags/macros in gcc to indicate that?
How is it done in other targets which deosnt have the hardware support?
Thanks in advance
Regards,
Shafi.
target hook TARGET_VECTOR_MODE_SUPPORTED_P hep me to indicate that?
Guess this is the right mailing list for my question.
Thanks in advance.
Regards,
Shafi.
- Original Message
From: Ian Lance Taylor <[EMAIL PROTECTED]>
To: Mohamed Shafi <[EMAIL PROTECTED]>
Cc: gcc@gcc.
(clobber (reg:CC 21 cc))
]) -1 (nil)
(nil))
Will i be able to find this pattern in .md files?
what does insn 8 6 9 1 mean?
reg/f ?
for varible declaration why is it needed to clobber CC?
Hope somebody will help me.
Thanks in advance.
Regards,
Shafi
t;
int main()
{
if (!(t.bit++))
exit (0);
else
abort ();
}
is -1 for my target. Can you explain this?
Thanks in advance.
Regards,
Shafi
- Original Message
From: Rask Ingemann Lambertsen <[EMAIL PROTECTED]>
To: Mohamed Shafi <[EMAIL PROTECTED]>
Cc: gcc@g
> It is because matching has not yet been attempted.
ok.. so what is the option to get hold of a rtl dump after all the matching is
done
- Original Message
From: Rask Ingemann Lambertsen <[EMAIL PROTECTED]>
To: Mohamed Shafi <[EMAIL PROTECTED]>
Cc: gcc@gcc.gnu.org
dundant codes or is
there a way to disable them?
Thanks in advance.
Regards,
Shafi.
Hello all,
Can anybody tell me the purpose of the testcase
testsuite\gcc.dg\special\gcsec-1.c in the gcc testsuite ?
Is it something related with garbage clooection?
What exactly doec this testcase test ?
Thanks in advance.
Regards ,
Shafi.
file name . why is it needed and what is 42?
In line 8 what does [0 A8] mean?
Thanks in advance,
Regards,
shafi
Hello all,
Looking at a .md file of a backend it there a way to know whether a
target supports long long
Should i look for patterns with machine mode DI?
Is there some other way?
Thanks in advance for the help.
Regards,
Shafi
:
On Mon, Nov 06, 2006 at 10:52:00AM +0530, Mohamed Shafi wrote:
> Hello all,
>
> Looking at a .md file of a backend it there a way to know whether a
> target supports long long
> Should i look for patterns with machine mode DI?
No. For example, 8-bit, 16-bit and 32-bit targets
On 11/7/06, Mike Stump <[EMAIL PROTECTED]> wrote:
On Nov 6, 2006, at 9:30 PM, Mohamed Shafi wrote:
> My target (non gcc/private one) fails for long long testcases
Does it work flawlessly otherwise, if not, fix all those problems
first. After those are all fixed, then you can see if
registers befor the use? After some pass they are not seen in the
dump.
Regards,
Shafi.
On 11/10/06, Mike Stump <[EMAIL PROTECTED]> wrote:
On Nov 9, 2006, at 6:39 AM, Mohamed Shafi wrote:
> When i diff the rtl dumps for programs passing negative value with and
> without frame pointer i find changes from file.greg .
A quick glance at the rtl shows that insn 95 tries
h in gcc 4.1.1?
Regards,
Shafi
t or define_insns or define_expand for DI mode, how
can i control the instructions generated due to reload?
Regards,
Shafi
d them out.
The following messages should help you out
http://gcc.gnu.org/ml/gcc/2006-08/msg00451.html
http://gcc.gnu.org/ml/gcc-help/2006-08/msg00213.html
Hope this helps.
Regards,
Shafi
ot;\n Shafi Debugging!!\n");
#endif
compiling 1.c:
gcc -DSHAFI_DEBUG 1.c
Is there any way to do this ?
Thanks in advance
Regards,
Shafi
Hello all,
In arithmetic expressions we need to conversion when the operands are
of different data types.
In gcc 4.1.1 where is this process started?
Is this in c-typeck.c, particularly in the function c_common_type ?
Thanks in advance,
Regards,
Shafi.
ther way?
One other question is that i am getting "test for excess errors" Fails
for some cases which produce lot of warnings but otherwise proper.
Can anyone help me?
Thanks in advance.
Regards,
Shafi.
this, one can only override the option and cannot provide one if
none is given
Is there anyway to do this?
Regards,
Shafi.
satisfy why is that the compiler is not trying to match the
constraint by generating a mova2b pattern? Is there something
that i am missing here?
Regards,
Shafi
"data_reg" "d"))]
"REGNO(operands[0]) == REGNO(operands[3])"
"movf\\t%1, %3"
)
even i wrote define_peephole2 which is similar to the above.
But the above patterns are not matched at all. But i can find these
patterns in the rtl dumps.
What could be the reason for this behavior?
Regards,
Shafi
On 4/12/07, Andreas Schwab <[EMAIL PROTECTED]> wrote:
"Mohamed Shafi" <[EMAIL PROTECTED]> writes:
> hello everyone,
>
> I have the following 2 patterns which are consecutive. (from shorten
> rtl dump file)
>
> (insn 69 34 70 (set (reg:SQ 0 d0)
>
the offset
is 4 if long long is mapped to TI mode and i want the generate the
offset such that it is 2.
Is there a way to do this in gcc ?
Regards,
Shafi
On 4/16/07, J.C. Pizarro <[EMAIL PROTECTED]> wrote:
2007/4/16, Mohamed Shafi <[EMAIL PROTECTED]>:
> hello all,
>
> Depending on the machine mode the compiler will generate automatically
> the offset required for the stack operation i.e for a machine with
> word si
On 4/16/07, J.C. Pizarro <[EMAIL PROTECTED]> wrote:
2007/4/16, Mohamed Shafi <[EMAIL PROTECTED]> wrote:
> > > Depending on the machine mode the compiler will generate automatically
> > > the offset required for the stack operation i.e for a machine with
> >
is is a 32bit
char target ? Can somebody help me with pointers to debug this issue?
Regards,
Shafi
On 10 February 2011 15:57, Richard Guenther wrote:
> On Thu, Feb 10, 2011 at 6:23 AM, Mohamed Shafi wrote:
>> Hi all,
>>
>> I am trying to port a private target in GCC 4.5.1. Following are the
>> properties of the target
>>
>> #define BITS_PER_UNIT
On 10 February 2011 17:16, Richard Guenther wrote:
> On Thu, Feb 10, 2011 at 12:42 PM, Mohamed Shafi wrote:
>> On 10 February 2011 15:57, Richard Guenther
>> wrote:
>>> On Thu, Feb 10, 2011 at 6:23 AM, Mohamed Shafi wrote:
>>>> Hi all,
>>>>
opied directly from
OLDEQUIV since this seems highly unlikely. */
gcc_assert (rl->secondary_in_reload < 0);
How can i overcome this failure? Can some one suggest a solution?
Thanks for the help.
Regards,
Shafi
On 11 February 2011 15:28, Paulo J. Matos wrote:
>
>
> On 11/02/11 09:46, Mohamed Shafi wrote:
>>
>> How can i overcome this failure? Can some one suggest a solution?
>>
>
>
> Have you defined TARGET_LEGITIMATE_ADDRESS_P and also BASE_REG_CLASS
> corr
loop counter being set to 0 in the body of the loop.
Can someone suggest me solution to get out of this?
Regards,
Shafi
ulling, the
annul bit will be cleared.
For each insn that is merged, if the branch is or will be non-annulling,
we delete the merged insn. */
I think REGOUT dependency of g1 between instructions 38 and 43 in the
delay slot is not being considered by 'try_merge_delay_insns'.
Is this a bug?
Regards,
Shafi
On 6 September 2011 20:50, Jeff Law wrote:
>
> On 09/06/11 08:46, Mohamed Shafi wrote:
>> Hi,
>>
>> I am doing a private port in GCC 4.5.1. For the my target i see some
>> strange behavior in delay slot scheduling. For my target the
>> instruction in the delay
I suspect that this is a GCC issue.
Can some one give me some pointers to resolve this issue?
Regards,
Shafi
assing so that R6 contains the msw and R7
contains lsw, regardless of the endianess mode.
Regards,
Shafi
?
Regards,
Shafi
checked with the mainline internals. Even
there the references of these deleted variables are not replaced.
Could somebody please take care of this.
Regards,
Shafi
2009/7/18 Ian Lance Taylor :
> Mohamed Shafi writes:
>
>> The change logs says that current_function_outgoing_args_size is no
>> more available. But it doesnt say with what it is replaced. Looking at
>> the other targets i find that its replaced with some field in a
>
2009/7/18 Dave Korn :
> Mohamed Shafi wrote:
>> Hello all,
>>
>> Is it possible to emit a assembler directive at the end of each sections?
>> Say like section_end
>> Is there any support for doing something like this in the back-end files?
>> Or should i need
2009/8/1 Dave Korn :
> Mohamed Shafi wrote:
>> I am looking for adding something to the end of each section in the
>> generated .s file. Using TARGET_ASM_NAMED_SECTION i will be able to
>> keep track of the sections that are being emitted. But from
>> TARGET_ASM_FILE_
2009/8/1 Dave Korn :
> Mohamed Shafi wrote:
>> 2009/8/1 Dave Korn :
>>> Mohamed Shafi wrote:
>>>> I am looking for adding something to the end of each section in the
>>>> generated .s file. Using TARGET_ASM_NAMED_SECTION i will be able to
>>>>
for this
#define PARM_BOUNDARY 8
#define STACK_BOUNDARY 64
I have also defined STACK_SLOT_ALIGNMENT. but this is not affecting the output.
What should i be doing to get the required alignment?
Regards,
Shafi
2009/8/3 Jim Wilson :
> On 08/03/2009 02:14 AM, Mohamed Shafi wrote:
>>
>> short - 2 bytes
>> i am not able to implement the alignment for short.
>> The following is are the macros that i used for this
>> #define PARM_BOUNDARY 8
>> #define STACK_BOUNDAR
2009/8/5 Jim Wilson :
> On Tue, 2009-08-04 at 11:09 +0530, Mohamed Shafi wrote:
>> >> i am not able to implement the alignment for short.
>> >> The following is are the macros that i used for this
>> >> #define PARM_BOUNDARY 8
>> >> #define STACK
instruction but only in
store instruction. So how can i implement this? Should i do a
define_expand for movQi3 and force it to a register when i get this
addressing mode?
Please let me know your thoughts on this.
Regards,
shafi
2009/7/3 Ian Lance Taylor :
> Mohamed Shafi writes:
>
>> I just want to know about the feasibility of implementing an
>> instruction for a port in gcc 4.4
>> The target has 40 bit register where the normal load/store/move
>> instructions will be able to access t
could i be missing here? Should i add anything specific for this
in the back-end?
Regards,
Shafi
2009/7/16 Richard Henderson :
> On 07/13/2009 07:35 AM, Mohamed Shafi wrote:
>>
>> So i made both TARGET_STRICT_ARGUMENT_NAMING and
>> PRETEND_OUTGOING_VARARGS_NAMED to return false. Is this correct?
>
> Yes.
>
>> How to make the varargs argument to be p
uot;
)
As you can see i have tried combinations. Since i was looking for
pattern matching i didnt bother to write according to the target.
Thought i will do that after i get a matching pattern. When i debugged
GCC was generating patterns with multiply. But that gets discarded
since md file doesnt have those patterns. How can i make GCC generate
shift and add pattern? Is GCC generating patterns with multiply due to
cost issues? I havent mentioned any cost details.
Regards,
Shafi
qi} (nil))
main1.c:11: internal compiler error: in reload_cse_simplify_operands,
at postreload.c:396
So what am i doing wrong?
Cant this scenario be solved by the reload pass?
How can generate instructions with the QImode restriction?
Regards,
Shafi
have compare instruction after the function call for FP
compare. Is there a way to let GCC know that the result for FP compare
are stored in the Status Register so that GCC generates directly a
jump operation? How can i implement this?
Regards,
Shafi
works for O0. But with optimizations i am getting
ICE. It seems that GCC won't accept unspec object in destination
operand. So how can split the pattens for the load and store for these
data types?
Regards,
Shafi
(pc))) 77 {compare_and_branch_insn} (expr_list:REG_DEAD (reg:QI 84)
(expr_list:REG_BR_PROB (const_int 200 [0xc8])
(nil
After reload pass:
(jump_insn 58 56 59 10 20070129.c:73 (set (pc)
(if_then_else (leu:CC (reg:QI 17 r1 [84])
(const_int 1 [0x1]))
(label_ref 87)
(pc))) 77 {compare_and_branch_insn} (expr_list:REG_BR_PROB
(const_int 200 [0xc8])
(nil)))
How can i overcome this error?
Thanks for your help.
Regards,
Shafi
GS is set.
assign_temp is called because STRICT_ALIGNMENT && PARM_BOUNDARY <
GET_MODE_ALIGNMENT (DImode) is true
Can somebody please confirm whether this is due to some mistake in my
port or a GCC bug?
Thanks,
Shafi
cases
when reload fixes the add pattern and those are when either the
destination is address register or there is no stack pointer involved.
But otherwise i am getting this ICE. I am not sure how to over come
this,.
Hope someone suggests me a solution.
Regards,
Shafi
P.S Can i have commutative op
G_RTX_P (op0)
&& BASE_REG_RTX_P (op0, strict));
...
...
My question is my definition of strict correct?
or should it be reload_in_progress || reload_completed?
Regards,
Shafi
2009/9/30 Richard Henderson :
> On 09/29/2009 07:32 AM, Mohamed Shafi wrote:
>>
>> My question is my definition of strict correct?
>> or should it be reload_in_progress || reload_completed?
>
> I'm tempted to say it should be the later, but I'm not sure i
2009/9/30 Richard Henderson :
> On 09/29/2009 09:46 PM, Mohamed Shafi wrote:
>>
>> bool strict = reload_completed ? true : false;
>
> What happens if you set "strict = false" here?
> That's what ARM does.
That particular case works, and yes arm does
2009/9/28 Richard Henderson :
> On 09/28/2009 07:25 AM, Mohamed Shafi wrote:
>>
>> Hope someone suggests me a solution.
>
> The solution is almost certainly something involving the
> TARGET_SECONDARY_RELOAD hook. You need to inform reload that it's going to
> need
2009/9/14 Richard Henderson :
> On 09/14/2009 07:24 AM, Mohamed Shafi wrote:
>>
>> Hello all,
>>
>> I am doing a port for a 32bit target in GCC 4.4.0. I have to support a
>> 40bit data (_Accum) in the port. The target has 40bit registers which
>> is a GPR and
milarly there are other operation that requires sign/zero extension.
So is there any way to tell GCC that the data registers are 40bit and
there by expect it to generate sign/zero extension accordingly ?
Regards,
Shafi
target options and the caller does not use the same options.
But looking in the sources i think this really should have been
TARGET_OPTION_CAN_INLINE_P
Shafi.
d in R6 and R7, R6 containing the most significant long
word and R7 containing the least significant long word, regardless of
the endianess mode. How can i do this in the DF compare pattern?
Regards,
Shafi
_int -100 [0xff9c]))) 16 {addqi3}
(expr_list:REG_DEAD (reg:SI 61 [ s ])
(nil)))
How can i prevent this ICE ?
Regards,
Shafi
2009/10/22 Richard Henderson :
> On 10/21/2009 07:25 AM, Mohamed Shafi wrote:
>>
>> For accessing a->b GCC generates the following code:
>>
>> move.l (sp-16), d3
>> lsrr.l #<16, d3
>> move.l (sp-12),d2
>> asll #&
2009/10/30 Jeff Law :
> On 10/30/09 07:13, Mohamed Shafi wrote:
>>
>> Hi,
>>
>> I am doing a port for a 32bit target in GCC 4.4.0. The target does not
>> have support for symbolic address in QImode for load operations.
>
> You'll need to make
2009/10/30 Ian Lance Taylor :
> Mohamed Shafi writes:
>
>>>From ice4.c.168r.asmcons
>>
>> (insn 5 2 6 2 ice4.c:4 (set (reg:SI 61 [ s ])
>> (mem/c/i:SI (symbol_ref:SI ("s") [flags 0x2] > 0xb7bfd000 s>) [0 s+0 S4 A32])) 2 {*movsi_internal} (n
2009/11/6 Richard Henderson :
> On 11/06/2009 05:29 AM, Mohamed Shafi wrote:
>>
>> The target that i am working on has 1& 2 bit shift-add patterns.
>> GCC is not generating shift-add patterns when the shift count is 1. It
>> is currently generating add ope
2009/11/6 Ian Lance Taylor :
> Mohamed Shafi writes:
>
>> It is generating with data registers. Here is the pattern that i have
>> written:
>>
>>
>> (define_insn "*saddl"
>> [(set (match_operand:SI 0 "register_operand" "=r,d&quo
2009/10/22 Richard Henderson :
> On 10/21/2009 07:25 AM, Mohamed Shafi wrote:
>>
>> For accessing a->b GCC generates the following code:
>>
>> move.l (sp-16), d3
>> lsrr.l #<16, d3
>> move.l (sp-12),d2
>> asll #&
h_dup 2)] UNSPEC_REG_LOW)
(unspec:HI [(match_dup 1)] UNSPEC_REG_LOW]
""
)
But in few testcases this is creating problems. So i would like to
know better patterns to split mulsi3 pattern.
Can someone help me out.
Regards,
Shafi
2009/11/10 Richard Henderson :
> On 11/10/2009 05:48 AM, Mohamed Shafi wrote:
>>
>> (define_insn "mulsi3"
>> [(set (match_operand:SI 0 "register_operand" "=&d")
>> (mult:SI (match_operand:SI 1 "register_operand&
native solution that i can
try. All i can think is to flag an insn for unsigned operation so that
i will be able to insert sign/zero extension during say reorg pass.
Can this be implemented? How feasible is this?
Regards,
Shafi
2009/12/18 Hans-Peter Nilsson :
> On Fri, 20 Nov 2009, Mohamed Shafi wrote:
>> I tried implementing the suggestion given by Richard, but got into
>> issues. The GCC frame work is written assuming that there are no modes
>> with HOST_BITS_PER_WIDE_INT < GET
en this problem should go away. I
havent check this. But i dont want to do that, since this means that i
will have to change all the dependencies that are affected by this
change. Is there any other solution for my problem?
Any help is appreciated.
Regards,
Shafi
y different operand combinartions?
>
> Yes, but that is often better, I suspect, than having too fancy a
> pattern that breaks the optimization simplifications that genrecog does.
>
> Note that the attributes that were requested could be made part of the
> iterator as well, using a mode_attribute.
>
I can't find a back-end that does this. Can you show me a example?
Regards,
Shafi
able this addressing
mode till reload is completed. */
if (!reload_completed && mode == QImode && BASE_REG_RTX_P
(base, strict))
return 0;
I haven't run the testsuite, but Is this ok to have like this?
Please let me know your thoughts on this.
Thanks for your time.
Regards
Shafi
2010/1/22 Richard Henderson :
> On 01/21/2010 06:22 AM, Mohamed Shafi wrote:
>>
>> Hello all,
>>
>> I am doing a port for a 32bit a target in GCC 4.4.0. The target
>> supports (base + offset) addressing mode for QImode store instructions
>> but not for QIm
I 16 r0)
(const_int 65536 [0x1])) [4 S4 A32])
(reg:SI 2 d2)) -1 (nil))
Is there something wrong with my legitimize_relaod_address?
Thanks for your time.
Regards,
shafi
register. Looking into
the gcc sources I find that this is done with the help of REG_OFFSET
macro. So can I use this macro to identify a register as a part of
multiword register? Is there any other way to do this?
Regards,
Shafi
Hi all,
Does GCC support architectures that has Variable Length Execution Set (VLES)?
Are there any developments happening in this direction?
Regards,
Shafi
2009/5/27 Ian Lance Taylor :
> Mohamed Shafi writes:
>
>> Does GCC support architectures that has Variable Length Execution Set (VLES)?
>> Are there any developments happening in this direction?
>
> gcc supports many instruction sets whose instructions are not all the
&g
register. Hope i make myself clear.
Will it be possible to implement this in the gcc back-end so that the
particular instruction is supported?
Regards,
Shafi
defaults to the value of
CALL_USED_REGISTERS.
But it doesn't say why one needs to use this.
What is the need for the macro CALL_REALLY_USED_REGISTERS when
compared to CALL_USED_REGISTERS?
regards,
Shafi
port
this target?
Regards,
Shafi
sign and zero ext instructions along with the
above instructions?
It would be of great help if you could guide me in deciding these instructions.
Regards,
Shafi
(mem/f/c/i:QI (reg:QI 28 a0) [0 f+0 S1 A32])) 9 {movqi_op} (nil))
insn 45 is redundant. Is this generated because the
legitimize_reload_address is wrong?
Any hints as to why the redundant instruction gets generated?
Regards,
Shafi
On 29 October 2010 00:06, Joern Rennecke wrote:
> Quoting Mohamed Shafi :
>
>> Hi,
>>
>> I am doing a port in GCC 4.5.1. For the port
>>
>> 1. there is only (reg + offset) addressing mode only when reg is SP.
>> Other base registers are not allowed
>&
On 30 October 2010 05:45, Joern Rennecke wrote:
> Quoting Mohamed Shafi :
>
>> On 29 October 2010 00:06, Joern Rennecke
>> wrote:
>>>
>>> Quoting Mohamed Shafi :
>>>
>>>> Hi,
>>>>
>>>> I am doing a port in GCC 4
e let me know your thoughts on this and the reason for
choosing it?
Regards,
Shafi
roperly. I ICE
goes away when i write the constraints as:
"=ad", "Wd"
or
"a,a,d,d," , "W,W,d,d"
So i have the following questions:
1. Why is that constraints are not matched here?
2. When can i combine the constrains?
Regards,
Shafi
On 12 November 2010 18:39, Joern Rennecke wrote:
> Quoting Mohamed Shafi :
>
>> So i have the following questions:
>>
>> 1. Why is that constraints are not matched here?
>
> Please read the node "Register Classes" in doc/tm.texi .
>
I am sorry , coul
On 30 October 2010 05:45, Joern Rennecke wrote:
> Quoting Mohamed Shafi :
>
>> On 29 October 2010 00:06, Joern Rennecke
>> wrote:
>>>
>>> Quoting Mohamed Shafi :
>>>
>>>> Hi,
>>>>
>>>> I am doing a port in GCC 4
mes 0 and hence breaks out and returns. Due to this
compiler crashes with "insn does not satisfy its constraints:" error.
Any pointers in fixing this?
Regards,
Shafi
P.S. When can we merge constraints? What are the criteria to decide
which all constraints to merge
On 20 December 2010 10:56, Jeff Law wrote:
> On 12/15/10 07:14, Mohamed Shafi wrote:
>>
>> Hi,
>>
>> I am doing a port in GCC 4.5.1.
>> The target supports storing immediate values into memory location
>> represented by a symbolic address. So in the move
On 20 December 2010 19:30, Jeff Law wrote:
> On 12/20/10 01:47, Mohamed Shafi wrote:
>>
>>
>>> I think this is a case where you're going to need a secondary reload to
>>> force the immediate into a register if the destination is a non-symbolic
>>>
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