Hello all,
I am doing a port for a 32bit target in GCC 4.4.0. I have to support a
40bit data (_Accum) in the port. The target has 40bit registers which
is a GPR and works as 32bit reg in other modes. The load and store for
_Accum happens in two step. The lower 32bit in one instruction and the
upper 8bit in the next instruction. I want to split the instruction
after reload. I tired to have a pattern (for load) like this:
(define_insn "fn_load_ext_sa"
[(set (unspec:SA [(match_operand:DA 0 "register_operand" "")]
UNSPEC_FN_EXT)
(match_operand:SA 1 "memory_operand" ""))]
(define_insn "fn_load_sa"
[(set (unspec:SA [(match_operand:DA 0 "register_operand" "")]
UNSPEC_FN)
(match_operand:SA 1 "memory_operand" ""))]
The above patterns works for O0. But with optimizations i am getting
ICE. It seems that GCC won't accept unspec object in destination
operand. So how can split the pattens for the load and store for these
data types?
Regards,
Shafi
