>Hi All,
> I am getting the error message bellow while hacking my gcc backend.
>Any suggestions on how to fix this?
>
>error: insn does not satisfy its constraints:
>(insn 25 50 26 2 (set (reg:HI 1 %r0 [33])
> (plus:HI (mem/s/j:HI (plus:HI (reg:HI 3 %r2)
> (reg/v/f:HI 11 %i2h [orig:28 cell ] [28])) [0
><variable>.dod S2 A8])
> (reg:HI 1 %r0 [43]))) 8 {*addhi3} (insn_list:REG_DEP_TRUE 3
>(insn_list:REG_DEP_TRUE 24 (nil)))
> (nil))
>
Operand 0 is a register
Operand 1 is a memory
Operand 2 is a register
>
>The md description for this instruction is:
>
>;; addhi3
>(define_expand "addhi3"
> [(set (match_operand:HI 0 "register_operand" "")
> (plus:HI (match_operand:HI 1 "cool_addhi_operand" "")
> (match_operand:HI 2 "cool_addhi_operand" "")))]
> ""
> "")
>
>(define_insn "*addhi3"
> [(set (match_operand:HI 0 "register_operand" "=r ,r ,r")
> (plus:HI (match_operand:HI 1 "cool_addhi_operand" "%0 ,rim,r")
> (match_operand:HI 2 "cool_addhi_operand" "rim,0 ,r")))]
> ""
Do you have an option where operand 0 is reg and operand 1 is mem and
operand 2 is reg?
I am not sure what rim is for?
Shafi
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