Re: ICE with MEM_REF when Pmode is different from word_mode

On 29 May 2012 17:31, Richard Guenther wrote: > On Tue, May 29, 2012 at 1:57 PM, Mohamed Shafi wrote: >> Hi, >> >> I am porting a private target in GCC 4.6.3 version. For my target >> pointer size is 24bits and word size is 32bits. Moreover a byte is >> 32bit >

ICE with MEM_REF when Pmode is different from word_mode

rg1 are different, one is Pmode and other is word_mode. This is present in m32c target which also has different Pmode and word_mode. Is this a know failure? I cannot find a bug entry for this issue. Should i report this? Regards, Shafi

Re: Reloading going wrong. Bug in GCC?

ping !!!. Any help on http://gcc.gnu.org/ml/gcc/2011-09/msg00150.html shafi On 14 September 2011 15:07, Mohamed Shafi wrote: > Hi, > > I am working on a 32bit private target which has the following restriction > > 1. store/load can happen only through a general purpose registe

Restricting with Multilib

ibgcc cpu3/libgcc libgcc That includes i variant for each cpu and a default version. Is there any way to restrict GCC from building the default version? Regards, Shafi

Reloading going wrong. Bug in GCC?

I suspect that this is a GCC issue. Can some one give me some pointers to resolve this issue? Regards, Shafi

Re: Issue with delay slot scheduling?

On 6 September 2011 20:50, Jeff Law wrote: > > On 09/06/11 08:46, Mohamed Shafi wrote: >> Hi, >> >> I am doing a private port in GCC 4.5.1. For the my target i see some >> strange behavior in delay slot scheduling. For my target the >> instruction in the delay

Issue with delay slot scheduling?

ulling, the annul bit will be cleared. For each insn that is merged, if the branch is or will be non-annulling, we delete the merged insn. */ I think REGOUT dependency of g1 between instructions 38 and 43 in the delay slot is not being considered by 'try_merge_delay_insns'. Is this a bug? Regards, Shafi

How to generate loop counter with a different mode ?

loop counter being set to 0 in the body of the loop. Can someone suggest me solution to get out of this? Regards, Shafi

Re: Reloading an auto-increment addresses

On 11 February 2011 15:28, Paulo J. Matos wrote: > > > On 11/02/11 09:46, Mohamed Shafi wrote: >> >> How can i overcome this failure?  Can some one suggest a solution? >> > > > Have you defined TARGET_LEGITIMATE_ADDRESS_P and also BASE_REG_CLASS > corr

Reloading an auto-increment addresses

opied directly from OLDEQUIV since this seems highly unlikely. */ gcc_assert (rl->secondary_in_reload < 0); How can i overcome this failure? Can some one suggest a solution? Thanks for the help. Regards, Shafi

Re: ICE in get_constraint_for_component_ref

On 10 February 2011 17:16, Richard Guenther wrote: > On Thu, Feb 10, 2011 at 12:42 PM, Mohamed Shafi wrote: >> On 10 February 2011 15:57, Richard Guenther >> wrote: >>> On Thu, Feb 10, 2011 at 6:23 AM, Mohamed Shafi wrote: >>>> Hi all, >>>>

Re: ICE in get_constraint_for_component_ref

On 10 February 2011 15:57, Richard Guenther wrote: > On Thu, Feb 10, 2011 at 6:23 AM, Mohamed Shafi wrote: >> Hi all, >> >> I am trying to port a private target in GCC 4.5.1. Following are the >> properties of the target >> >> #define BITS_PER_UNIT        

ICE in get_constraint_for_component_ref

is is a 32bit char target ? Can somebody help me with pointers to debug this issue? Regards, Shafi

Re: Help with reloading

On 20 December 2010 19:30, Jeff Law wrote: > On 12/20/10 01:47, Mohamed Shafi wrote: >> >> >>> I think this is a case where you're going to need a secondary reload to >>> force the immediate into a register if the destination is a non-symbolic >>>

Re: Help with reloading

On 20 December 2010 10:56, Jeff Law wrote: > On 12/15/10 07:14, Mohamed Shafi wrote: >> >> Hi, >> >> I am doing a port in GCC 4.5.1. >> The target supports storing immediate values into memory location >> represented by a symbolic address. So in the move

Help with reloading

mes 0 and hence breaks out and returns. Due to this compiler crashes with "insn does not satisfy its constraints:" error. Any pointers in fixing this? Regards, Shafi P.S. When can we merge constraints? What are the criteria to decide which all constraints to merge

Re: Help with reloading FP + offset addressing mode

On 30 October 2010 05:45, Joern Rennecke wrote: > Quoting Mohamed Shafi : > >> On 29 October 2010 00:06, Joern Rennecke >> wrote: >>> >>> Quoting Mohamed Shafi : >>> >>>> Hi, >>>> >>>> I am doing a port in GCC 4

Re: A question about combining constraints

On 12 November 2010 18:39, Joern Rennecke wrote: > Quoting Mohamed Shafi : > >> So i have the following questions: >> >> 1. Why is that constraints are not matched here? > > Please read the node "Register Classes" in doc/tm.texi . > I am sorry , coul

A question about combining constraints

roperly. I ICE goes away when i write the constraints as: "=ad", "Wd" or "a,a,d,d," , "W,W,d,d" So i have the following questions: 1. Why is that constraints are not matched here? 2. When can i combine the constrains? Regards, Shafi

Opinion on a hardware feature for conditional instructions

e let me know your thoughts on this and the reason for choosing it? Regards, Shafi

Re: Help with reloading FP + offset addressing mode

On 30 October 2010 05:45, Joern Rennecke wrote: > Quoting Mohamed Shafi : > >> On 29 October 2010 00:06, Joern Rennecke >> wrote: >>> >>> Quoting Mohamed Shafi : >>> >>>> Hi, >>>> >>>> I am doing a port in GCC 4

Re: Help with reloading FP + offset addressing mode

On 29 October 2010 00:06, Joern Rennecke wrote: > Quoting Mohamed Shafi : > >> Hi, >> >> I am doing a port in GCC 4.5.1. For the port >> >> 1. there is only (reg + offset) addressing mode only when reg is SP. >> Other base registers are not allowed >&

Help with reloading FP + offset addressing mode

    (mem/f/c/i:QI (reg:QI 28 a0) [0 f+0 S1 A32])) 9 {movqi_op} (nil)) insn 45 is redundant. Is this generated because the legitimize_reload_address is wrong? Any hints as to why the redundant instruction gets generated? Regards, Shafi

Need help in deciding the instruction set for a new target.

sign and zero ext instructions along with the above instructions? It would be of great help if you could guide me in deciding these instructions. Regards, Shafi

Help for target with BITS_PER_UNIT = 16

port this target? Regards, Shafi

how to identify a part of a multi-word register

register. Looking into the gcc sources I find that this is done with the help of REG_OFFSET macro. So can I use this macro to identify a register as a part of multiword register? Is there any other way to do this? Regards, Shafi

How to write legitimize_reload_address

I 16 r0) (const_int 65536 [0x1])) [4 S4 A32]) (reg:SI 2 d2)) -1 (nil)) Is there something wrong with my legitimize_relaod_address? Thanks for your time. Regards, shafi

Re: Question about peephole2 and addressing mode

2010/1/22 Richard Henderson : > On 01/21/2010 06:22 AM, Mohamed Shafi wrote: >> >> Hello all, >> >> I am doing a port for a 32bit a target in GCC 4.4.0. The target >> supports (base + offset) addressing mode for QImode store instructions >> but not for QIm

Question about peephole2 and addressing mode

able this addressing mode till reload is completed. */ if (!reload_completed && mode == QImode && BASE_REG_RTX_P (base, strict)) return 0; I haven't run the testsuite, but Is this ok to have like this? Please let me know your thoughts on this. Thanks for your time. Regards Shafi

Re: How to implement pattens with more that 30 alternatives

y different operand combinartions? > > Yes, but that is often better, I suspect, than having too fancy a > pattern that breaks the optimization simplifications that genrecog does. > > Note that the attributes that were requested could be made part of the > iterator as well, using a mode_attribute. > I can't find a back-end that does this. Can you show me a example? Regards, Shafi

How to implement pattens with more that 30 alternatives

en this problem should go away. I havent check this. But i dont want to do that, since this means that i will have to change all the dependencies that are affected by this change. Is there any other solution for my problem? Any help is appreciated. Regards, Shafi

Re: How to support 40bit GP register - Take two

2009/12/18 Hans-Peter Nilsson : > On Fri, 20 Nov 2009, Mohamed Shafi wrote: >> I tried implementing the suggestion given by Richard, but got into >> issues. The GCC frame work is written assuming that there are no modes >> with HOST_BITS_PER_WIDE_INT < GET

How to support 40bit GP register - Take two

native solution that i can try. All i can think is to flag an insn for unsigned operation so that i will be able to insert sign/zero extension during say reorg pass. Can this be implemented? How feasible is this? Regards, Shafi

Re: How to split mulsi3 pattern

2009/11/10 Richard Henderson : > On 11/10/2009 05:48 AM, Mohamed Shafi wrote: >> >> (define_insn "mulsi3" >>  [(set (match_operand:SI 0 "register_operand"           "=&d") >>       (mult:SI (match_operand:SI 1 "register_operand&

How to split mulsi3 pattern

h_dup 2)] UNSPEC_REG_LOW) (unspec:HI [(match_dup 1)] UNSPEC_REG_LOW] "" ) But in few testcases this is creating problems. So i would like to know better patterns to split mulsi3 pattern. Can someone help me out. Regards, Shafi

Re: How to support 40bit GP register

2009/10/22 Richard Henderson : > On 10/21/2009 07:25 AM, Mohamed Shafi wrote: >> >> For accessing a->b GCC generates the following code: >> >>        move.l  (sp-16), d3 >>        lsrr.l  #<16, d3 >>        move.l  (sp-12),d2 >>        asll    #&

Re: How to write shift and add pattern?

2009/11/6 Ian Lance Taylor : > Mohamed Shafi writes: > >> It is generating with data registers. Here is the pattern that i have >> written: >> >> >> (define_insn "*saddl" >>   [(set (match_operand:SI 0 "register_operand" "=r,d&quo

Re: How to write shift and add pattern?

2009/11/6 Richard Henderson : > On 11/06/2009 05:29 AM, Mohamed Shafi wrote: >> >>     The target that i am working on has 1&  2 bit shift-add patterns. >> GCC is not generating shift-add patterns when the shift count is 1. It >> is currently generating add ope

Re: IRA is not looking into the predicates ?

2009/10/30 Ian Lance Taylor : > Mohamed Shafi writes: > >>>From ice4.c.168r.asmcons >> >> (insn 5 2 6 2 ice4.c:4 (set (reg:SI 61 [ s ]) >>         (mem/c/i:SI (symbol_ref:SI ("s") [flags 0x2] > 0xb7bfd000 s>) [0 s+0 S4 A32])) 2 {*movsi_internal} (n

Re: IRA is not looking into the predicates ?

2009/10/30 Jeff Law : > On 10/30/09 07:13, Mohamed Shafi wrote: >> >> Hi, >> >> I am doing a port for a 32bit target in GCC 4.4.0. The target does not >> have support for symbolic address in QImode for load operations. > > You'll need to make

Re: How to support 40bit GP register

2009/10/22 Richard Henderson : > On 10/21/2009 07:25 AM, Mohamed Shafi wrote: >> >> For accessing a->b GCC generates the following code: >> >>        move.l  (sp-16), d3 >>        lsrr.l  #<16, d3 >>        move.l  (sp-12),d2 >>        asll    #&

IRA is not looking into the predicates ?

_int -100 [0xff9c]))) 16 {addqi3} (expr_list:REG_DEAD (reg:SI 61 [ s ]) (nil))) How can i prevent this ICE ? Regards, Shafi

Re: Supporting FP cmp lib routines

d in R6 and R7, R6 containing the most significant long word and R7 containing the least significant long word, regardless of the endianess mode. How can i do this in the DF compare pattern? Regards, Shafi

Typo in internals

target options and the caller does not use the same options. But looking in the sources i think this really should have been TARGET_OPTION_CAN_INLINE_P Shafi.

How to support 40bit GP register

milarly there are other operation that requires sign/zero extension. So is there any way to tell GCC that the data registers are 40bit and there by expect it to generate sign/zero extension accordingly ? Regards, Shafi

Re: How to split 40bit data types load/store?

2009/9/14 Richard Henderson : > On 09/14/2009 07:24 AM, Mohamed Shafi wrote: >> >> Hello all, >> >> I am doing a port for a 32bit target in GCC 4.4.0. I have to support a >> 40bit data (_Accum) in the port. The target has 40bit registers which >> is a GPR and

Re: Reload going wrong for addition.

2009/9/28 Richard Henderson : > On 09/28/2009 07:25 AM, Mohamed Shafi wrote: >> >> Hope someone suggests me a solution. > > The solution is almost certainly something involving the > TARGET_SECONDARY_RELOAD hook.  You need to inform reload that it's going to > need

Re: define_memory_constraint and REG_OK_STRICT

2009/9/30 Richard Henderson : > On 09/29/2009 09:46 PM, Mohamed Shafi wrote: >> >>  bool strict =  reload_completed ? true : false; > > What happens if you set "strict = false" here? > That's what ARM does. That particular case works, and yes arm does

Re: define_memory_constraint and REG_OK_STRICT

2009/9/30 Richard Henderson : > On 09/29/2009 07:32 AM, Mohamed Shafi wrote: >> >> My question is my definition of strict correct? >> or should it be reload_in_progress || reload_completed? > > I'm tempted to say it should be the later, but I'm not sure i

define_memory_constraint and REG_OK_STRICT

G_RTX_P (op0) && BASE_REG_RTX_P (op0, strict)); ... ... My question is my definition of strict correct? or should it be reload_in_progress || reload_completed? Regards, Shafi

Reload going wrong for addition.

cases when reload fixes the add pattern and those are when either the destination is address register or there is no stack pointer involved. But otherwise i am getting this ICE. I am not sure how to over come this,. Hope someone suggests me a solution. Regards, Shafi P.S Can i have commutative op

Segmentation fault when calling a library fun - GCC bug?

GS is set. assign_temp is called because STRICT_ALIGNMENT && PARM_BOUNDARY < GET_MODE_ALIGNMENT (DImode) is true Can somebody please confirm whether this is due to some mistake in my port or a GCC bug? Thanks, Shafi

How to implement compare and branch instruction

(pc))) 77 {compare_and_branch_insn} (expr_list:REG_DEAD (reg:QI 84) (expr_list:REG_BR_PROB (const_int 200 [0xc8]) (nil After reload pass: (jump_insn 58 56 59 10 20070129.c:73 (set (pc) (if_then_else (leu:CC (reg:QI 17 r1 [84]) (const_int 1 [0x1])) (label_ref 87) (pc))) 77 {compare_and_branch_insn} (expr_list:REG_BR_PROB (const_int 200 [0xc8]) (nil))) How can i overcome this error? Thanks for your help. Regards, Shafi

How to split 40bit data types load/store?

works for O0. But with optimizations i am getting ICE. It seems that GCC won't accept unspec object in destination operand. So how can split the pattens for the load and store for these data types? Regards, Shafi

Supporting FP cmp lib routines

have compare instruction after the function call for FP compare. Is there a way to let GCC know that the result for FP compare are stored in the Status Register so that GCC generates directly a jump operation? How can i implement this? Regards, Shafi

Reloading is going wrong?

qi} (nil)) main1.c:11: internal compiler error: in reload_cse_simplify_operands, at postreload.c:396 So what am i doing wrong? Cant this scenario be solved by the reload pass? How can generate instructions with the QImode restriction? Regards, Shafi

How to write shift and add pattern?

uot; ) As you can see i have tried combinations. Since i was looking for pattern matching i didnt bother to write according to the target. Thought i will do that after i get a matching pattern. When i debugged GCC was generating patterns with multiply. But that gets discarded since md file doesnt have those patterns. How can i make GCC generate shift and add pattern? Is GCC generating patterns with multiply due to cost issues? I havent mentioned any cost details. Regards, Shafi

Re: Function argument passing

2009/7/16 Richard Henderson : > On 07/13/2009 07:35 AM, Mohamed Shafi wrote: >> >> So i made both TARGET_STRICT_ARGUMENT_NAMING and >> PRETEND_OUTGOING_VARARGS_NAMED to return false. Is this correct? > > Yes. > >> How to make the varargs argument to be p

DI mode and endianess

could i be missing here? Should i add anything specific for this in the back-end? Regards, Shafi

Re: About feasibility of implementing an instruction

2009/7/3 Ian Lance Taylor : > Mohamed Shafi writes: > >> I just want to know about the feasibility of implementing an >> instruction for a port in gcc 4.4 >> The target has 40 bit register where the normal load/store/move >> instructions will be able to access t

Restrictive addressing mode

instruction but only in store instruction. So how can i implement this? Should i do a define_expand for movQi3 and force it to a register when i get this addressing mode? Please let me know your thoughts on this. Regards, shafi

Re: How to set the alignment

2009/8/5 Jim Wilson : > On Tue, 2009-08-04 at 11:09 +0530, Mohamed Shafi wrote: >> >> i am not able to implement the alignment for short. >> >> The following is are the macros that i used for this >> >> #define PARM_BOUNDARY 8 >> >> #define STACK

Re: How to set the alignment

2009/8/3 Jim Wilson : > On 08/03/2009 02:14 AM, Mohamed Shafi wrote: >> >> short - 2 bytes >> i am not able to implement the alignment for short. >> The following is are the macros that i used for this >> #define PARM_BOUNDARY 8 >> #define STACK_BOUNDAR

How to set the alignment

for this #define PARM_BOUNDARY 8 #define STACK_BOUNDARY 64 I have also defined STACK_SLOT_ALIGNMENT. but this is not affecting the output. What should i be doing to get the required alignment? Regards, Shafi

Re: Output sections

2009/8/1 Dave Korn : > Mohamed Shafi wrote: >> 2009/8/1 Dave Korn : >>> Mohamed Shafi wrote: >>>> I am looking for adding something to the end of each section in the >>>> generated .s file. Using TARGET_ASM_NAMED_SECTION i will be able to >>>>

Re: Output sections

2009/8/1 Dave Korn : > Mohamed Shafi wrote: >> I am looking for adding something to the end of each section in the >> generated .s file. Using TARGET_ASM_NAMED_SECTION i will be able to >> keep track of the sections that are being emitted. But from >> TARGET_ASM_FILE_

Re: Output sections

2009/7/18 Dave Korn : > Mohamed Shafi wrote: >> Hello all, >> >> Is it possible to emit a assembler directive at the end of each sections? >> Say like section_end >> Is there any support for doing something like this in the back-end files? >> Or should i need

Re: current_function_outgoing_args_size

2009/7/18 Ian Lance Taylor : > Mohamed Shafi writes: > >> The change logs says that current_function_outgoing_args_size is no >> more available. But it doesnt say with what it is replaced. Looking at >> the other targets i find that its replaced with some field in a >

current_function_outgoing_args_size

checked with the mainline internals. Even there the references of these deleted variables are not replaced. Could somebody please take care of this. Regards, Shafi

Output sections

? Regards, Shafi

Function argument passing

assing so that R6 contains the msw and R7 contains lsw, regardless of the endianess mode. Regards, Shafi

CALL_USED_REGISTERS vs CALL_REALLY_USED_REGISTERS

defaults to the value of CALL_USED_REGISTERS. But it doesn't say why one needs to use this. What is the need for the macro CALL_REALLY_USED_REGISTERS when compared to CALL_USED_REGISTERS? regards, Shafi

About feasibility of implementing an instruction

register. Hope i make myself clear. Will it be possible to implement this in the gcc back-end so that the particular instruction is supported? Regards, Shafi

Re: Variable Length Execution Set?

2009/5/27 Ian Lance Taylor : > Mohamed Shafi writes: > >> Does GCC support architectures that has Variable Length Execution Set (VLES)? >> Are there any developments happening in this direction? > > gcc supports many instruction sets whose instructions are not all the &g

Variable Length Execution Set?

Hi all, Does GCC support architectures that has Variable Length Execution Set (VLES)? Are there any developments happening in this direction? Regards, Shafi

Re: insn does not satisfy its constraints

- Original Message > From: Omar Torres <[EMAIL PROTECTED]> > To: [EMAIL PROTECTED] > Cc: gcc@gcc.gnu.org > Sent: Saturday, August 30, 2008 12:11:36 AM > Subject: Re: insn does not satisfy its constraints > > shafi wrote: > >Operand 0 is a regi

Re: insn does not satisfy its constraints

addhi_operand" "%0 ,rim,r") >(match_operand:HI 2 "cool_addhi_operand" "rim,0 ,r")))] > "" Do you have an option where operand 0 is reg and operand 1 is mem and operand 2 is reg? I am not sure what rim is for? Shafi -- View this message in context: http://www.nabble.com/insn-does-not-satisfy-its-constraints-tp19211080p19218836.html Sent from the gcc - Dev mailing list archive at Nabble.com.

Need a pointer for debugging

246 224 26 18 "" [0 uses]) ;; End of basic block 26, registers live: (nil) " Note that if i compile a code which has SImode EQ comparisons the basic blocks and code is generated properly. Right now i am stuck in debugging. Could anybody please provide me with any pointers? Regards, Shafi

ICE in flow.c - Gcc 4.1.2 private port

initialized and prologue will set stack space accordingly. Based on the live information 'propagate_one_insn()' is trying to delete the insn from the prologue. My question is is gcc suppose to delete insn 9, even before prologue generation ? If its not the case where am i going wrong? Regards, Shafi

What are the functions that i can use?

of the instruction. Could any one tell me the functions that i can use to find out whether an register is being used and/or defined in a particular instruction? Regards, Shafi

Re: A question about varargs

2008/7/16 Ian Lance Taylor <[EMAIL PROTECTED]>: > "Mohamed Shafi" <[EMAIL PROTECTED]> writes: > >> I am involved in the porting of gcc 4.1.2 for 16 bit target. For this >> target size of long long is 32bits. For the following code >> >> #defi

A question about varargs

g function shouldn't the mode of the argument be SImode instead of DImode since long long is only 32bit for the target? Regards, Shafi

Re: Is this the expected behavior?

nt registers, caller save registers and finally the callee save registers. > > > cheers > Ramana >> >>> >>> HTH. >>> >>> >>> cheers >>> Ramana >>> >>> On Tue, Jul 15, 2008 at 7:50 AM, Mohamed Shafi <[EMAIL PROT

Re: Is this the expected behavior?

that GCC has used only the argument registers, stack pointer and callee saved registers. So out of the 16 available registers ony 5+1+4 registers were used, even though there was 6 caller save registers were available > > HTH. > > > cheers > Ramana > > On Tue, Jul 15, 2008

Is this the expected behavior?

other function? Or is this a gcc bug? Hope my question is clear. Regards, Shafi

Re: How to get signedness from rtx?

s that for some processing during comparison i need to know whether is the char operand is signed or unsigned. So i guess i can get this looking at what type of comparison is. But if the comparison code is EQ or NE will i be able to get the information? Shafi

How to get signedness from rtx?

Hello all, Is there a way to know whether an operand is signed or unsigned from its rtx? Regards, Shafi

How to identify comparison of 8bit operands

comparison of sign-extended 8bit values are proper. So i can use the normal comparison for char and the modified one for 16bit values. So my question is in the back-end will i be able to identify between comparisons of signed-extended 8bit and 16bit operands? Regards, Shafi

How to implement conditional execution

set any status flags. Will it be possible to implement this in the Gcc backend ? Does any other targets have similar instructions? Regards, Shafi

Re: Can register rename pass rename a callee-saved register?

2008/6/20 Andrew Pinski <[EMAIL PROTECTED]>: > On Thu, Jun 19, 2008 at 11:56 PM, Mohamed Shafi <[EMAIL PROTECTED]> wrote: >> Can you tell me what was done in gcc 4.3 so that i can back port >> the changes to gcc 4.1.2 > > It was a rewrite of life information of

Re: Can register rename pass rename a callee-saved register?

2008/6/19 Ian Lance Taylor <[EMAIL PROTECTED]>: > "Mohamed Shafi" <[EMAIL PROTECTED]> writes: > >>> Which version of gcc? I was under the impression that this >>> longstanding buglet was cleaned up by the dataflow work. >>> >> &

Re: Can register rename pass rename a callee-saved register?

2008/6/19 Ian Lance Taylor <[EMAIL PROTECTED]>: > "Mohamed Shafi" <[EMAIL PROTECTED]> writes: > >> Before register renaming pass, callee registers was being used in the >> body of the code. Hence function prologue saved the register and >> epilogue res

Can register rename pass rename a callee-saved register?

patterns instead of the target macros. So is the rename pass allowed to rename a callee saved register? Where might this going wrong? Thanks for you help. Regards, Shafi

Re: How to write pattern for addition with carry operation

ructions add and addc? >> > > You can look into config/i386.md, how i.e. adddi3 is expanded and split in > case of !TARGET_64BIT. But is it scheduling safe? I mean you can't have addc executed before add. If i am right there will be no dependency between the two instructions. So there can be a case where addc gets scheduled before add. Am i right on both counts? Regards, Shafi

How to write pattern for addition with carry operation

will have add %0, %1\naddc %N0, %N1 sub %0, %1\nsubc %N0, %N1 Will it be possible for me to write separate patterns for the instructions add and addc? Regards, Shafi

How to insert nops

re nop gets inserted when it's not really required. How will it be possible to solve this issue? Regards, Shafi

Implementing a restrictive addressing mode for a gcc port - Take 2

for movqi will generate SImode register, reg28 and does the operations. But this is not reflected in the subsequent instructions (insn 14). And hence insn 13 is getting deleted as its operands are never used. What i am i doing wrong? Am i implementing the addressing mode properly? Any help is appreciated. Regards, Shafi

Re: Few question regarding the implementation of splitting HImode patterns

On Sat, May 24, 2008 at 12:26 AM, Omar Torres <[EMAIL PROTECTED]> wrote: > Mohamed Shafi wrote: >> Hello Omar, >> >> I saw your mail to gcc mailing list regarding splitting of HImode >> patterns into QImode patterns. I am also involved in porting. My >> pro

How to specify registers constraints for memory operands?

nd" "R00,R02,R04,R06,R08,R12,R14,m"))] Is this the proper way to do this? Thank you for taking the time to read this. Regards, Shafi

Re: How to legitimize the reload address?

On Wed, May 21, 2008 at 1:42 AM, Jeff Law <[EMAIL PROTECTED]> wrote: > Ian Lance Taylor wrote: >> >> "Mohamed Shafi" <[EMAIL PROTECTED]> writes: >> >>> For the 16 bit target that i am currently porting can have only >>> positive offset

  1   2   >