Hi Hugo,
On Fri, Nov 21, 2025 12:57 PM, Chris Brandt wrote:
> On Fri, Nov 21, 2025 12:02 PM, Hugo Villeneuve wrote:
> > > Pieces of code are reused all the time. So I think it is better to
> > > make sure it doesn't overflow on 32-bit.
> >
> > Here is a
a simple quotient (intin) and remainder (fracin).
Let me try out your code with different boards and resolutions and see if it
matches the excel sheet I use to verify all the math/registers.
If it's the same, then I'll put it in V6 (which is ready to go as soon as we
fix this last part)
Thanks,
Chris
> this?
I've got no comment here.
I can't image when someone would ever want to compile this code for a 32-bit
system.
So I'll leave it as it is now unless Geert wants me to change it to something
else.
Chris
d, you can see it is always used to calculate the PLL regardless of odd/even.
But, only when you need to calculate the DIV_A,B, you might have that extra 1/2
divide in there.
Thanks for pointing this out.which made me realize my diagram was wrong.
Chris
even more
> clear, and simply reusing their values in rzg2l_cpg_div_ab...
The hardware manual says in DPI mode, "set divider to 1/2, 1/4, or 1/8".
So, then if you look at the code and it has:
rzg2l_cpg_dsi_div_set_divider(8, PLL5_TARGET_DPI);
That makes sense to me. It's doing exactly what the hardware manual told you to
do at a high level.
Other places later in the code it will figure out how to turn that into 'a' and
'b', but there is no need to worry about that yet.
That was my thinking.
Chris
ons offer more safety. Just s/u8/u8 divider/ should fix
> the W=1 issue.
Yes, that was a mistake/typo on my part. Oops.
I'll be fixing that for my next submission.
At the moment, I'm moving to the "renesas-clk" repo/branch because Biju
mentioned my patchset does not apply cleanly.
Chris
From: Chris Morgan
Add support for the HDMI port for the Gameforce Ace. The HDMI port
has no HPD pin present (the manufacturer's devicetree states the pin
is reused for an additional face button) so add the attribute of
no-hpd to poll for connected devices.
Signed-off-by: Chris M
From: Chris Morgan
Add an attribute of "no-hpd" for the Rockchip dw-hdmi-qp controller.
This is used to describe implementations where the HPD pin is not
connected or used for other purposes, such as in the RK3588S based
Gameforce Ace which repurposed the GPIO for an additional face
bu
From: Chris Morgan
Add support for the dw-hdmi-qp driver to handle devices with missing
HPD pins.
Since in this situation we are now polling for the EDID data via i2c
change the error message to a rate limited debug message when we are
unable to complete an i2c read, as a disconnected device
From: Chris Morgan
Add support for the micro HDMI port for the Gameforce Ace. This port does
not have a HPD pin so it requires making changes to the HDMI controller
to support this configuration.
Changes since v1:
- Simplified checking of no-hpd parameter and changed to
On Wed, Nov 19, 2025 at 07:49:23PM +0200, Cristian Ciocaltea wrote:
> On 11/19/25 6:24 PM, Chris Morgan wrote:
> > On Wed, Nov 19, 2025 at 10:02:23AM +0100, Maxime Ripard wrote:
> >> On Tue, Nov 18, 2025 at 02:36:09PM -0600, Chris Morgan wrote:
> >>> On Tue, No
On Wed, Nov 19, 2025 at 10:02:23AM +0100, Maxime Ripard wrote:
> On Tue, Nov 18, 2025 at 02:36:09PM -0600, Chris Morgan wrote:
> > On Tue, Nov 18, 2025 at 09:46:04AM +0100, Maxime Ripard wrote:
> > > Hi,
> > >
> > > On Thu, Nov 13, 2025 at 01:29:38PM -0600, Chr
Before the MIPI DSI clock source can be configured, the target divide
ratio needs to be known.
Signed-off-by: Chris Brandt
Reviewed-by: Biju Das
Tested-by: Biju Das
---
v1->v2:
- Add spaces around '/' in comments
- Add target argument in new API
v2->v3:
- Add missing period
Convert the limited MIPI clock calculations to a full range of settings
based on math including H/W limitation validation.
Since the required DSI division setting must be specified from external
sources before calculations, expose a new API to set it.
Signed-off-by: Chris Brandt
Reviewed-by
rrect div round macro"
Chris Brandt (2):
clk: renesas: rzg2l: Remove DSI clock rate restrictions
drm: renesas: rz-du: mipi_dsi: Set DSI divider
drivers/clk/renesas/rzg2l-cpg.c | 162 +++---
.../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c| 21 ++-
include
On Tue, Nov 18, 2025 at 09:46:04AM +0100, Maxime Ripard wrote:
> Hi,
>
> On Thu, Nov 13, 2025 at 01:29:38PM -0600, Chris Morgan wrote:
> > From: Chris Morgan
> >
> > Add support for the dw-hdmi-qp driver to handle devices with missing
> > HPD pins.
> >
From: Chris Morgan
Add support for the dw-hdmi-qp driver to handle devices with missing
HPD pins.
Since in this situation we are now polling for the EDID data via i2c
change the error message to a debug message when we are unable to
complete an i2c read, as a disconnected device would otherwise
From: Chris Morgan
Add an attribute of "no-hpd" for the Rockchip dw-hdmi-qp controller.
This is used to describe implementations where the HPD pin is not
connected or used for other purposes, such as in the RK3588S based
Gameforce Ace which repurposed the GPIO for an additional face
bu
From: Chris Morgan
Add support for the HDMI port for the Gameforce Ace. The HDMI port
has no HPD pin present (the manufacturer's devicetree states the pin
is reused for an additional face button) so add the attribute of
no-hpd to poll for connected devices.
Signed-off-by: Chris M
From: Chris Morgan
Add support for the micro HDMI port for the Gameforce Ace. This port does
not have a HPD pin so it requires making changes to the HDMI controller
to support this configuration.
Changes since v1:
- Simplified checking of no-hpd parameter and changed to
-EINVAL, so I can do that as
well.
> > - priv->mux_dsi_div_params.clksrc = 1; /* Use clk src 1 for DSI */
> > - priv->mux_dsi_div_params.dsi_div_a = 1; /* Divided by 2 */
> > - priv->mux_dsi_div_params.dsi_div_b = 2; /* Divided by 3 */
> > + /* Default settings for DPI */
> > + priv->mux_dsi_div_params.clksrc = 0;
> > + priv->mux_dsi_div_params.dsi_div_a = 3; /* Divided by 8 */
> > + priv->mux_dsi_div_params.dsi_div_b = 0; /* Divided by 1 */
> > + dsi_div_ab_desired = 8; /* (1 << a) * (b + 1) */
>
> Use inline function rzg2l_cpg_div_ab() previously suggested.
I plan on getting rid of this code block anyway.
It's not needed.
Cheers
Chris
DSI divider based on...
Done.
> By using an intermediate bpp variable, you can avoid a useless second call to
> mipi_dsi_pixel_format_to_bpp():
Done.
Cheers
Chris
are using the same number of lanes as the
Renesas eval board.
I'm trying to fix support for lanes = 3,2,1
Thank you,
Chris
arams.dsi_div_b = 0; /* Divided by 1 */
- dsi_div_ab_desired = 8; /* (1 << a) * (b + 1) */
+ rzg2l_cpg_dsi_div_set_divider(8, PLL5_TARGET_DPI);
I just did some testing with DPI and DSI, and so far everything works the same.
What do you think???
Chris
/scm/linux/kernel/git/geert/renesas-devel.git
I have been testing with v6-18-rc2 (I have not pulled in the latest yet)
Chris
0.clock-controller: hsclk out of range
I'm pretty sure you are using 4 lanes, and a 24-bit panel, but what is the vclk
of your display?
I want to check out the math.
Thank you,
Chris
(EXTAL_FREQ_IN_MEGA_HZ *
MEGA);
+ if (params->pl5_intin < PLL5_INTIN_MIN + 1 ||
+ params->pl5_intin > PLL5_INTIN_MAX - 1)
+ continue;
was wrong.
I forgot to mention that in the patch. :)
Thanks,
Chris
the driver that we have been using for the last couple
years.
Cheers
Chris
t; It seems to me that pl5_intin type should be modified to account for its
> maximum value (u16?), and this should probably goes into a separate patch
> (with a Fixed: tag), that can be backported (if necessary).
You are totally right!
INTIN is a 12-bit register value.
It's a bug.
Good catch.
I'll make that a separate patch so I can CC stable.
Chris
On Thu, Nov 06, 2025 at 08:40:55PM +0100, Heiko Stuebner wrote:
> Am Donnerstag, 6. November 2025, 19:09:13 Mitteleuropäische Normalzeit
> schrieb Chris Morgan:
> > From: Chris Morgan
> >
> > Add support for the dw-hdmi-qp driver to handle devices with missing
> &g
From: Chris Morgan
Add support for the dw-hdmi-qp driver to handle devices with missing
HPD pins.
Since in this situation we are now polling for the EDID data via i2c
change the error message to a debug message when we are unable to
complete an i2c read, as a disconnected device would otherwise
From: Chris Morgan
Add support for the HDMI port for the Gameforce Ace. The HDMI port
has no HPD pin present (the manufacturer's devicetree states the pin
is reused for an additional face button) so add the attribute of
no_hpd to poll for connected devices.
Signed-off-by: Chris M
From: Chris Morgan
Add an attribute of "no-hpd" for the Rockchip dw-hdmi-qp controller.
This is used to describe implementations where the HPD pin is not
connected or used for other purposes, such as in the RK3588S based
Gameforce Ace which repurposed the GPIO for an additional face
bu
From: Chris Morgan
Add support for the micro HDMI port for the Gameforce Ace. This port does
not have a HPD pin so it requires making changes to the HDMI controller
to support this configuration.
Chris Morgan (3):
dt-bindings: display: rockchip: Add no-hpd for dw-hdmi-qp controller
drm
Before the MIPI DSI clock source can be configured, the target divide
ratio needs to be known.
Signed-off-by: Chris Brandt
Reviewed-by: Biju Das
Tested-by: Biju Das
---
v1->v2:
- Add spaces around '/' in comments
- Add target argument in new API
v2->v3:
- Add missing period
Convert the limited MIPI clock calculations to a full range of settings
based on math including H/W limitation validation.
Since the required DSI division setting must be specified from external
sources before calculations, expose a new API to set it.
Signed-off-by: Chris Brandt
Reviewed-by
, multiple resolutions
Chris Brandt (2):
clk: renesas: rzg2l: Remove DSI clock rate restrictions
drm: renesas: rz-du: Set DSI divider based on target MIPI device
drivers/clk/renesas/rzg2l-cpg.c | 147 --
.../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c| 18
FOUTPOSTDIV. So, clksrc=0 always for RZ/G2UL.
Hmm...
I have code that was tested on all the boards, but you're right that it does not
match the documentation.
So now I have to change the code to match the documentation, but keep the
functionality the same.
Then, retest it all.
:(
Chris
arams.dsi_div_a = 3; /* Divided by 8 */
priv->mux_dsi_div_params.dsi_div_b = 0; /* Divided by 1 */
dsi_div_ab = (priv->mux_dsi_div_params.dsi_div_b + 1) <<
priv->mux_dsi_div_params.dsi_div_a;
And on a RZ/G2UL (DPI) EVK, resolutions between 640x48 to 1920x1080 all work.
Do you agree? Or am I missing something?
Chris
priv->dev, "Failed to calculate exact PLL5 settings\n");
>
> Similar to my comment above, would it be a good idea to add something like
> "Failed to calculate exact PLL5 settings, using defaults\n" ?
I can agree to that.
I'll change the message.
Chris
> > + /* If foutvco is above 1.5GHz, change parent and recalculate */
>
> Similar suggestion for hardcoded values in comments, maybe replace "above
> 1.5GHz" with "too high"...
This one I'm OK with because that's the design specification of the hardware IP
that's used in all the devices.
If for some reason they re-design the hardware in future devices, something
going to have to change and
the driver will need to be updated. So we'll deal with it at that point.
Cheers
Chris
acters left to spare on the line :)
Thanks,
Chris
(EXTAL_FREQ_IN_MEGA_HZ *
> > MEGA)) << 24,
> > +EXTAL_FREQ_IN_MEGA_HZ *
> > MEGA);
>
> Remove second identical block?
Wow! How did that get in there
Thanks !
I'll wait a little to see if there are any other comments, then I'll send V4
Chris
Before the MIPI DSI clock source can be configured, the target divide
ratio needs to be known.
Signed-off-by: Chris Brandt
Reviewed-by: Biju Das
Tested-by: Biju Das
---
v1->v2:
- Add spaces around '/' in comments
- Add target argument in new API
v2->v3:
- Add missing period
Convert the limited MIPI clock calculations to a full range of settings
based on math including H/W limitation validation.
Since the required DSI division setting must be specified from external
sources before calculations, expose a new API to set it.
Signed-off-by: Chris Brandt
Signed-off-by
that lanes 3,2,1 can be supported.
Chris Brandt (2):
clk: renesas: rzg2l: Remove DSI clock rate restrictions
drm: renesas: rz-du: Set DSI divider based on target MIPI device
drivers/clk/renesas/rzg2l-cpg.c | 129 --
.../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
the team back in Japan, so that is why we have a MAX of
'2'.
Cheers
Chris
Hi Geert,
Thank you for your review !!
I will update and submit a new version.
Cheers
Chris
-Original Message-
From: Geert Uytterhoeven
Sent: Tuesday, October 21, 2025 10:02 AM
To: Chris Brandt
Cc: Michael Turquette ; Stephen Boyd
; Biju Das ; Maarten Lankhorst
; Maxime Ripard
Hi Geert,
> This needs a dummy for compile-testing the CONFIG_CLK_RZG2L=n case.
OK, thank you.
I will add one and post v3.
Thank you,
Chris
-Original Message-
From: Geert Uytterhoeven
Sent: Thursday, October 16, 2025 9:42 AM
To: Chris Brandt
Cc: Michael Turquette ; Stephen B
reexisting ones.
The ABI predates Iris and Vulkan and provides information about
platforms that they do not support. Since they are using a strict subset
of the pre-existing ABI, there is no requirement to make backwards or
forwards incompatible changes to the stable information provided by the
kernel.
-Chris
transferred to the mmo tree. It is sufficient to just return the err.
-Chris
Before the MIPI DSI clock source can be configured, the target divide
ratio needs to be known.
Signed-off-by: Chris Brandt
---
v1->v2:
- Add spaces around '/' in comments
- Add target argument in new API
---
drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 18 ++
1
On 9/19/25 4:36 AM, Balbir Singh wrote:
> On 9/19/25 02:42, Chris Mason wrote:
>> On Mon, 8 Sep 2025 10:04:38 +1000 Balbir Singh wrote:
>>
>>> Extend migrate_vma_collect_pmd() to handle partially mapped large
>>> folios that require splitting before migration can
> + */
> + if (!new_fault_folio) {
> + folio_unlock(folio);
> + folio_put(folio);
> + } else if (folio != new_fault_folio) {
> + folio_get(new_fault_folio);
> + folio_lock(new_fault_folio);
> + folio_unlock(folio);
> + folio_put(folio);
> + }
Same question here, do we need trylocks?
-chris
>ref, 1 <<
> order));
Here we always bump by 1 << order
I hesitate to send this one because I don't know the code at all, but the
AI review prompts keep flagging this apparent refcount mismatch, and it looks
real to me.
Are the differences in refcount handling inside free_zone_device_folio()
intentional?
-chris
rt thought about adding a new API to the
clock driver.
Chris
-Original Message-
From: Hugo Villeneuve
Sent: Wednesday, September 17, 2025 4:29 PM
To: Chris Brandt
Cc: Geert Uytterhoeven ; Michael Turquette
; Stephen Boyd ; Biju Das
; Maarten Lankhorst
; Maxime Ripard ; Thomas
Zi
t; + return rzg2l_cpg_get_foutpostdiv_rate(priv, params, rate);
> > + }
That is true. I guess that saves a couple CPU cycles that way.
As long as it's still easy to follow (since I am using a reclusive function),
I'm fine with that.
Thank you,
Chris
-Orig
that lanes 3,2,1 can be supported.
Chris Brandt (2):
clk: renesas: rzg2l: Remove DSI clock rate restrictions
drm: renesas: rz-du: Set DSI divider based on target MIPI device
drivers/clk/renesas/rzg2l-cpg.c | 129 --
.../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
Convert the limited MIPI clock calculations to a full range of settings
based on math including H/W limitation validation.
Since the required DSI division setting must be specified from external
sources before calculations, expose a new API to set it.
Signed-off-by: Chris Brandt
Signed-off-by
e table in the hardware manual that
becomes difficult to satisfy in software.
Chris
-Original Message-
From: Geert Uytterhoeven
Sent: Thursday, August 14, 2025 3:39 AM
To: Biju Das
Cc: Chris Brandt ; Michael Turquette
; Stephen Boyd ; Maarten Lankhorst
; Maxime Ripard ; Thomas
Zimmermann
On Mon, Jul 21, 2025 at 08:22:48AM -0400, Satadru Pramanik wrote:
> Hello all,
>
> I suspect this commit in 6.16-rc7 has broken acceleration with Mesa's
> nouveau drivers on my machine.
>
> glxinfo -B reports that I'm using llvmpipe.
>
> Reverting this in 6.16-rc7 restores nouveau acceleration,
Thanks, Simona.
On 11/07/2025 22:54, Simona Vetter wrote:
> On Fri, Jul 11, 2025 at 01:34:19PM +0100, Chris Clayton wrote:
>> Hi
>>
>> I've built and installed 6.16 cloned from Linus' tree and am consistently
>> getting a warning during system startup.
>
are spaces around *?
I missed that one.
Thank you.
Chris
-Original Message-
From: Sergey Shtylyov
Sent: Thursday, July 10, 2025 4:45 AM
To: Chris Brandt ; Geert Uytterhoeven
; Michael Turquette ; Stephen
Boyd ; Biju Das ; Maarten
Lankhorst ; Maxime Ripard
; Thomas Zimmermann ;
u/drm/drm_internal.h | 2 ++
3 files changed, 51 insertions(+), 11 deletions(-)
I've attached files that contain a full dmesg and the bisect log.
If you require any additional diagnostics, just let me know, but please cc me
as I'm not subscribed.
Chris[0.00] Lin
around 'foutvco_rate > 15'
> #146: FILE: drivers/clk/renesas/rzg2l-cpg.c:648:
> + if (priv->mux_dsi_div_params.clksrc && (foutvco_rate > 15)) {
I saw that...but I thought the ( ) makes it a little easier to read.
But, what's the general rule here? Make
Before the MIPI DSI clock source can be configured, the target divide
ratio needs to be known.
Signed-off-by: Chris Brandt
---
drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
b
Convert the limited MIPI clock calculations to a full range of settings
based on math including H/W limitation validation.
Since the required DSI division setting must be specified from external
sources before calculations, expose a new API to set it.
Signed-off-by: Chris Brandt
Signed-off-by
nable")
6f392f371650 ("drm: renesas: rz-du: Implement MIPI DSI host transfers")
Chris Brandt (2):
clk: renesas: rzg2l: Remove DSI clock rate restrictions
drm: renesas: rz-du: Set DSI divider based on target MIPI device
drivers/clk/renesas/rzg2l-cpg.c | 113 +++
On Thu, Jun 05, 2025 at 01:54:50PM +0200, Diederik de Haas wrote:
> On Tue Jun 3, 2025 at 9:39 PM CEST, Chris Morgan wrote:
> > From: Chris Morgan
> >
> > Add support for the Huiling hl055fhav028c panel as used on the
> > Gameforce Ace handheld gaming console. This
Tested on 2 different panels, with an RZ/G2L and RZ/V2L.
Thanks Hugo!
Tested-by: Chris Brandt
-Original Message-
From: Hugo Villeneuve
Sent: Wednesday, June 4, 2025 10:53 AM
To: Biju Das ; [email protected];
[email protected]; [email protected]; airl
is to add this to your previous patch instead of making it separate.
Otherwise, it's like you are submitting one patch with a known bug, then
immediately fixing it with a second patch.
This also would prevent the merge conflict with my patch that also modifies
rzg2l_mipi_dsi_atomic_e
..no comment at all. It's pretty obvious what the code is doing because you
are writing
RZG2L_DCS_BUF_SIZE to a register.
Chris
-Original Message-
From: Chris Brandt
Sent: Wednesday, June 4, 2025 7:54 AM
To: Hugo Villeneuve ; Biju Das ;
[email protected]; m
bytes.
Chris
-Original Message-
From: Hugo Villeneuve
Sent: Wednesday, June 4, 2025 9:35 AM
To: Chris Brandt
Cc: Biju Das ; [email protected];
[email protected]; [email protected]; [email protected]; [email protected];
[email protected]; linux-r
From: Chris Morgan
Enable the DSI controller, DSI DCPHY, and Huiling hl055fhav028c
1080x1920 panel for the Gameforce Ace.
Signed-off-by: Chris Morgan
---
.../dts/rockchip/rk3588s-gameforce-ace.dts| 66 +++
1 file changed, 66 insertions(+)
diff --git a/arch/arm64/boot/dts
From: Chris Morgan
Add support for the Huiling hl055fhav028c panel as used on the
Gameforce Ace handheld gaming console. This panel uses a Himax HX8399C
display controller and requires a sparsely documented vendor provided
init sequence. The display resolution is 1080x1920 and is 70mm by 127mm
From: Chris Morgan
Add support for the DSI panel as found on the Gameforce Ace handheld
gaming console based on the RK3588s.
Chris Morgan (4):
dt-bindings: vendor-prefixes: Add prefix for Huiling
dt-bindings: display: himax-hx8394: Add Huiling hl055fhav028c
drm/panel: himax-hx8394: Add
From: Chris Morgan
Add compatible string for the Huiling hl055fhav028c. This panel is
based on the Himax HX8399C display controller which is extremely
similar to the existing HX8394. Add a new constant for
himax,hx8399c for this new display controller as well.
Signed-off-by: Chris Morgan
From: Chris Morgan
Shenzhen Huiling Information Technology Co. Ltd. specializes in the
research and manufacturing of display and touch screens for industrial
usage. https://en.szhuiling.com/
Signed-off-by: Chris Morgan
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file
When drm_panel.prepare_prev_first is set to true in a panel driver, the
panel expects the MIPI DSI hardware to be already configured before the
panel's prepare function is called because it might need to send DCS
commands.
Signed-off-by: Chris Brandt
---
v1->v2
- Fixed alignment rep
Hi Biju,
> Check patch is complaining about Alignment. Please check and fix it.
>
> scripts/checkpatch.pl --strict *.patch
I ran checkpatch first like I always do, but I didn't use --strict.
I didn't even know there was such a thing.
I'll send a V2
Thanks!
Chris
Sorry, ignore this version.
The local variables are wrong.
I'll submit a V2.....
Chris
-Original Message-
From: Chris Brandt
Sent: Wednesday, May 21, 2025 10:24 AM
To: Biju Das ; Maarten Lankhorst
; Maxime Ripard ; Thomas
Zimmermann ; David Airlie ; Simona
Vetter ; Hien
When drm_panel.prepare_prev_first is set to true in a panel driver, the
panel expects the MIPI DSI hardware to be already configured before the
panel's prepare function is called because it might need to send DCS
commands.
Signed-off-by: Chris Brandt
---
drivers/gpu/drm/renesas/
ode needs to go into the new pre_enable function I made, I
suggest his patch set assumes my patch was already applied.
For now, I'm going to stick with my V1.
Sorry for the noise.
Chris
-Original Message-
From: Chris Brandt
Sent: Wednesday, May 21, 2025 2:38 PM
To: Chris Brandt ;
from v9 to add names for the new
> register blocks. As discussed, the H616 LCD support patchset (which are
> largely device-tree now that the clock/reset binding definitions from v9 have
> been taken as a subset) will be sent separately with the rest of Chris'
> updates.
>
>
On Fri, May 09, 2025 at 05:31:40PM +0100, Andre Przywara wrote:
> On Fri, 9 May 2025 23:29:50 +0900
> Chen-Yu Tsai wrote:
>
> > On Fri, May 9, 2025 at 11:14 PM Andre Przywara
> > wrote:
> > >
> > > On Wed, 7 May 2025 15:19:21 -0500
&g
On Fri, May 09, 2025 at 03:32:04PM +0100, Andre Przywara wrote:
> On Wed, 7 May 2025 15:19:42 -0500
> Chris Morgan wrote:
>
> Hi Chris,
>
> > From: Chris Morgan
> >
> > The LCD backlight for this device can be exposed as a simple GPIO-
> > control
On Thu, May 08, 2025 at 09:26:24AM +0200, Krzysztof Kozlowski wrote:
> On Wed, May 07, 2025 at 03:19:19PM GMT, Chris Morgan wrote:
> > From: Chris Morgan
> >
> > I've spoken with Ryan and he agreed to let me take over this series to
> > get the display engine wor
From: Chris Morgan
Add compatible strings for allwinner,sun50i-h616-display-engine. The
device is functionally identical to the
allwinner,sun50i-h6-display-engine.
Signed-off-by: Chris Morgan
---
.../allwinner,sun4i-a10-display-engine.yaml | 39 +++
1 file changed, 22
From: Chris Morgan
The DE33 is a newer version of the Allwinner Display Engine IP block,
found in the H616, H618, H700 and T507 SoCs. DE2 and DE3 are already
supported by the mainline driver.
The DE33 in the H616 has mixer0 and writeback units. The clocks
and resets required are identical to
From: Chris Morgan
Use the new blender register lookup function where required in the layer
commit and update code.
Signed-off-by: Jernej Skrabec
Signed-off-by: Ryan Walklin
Signed-off-by: Chris Morgan
---
Changelog v2..v3:
- Refactor for 6.11 layer init/modesetting changes
---
drivers/gpu
From: Chris Morgan
The Allwinner H700 exposes RGB and LVDS pins as well as a HDMI
connector. This requires additional clocks for the TCON_TOP and clock
and resets for the TCON_LCD LCD controllers to be defined as per the
T507 datasheet (which shares the same die).
Signed-off-by: Ryan Walklin
From: Chris Morgan
The RG35XX has a 640x480 RGB/SPI LCD panel, supported by the SoC display
pipeline and an NV3052C controller. The H616 SOC's GPIO bank D contains
the muxed display pins for RGB and LVDS output support.
Enable the display engine and LCD timing controller, configure the
From: Chris Morgan
The LCD backlight for this device can be exposed as a simple GPIO-
controlled device. It would be more accurately modelled using PWM to
enable brightness control, however the PWM driver design for the H616 is
not yet upstreamed.
Add a GPIO backlight node to the DTS.
Signed
From: Chris Morgan
The Allwinner H616 and variants have a new display engine revision
(DE33).
The mixer configuration registers are significantly different to the DE3
and DE2 revisions, being split into separate top and display blocks,
therefore a fallback for the mixer compatible is not
From: Chris Morgan
The H616 (and related SoC packages sharing the same die) carry the new
DE33 display engine.
Add the mixer configuration and a compatible string for the H616 to the
mixer.
Signed-off-by: Jernej Skrabec
Signed-off-by: Ryan Walklin
Signed-off-by: Chris Morgan
---
Changelog
From: Chris Morgan
The vi_scaler appears to be used in preference to the ui_scaler module
for hardware video scaling in the DE33.
Enable support for this scaler.
Signed-off-by: Jernej Skrabec
Signed-off-by: Ryan Walklin
Signed-off-by: Chris Morgan
---
drivers/gpu/drm/sun4i/sun8i_ui_layer.c
From: Chris Morgan
The Allwinner H616 has a display pipeline similar to other Allwinner
devices, specifically the A10, but using a newer display engine
revision (DE33).
Not all output pins are exposed on all package variants, for example
only the H700 and T507 have LCD pins exposed, but all
From: Chris Morgan
I've spoken with Ryan and he agreed to let me take over this series to
get the display engine working on the Allwinner H616. I've taken his
previous patch series for Display Engine 3.3 and combined it with the
LCD controller patch series. I've also fixed a few
From: Chris Morgan
The Allwinner H616 (and its H618, H700 and T507 package variants with
the same die) have 28 video output pins for RGB/SPI and LVDS display.
These are in GPIO Bank D and are multiplexed.
In RGB mode, pins PD0-PD23 are for 24-bit RGB pixel output, pins
PD24-PD27 are for clock
From: Chris Morgan
Add a compatible string for the H616 SRAM C region which is
functionally similar to the A64 SRAM C region.
Signed-off-by: Chris Morgan
---
.../bindings/sram/allwinner,sun4i-a10-system-control.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
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