Hi Geert, > This needs a dummy for compile-testing the CONFIG_CLK_RZG2L=n case.
OK, thank you. I will add one and post v3. Thank you, Chris -----Original Message----- From: Geert Uytterhoeven <[email protected]> Sent: Thursday, October 16, 2025 9:42 AM To: Chris Brandt <[email protected]> Cc: Michael Turquette <[email protected]>; Stephen Boyd <[email protected]>; Biju Das <[email protected]>; Maarten Lankhorst <[email protected]>; Maxime Ripard <[email protected]>; Thomas Zimmermann <[email protected]>; David Airlie <[email protected]>; Simona Vetter <[email protected]>; Hien Huynh <[email protected]>; Nghia Vo <[email protected]>; Hugo Villeneuve <[email protected]>; [email protected]; [email protected]; [email protected] Subject: Re: [PATCH v2 1/2] clk: renesas: rzg2l: Remove DSI clock rate restrictions Hi Chris, On Fri, 12 Sept 2025 at 16:22, Chris Brandt <[email protected]> wrote: > Convert the limited MIPI clock calculations to a full range of > settings based on math including H/W limitation validation. > Since the required DSI division setting must be specified from > external sources before calculations, expose a new API to set it. > > Signed-off-by: Chris Brandt <[email protected]> > Signed-off-by: hienhuynh <[email protected]> > Signed-off-by: Nghia Vo <[email protected]> Thanks for your patch! > --- a/include/linux/clk/renesas.h > +++ b/include/linux/clk/renesas.h > @@ -33,3 +33,7 @@ void cpg_mssr_detach_dev(struct generic_pm_domain *unused, > struct device *dev); > #define cpg_mssr_detach_dev NULL > #endif > #endif > + > +#ifdef CONFIG_CLK_RZG2L > +void rzg2l_cpg_dsi_div_set_divider(int divider, int target); #endif This needs a dummy for compile-testing the CONFIG_CLK_RZG2L=n case. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected] In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
