Hi Hugo,
On Wed, Nov 19, 2025 6:32 PM, Hugo Villeneuve wrote:
> > + unsigned int dsi_div_ab_calc;
>
> Change type to u8 like dsi_div_ab_desired.
OK.
> > + if (rzg2l_cpg_div_ab(a, b) == dsi_div_ab_calc) {
> > + priv->mux_dsi_div_params.dsi_div_a = a;
> > + priv->mux_dsi_div_params.dsi_div_b = b;
> > + goto calc_pll_clk;
>
> At this point, you matched your a and b with dsi_div_ab_calc, which can be
> different than dsi_div_ab_desired (even -> divided by 2). And
> when you calculate PLL5 clock (after calc_pll_clk), you use
> dsi_div_ab_desired, not dsi_div_ab_calc. Is this ok?
Yes.
But, I just noticed that my ASCII diagram was wrong.
I was trying to save space to keep it under 100 characters, but in trying to
compress it, I ended up drawing it wrong.
So now I'll just put the comment outside the function to get more space.
Here's the new diagram.
/*
* VCO-->[POSTDIV1,2]--FOUTPOSTDIV--------------->|
* | |-->[1/(DSI DIV A * B)]-->
MIPI_DSI_VCLK
* |-->[1/2]--FOUT1PH0-->|
* |
* |------->[1/16]-------------------------------->
hsclk (MIPI-PHY)
*/
The "dsi_div_ab_desired" is chosen mostly to make hsclk happy.
And, you can see it is always used to calculate the PLL regardless of odd/even.
But, only when you need to calculate the DIV_A,B, you might have that extra 1/2
divide in there.
Thanks for pointing this out.....which made me realize my diagram was wrong.
Chris
