Hi Geert, -----Original Message----- From: Geert Uytterhoeven <[email protected]> Sent: Tuesday, October 21, 2025 10:02 AM
> Thanks for your patch! I implemented all your suggestions changes and re-tested and everything still seems to work the same. :) However.... > > +#define PLL5_REFDIV_MIN 1 > > +#define PLL5_REFDIV_MAX 2 > > Documentation says 1..63? Yes, for the 'possible' register bit values, but then later on they say only set it to '1 to 2' in the table in section 7.2.4.14 of RZ/G2L Hardware Manual. I also heard this from the team back in Japan, so that is why we have a MAX of '2'. Cheers Chris
