[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen updated this revision to Diff 326104. khchen marked 10 inline comments as done. khchen added a comment. 1. Rebase 2. Address Craig's comments. 3. Change the operand orders of builtin to the same order of IR intrinsics. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION htt

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:899 +// (operand) in ProtoSeq. ProtoSeq[0] is output operand. +SmallVector ProtoSeq; +const StringRef Primaries("evwqom0ztc"); craig.topper wrote: > I think this is somet

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen updated this revision to Diff 326107. khchen marked 2 inline comments as done. khchen added a comment. address https://reviews.llvm.org/D95016?id=324197#inline-912573 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95016/new/ https://reviews.l

[PATCH] D96843: [Clang][RISCV] Add vsetvl and vsetvlmax.

khchen updated this revision to Diff 326310. khchen added a comment. Rebase. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D96843/new/ https://reviews.llvm.org/D96843 Files: clang/include/clang/Basic/riscv_vector.td clang/lib/Basic/Targets/RISC

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen updated this revision to Diff 326300. khchen marked 21 inline comments as done. khchen added a comment. 1. Rename Dump to Print. 2. Address Craig's comments, thanks for your patient. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95016/new/ h

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:270 + IsPointer(false), IsSize_t(false), IsPtrdiff_t(false), + ElementBitwidth(~0U), Scale(0) { + applyBasicType(); craig.topper wrote: > Why is ElementBitwidth default ~0

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen updated this revision to Diff 326309. khchen added a comment. refine comment Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95016/new/ https://reviews.llvm.org/D95016 Files: clang/include/clang/Basic/BuiltinsRISCV.def clang/include/clang

[PATCH] D107433: [RISCV] Half-precision for vget/vset.

khchen added inline comments. Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics/vget.c:554 +// +vfloat16m1_t test_vget_v_f16m2_f16m1 (vfloat16m2_t src, size_t index) { + return vget_v_f16m2_f16m1(src, 0); index is an unused argument. Comment

[PATCH] D107433: [RISCV] Half-precision for vget/vset.

khchen accepted this revision. khchen added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107433/new/ https://reviews.llvm.org/D107433 __

[PATCH] D105001: [Clang][RISCV] Support half-precision floating point for RVV intrinsics.

khchen added a comment. This all looks good to me except adding back the asm check. BTW, do we need to attach the half-precision floating point spec link? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105001/new/ https://reviews.llvm.org/D105001

[PATCH] D105092: [PoC][RISCV] Add the tail policy argument to builtins/intrinsics.

khchen added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:1148 +if (HasPolicy) { + ProtoMaskSeq.push_back("z"); +} maybe the policy argument should be a constant value ("Kz")? Repository: rG LLVM Github Monorepo CHANGES SI

[PATCH] D102582: [RISCV] Report an error when ABI mismatch with target-abi module flag.

khchen added a comment. ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D102582/new/ https://reviews.llvm.org/D102582 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-

[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

khchen updated this revision to Diff 356425. khchen added a comment. Update test cases. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D71387/new/ https://reviews.llvm.org/D71387 Files: clang/lib/Driver/ToolChains/Arch/RISCV.cpp clang/lib/Driver

[PATCH] D102582: [RISCV] Report an error when ABI mismatch with target-abi module flag.

khchen added inline comments. Comment at: llvm/test/CodeGen/RISCV/module-target-abi-tests.ll:5 +; RUN: cat %s > %t.emptyabi +; RUN: echo '!0 = !{i32 1, !"target-abi", !""}' >> %t.emptyabi +; RUN: llc -mtriple=riscv32 < %t.emptyabi -o /dev/null jrtc27 wrote: > khc

[PATCH] D105555: [PoC][RISCV][Clang] Compute the default target-abi if it's empty.

khchen created this revision. khchen added reviewers: jrtc27, asb, luismarques. Herald added subscribers: vkmr, frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, kito-cheng, nios

[PATCH] D105555: [PoC][RISCV][Clang] Compute the default target-abi if it's empty.

khchen updated this revision to Diff 357148. khchen added a comment. Herald added subscribers: llvm-commits, dexonsmith, hiraditya. Herald added a project: LLVM. address jrtc27's comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D10/new/ ht

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

khchen added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:195 if (MArch.startswith_insensitive("rv32")) { // FIXME: parse `March` to find `D` extension properly if (MArch.substr(4).contains_insensitive("d") || I think maybe

[PATCH] D102582: [RISCV] Report an error when ABI mismatch with target-abi module flag.

khchen updated this revision to Diff 357420. khchen added a comment. rebase on D102582 report a error if target-abi module flag is is empty. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D102582/new/ https://review

[PATCH] D105001: [Clang][RISCV] Support half-precision floating point for RVV intrinsics.

khchen added inline comments. Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c:13 +// ASM-NOT: warning #include HsiangKai wrote: > craig.topper wrote: > > Do you plan to bring back the ASM check for all tests? > No, I will remove it. Thi

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

khchen added inline comments. Comment at: clang/test/Driver/riscv-abi.c:68 -// RUN: %clang -target riscv64-unknown-elf %s -### -o %t.o -march=rv64d -mabi=lp64d 2>&1 \ +// RUN: %clang -target riscv64-unknown-elf %s -### -o %t.o -march=rv64ifd -mabi=lp64d 2>&1 \ // RUN: | Fi

[PATCH] D112408: [WIP][RISCV] Add the zve extension according to the v1.0-rc2 spec

khchen added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:181 } + if (MinVLen) { please add a note in commit or comment here for those macros are proposed in the PR https://github.com/riscv-non-isa/riscv-c-api-doc/pull/21 ==

[PATCH] D105555: [RISCV][Clang] Compute the default target-abi if it's empty.

khchen updated this revision to Diff 384981. khchen added a comment. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence. rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D10/new/ https://reviews.llvm.org/D10 Fil

[PATCH] D96843: [Clang][RISCV] Add vsetvl and vsetvlmax.

khchen updated this revision to Diff 326612. khchen marked 3 inline comments as done. khchen added a comment. address Craig's comments. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D96843/new/ https://reviews.llvm.org/D96843 Files: clang/include

[PATCH] D96843: [Clang][RISCV] Add vsetvl and vsetvlmax.

khchen added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:1052 uint8_t PrevExt = (*Defs.begin())->getRISCV_Extensions(); - bool NeedEndif = emitExtDefStr(PrevExt, OS); + bool NeedEndif = + (*Defs.begin())->hasAutoDef() ? emitExtDefStr(PrevExt, OS)

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen updated this revision to Diff 326585. khchen marked 10 inline comments as done. khchen added a comment. 1. address Craig's comments. 2. use ListSeparator in some code snippet. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95016/new/ https://

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen updated this revision to Diff 326980. khchen marked 17 inline comments as done. khchen added a comment. 1. address @jrtc27's suggestions, thanks. 2. fix several bugs. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95016/new/ https://reviews.l

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:56 +// +// e: type of "t" as is (identity) +// v: computes a vector type whose element type is "t" for the current LMUL jrtc27 wrote: > khchen wrote: > > jrtc27 wrote: > > > D

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen updated this revision to Diff 327363. khchen marked 11 inline comments as done. khchen added a comment. address @jrtc27's comments, thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95016/new/ https://reviews.llvm.org/D95016 Files: cl

[PATCH] D97826: [RISCV] Make use of the required features in BuiltinInfo to store that V extension builtins require 'experimental-v'.

khchen added a comment. LGTM! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D97826/new/ https://reviews.llvm.org/D97826 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-b

[PATCH] D97916: [Driver][RISCV] Support parsing multi-lib config from GCC.

khchen added a comment. I didn't check why I got error in Failed Tests (1): Clang :: Driver/riscv64-toolchain.c Could you please double check it? Thanks! Comment at: clang/lib/Driver/ToolChains/Gnu.cpp:1599 +static std::string getGCCPath(const Driver &D, const ArgList &Ar

[PATCH] D97916: [Driver][RISCV] Support parsing multi-lib config from GCC.

khchen added a comment. Overall LGTM. Comment at: clang/lib/Driver/ToolChains/Gnu.cpp:1604 + const Arg *A = Args.getLastArg(clang::driver::options::OPT_gcc_toolchain); + if (A) { +GCCPath = findGCCPath(D, A->getValue()); khchen wrote: > if (const Arg *A =

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen updated this revision to Diff 328533. khchen added a comment. rebase. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95016/new/ https://reviews.llvm.org/D95016 Files: clang/include/clang/Basic/BuiltinsRISCV.def clang/include/clang/Basic/

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen added a comment. @jrtc27, please advise if there is anything more should to be changed, thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95016/new/ https://reviews.llvm.org/D95016 ___ cfe-com

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGd6a0560bf258: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics. (authored by khchen). Changed prior to commit: https://revie

[PATCH] D98388: [RISCV][Clang] Add RVV vle/vse intrinsic functions.

khchen marked 6 inline comments as done. khchen added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:689 + skew = 1; +for (unsigned i = 0; i < PermuteOperands.size(); ++i) { + if (i != PermuteOperands[i]) rogfer01 wrote: > These

[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

khchen added a comment. In D70401#3172457 , @zixuan-wu wrote: > Hi, all. Why is it not continued? Sorry, I have to work on other tasks so stop the rv32e implementation work. Are you interest to finish it? I could share my patches to you. Repository: r

[PATCH] D140389: [NFC][Clang][RISCV] Rename data member 'DefaultPolicy' to 'PolicyAttrs'

khchen accepted this revision. khchen added a comment. This revision is now accepted and ready to land. LGTM, thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D140389/new/ https://reviews.llvm.org/D140389 __

[PATCH] D140662: [NFC][Clang][RISCV] Reduce boilerplate when determining prototype for segment loads

khchen added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:847 + + // Intrinsic is in the form of below, + // Masked: (Vector0, ..., Vector{NF - 1}, Ptr, Mask, VL, Policy) After remove the builtins comment I don't have idea what

[PATCH] D140687: [Clang][RISCV] Use poison instead of undef

khchen accepted this revision. khchen added a comment. This revision is now accepted and ready to land. LGTM, thanks!! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D140687/new/ https://reviews.llvm.org/D140687 _

[PATCH] D140662: [NFC][Clang][RISCV] Reduce boilerplate when determining prototype for segment loads

khchen added a comment. LGTM. Thanks for clean up code! Comment at: clang/include/clang/Basic/riscv_vector.td:820 +(Address0, ..., Address{NF - 1}, mask, Ptr, VL) +(Address0, ..., Address{NF - 1}, mask, Maskedoff0, ..., Maskedoff{NF - 1}, + Ptr, VL) nit: there

[PATCH] D126461: [RISCV] Extract and store new vl of vleff/vlsegff iff destination isn't null

khchen added a comment. Could you please purpose this implement in rvv-intrinsc-doc first? I think this feature need to have discussion because store to nullptr is UB but we are making it as defined behavior only for these intrinsics. Personally I like they have consistent behavior and in documen

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

khchen added inline comments. Comment at: clang/lib/Sema/SemaRVVLookup.cpp:175 + for (auto &Record : RVVIntrinsicRecords) { +// Create Intrinsics for each type and LMUL. +BasicType BaseType = BasicType::Unknown; Those code logic need to sync with createR

[PATCH] D126634: [RISCV][NFC] Rename variables in rvv intrinsics related files.

khchen created this revision. khchen added a reviewer: kito-cheng. Herald added subscribers: sunshaoce, VincentWu, luke957, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzh

[PATCH] D126634: [RISCV][NFC] Rename variables in rvv intrinsics related files.

This revision was automatically updated to reflect the committed changes. Closed by commit rG79e3d57f5228: [RISCV][NFC] Rename variables in rvv intrinsics related files. (authored by khchen). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D126634/new/

[PATCH] D126740: [RISCV][Clang] Refactor and rename rvv intrinsic related stuff. (NFC)

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, kito-cheng, fakepaper56, eopXD. Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o,

[PATCH] D126741: [RISCV][Clang] Refactor RISCVVEmitter. (NFC)

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, kito-cheng, fakepaper56, eopXD. Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o,

[PATCH] D126743: [RISCV][Clang] Add tests for all supported policy functions. (NFC)

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, kito-cheng, fakepaper56, eopXD. Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o,

[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, kito-cheng, fakepaper56, eopXD. Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o,

[PATCH] D126746: [RISCV][Clang] Support policy functions for Vector Comparison Instructions.

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, kito-cheng, fakepaper56, eopXD. Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o,

[PATCH] D126748: [RISCV][Clang] Support policy functions for Vector Reduction Instructions.

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, kito-cheng, fakepaper56, eopXD. Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o,

[PATCH] D126749: [RISCV][Clang] Support policy functions for Vector Mask Instructions.

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, kito-cheng, fakepaper56, eopXD. Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o,

[PATCH] D125323: [RISCV] Add the passthru operand for RVV unmasked segment load IR intrinsics.

khchen added a comment. In D125323#3549794 , @pcwang-thead wrote: > Is there an easy way to update tests? Or we need to add passthru operands > manually? I will appreciate it if you can tell me. :-) use sed to do replacement. ex. #!/bin/bash set -

[PATCH] D125624: [gold] Remove an external dependency to GNU binutils' header file

khchen added a comment. IMO, maybe we could keep the DLLVM_BINUTILS_INCDIR option support but default is using the Plugin.h? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125624/new/ https://reviews.llvm.org/D125624 __

[PATCH] D126461: [RISCV] Extract and store new vl of vleff iff destination isn't null

khchen added a comment. > Store to null will be changed to unreachable, so all instructions after vleff > intrinsic call will be deleted and it causes runtime errors. If destination > to store is null, we won't extract and store the new vl. > Yes, but only for vleff instructions, since it has

[PATCH] D126461: [RISCV] Extract and store new vl of vleff iff destination isn't null

khchen added a comment. IMO, if I'm an user, I would not expected intrinsic function will generate the condition code to impact the performance, maybe we need to raise a issue in rvv-intrinsic-doc. maybe another way is adding a note in intrinsic document to address that the vl could not be a n

[PATCH] D138429: [clang][RISCV][NFC] Prevent data race in RVVType::computeType

khchen added inline comments. Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:284 + +class RVVTypeCache { +private: nit: maybe we could add some comments to said the motivation for `RVVTypeCache`. Comment at: clang/include/clan

[PATCH] D72245: [PoC][RISCV][LTO] Pass target-abi via module flag metadata

khchen abandoned this revision. khchen added a comment. Herald added subscribers: jobnoorman, luke, pcwang-thead, eopXD, VincentWu, ormris, vkmr, frasercrmck, arichardson. Herald added a project: All. I'm not working on RISC-V now and please reference https://reviews.llvm.org/D132843#3770454 to

[PATCH] D78035: [PoC][RISCV] enable LTO/ThinLTO on RISCV

khchen abandoned this revision. khchen added a comment. Herald added subscribers: jobnoorman, luke, pcwang-thead, eopXD, VincentWu, arichardson. Herald added a project: All. I'm not working on RISC-V now and please reference https://reviews.llvm.org/D132843#3770454 to see the follow-up work. R

[PATCH] D102582: [RISCV] Report an error when ABI mismatch with target-abi module flag.

khchen abandoned this revision. khchen added a comment. Herald added subscribers: jobnoorman, luke, pcwang-thead, eopXD, VincentWu. Herald added a project: All. we don't need this patch because we already handle the empty target-abi module flag now. Repository: rG LLVM Github Monorepo CHANGE

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

khchen added a comment. 1. please add a check here and a clang cc1 test for it. 2. Have you try to run llvm-test-suite with rv32e config on qemu? Commen

[PATCH] D117647: [RISCV] Add destination operand for RVV nomask load intrinsics.

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, evandro, arcbbb, monkchiang. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, bruc

[PATCH] D117681: [RISCV] Add the policy operand for some masked RVV ternary IR intrinsics.

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, frasercrmck, kito-cheng, arcbbb, monkchiang. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX

[PATCH] D117724: [RISCV] Remove Zvlsseg extension.

khchen added inline comments. Comment at: llvm/test/MC/RISCV/rvv/zvlsseg.s:11 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v \ # RUN: --mattr=+experimental-zvlsseg %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN ---

[PATCH] D117647: [RISCV] Add destination operand for RVV nomask load intrinsics.

khchen updated this revision to Diff 401446. khchen added a comment. Address Craig's comments, thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117647/new/ https://reviews.llvm.org/D117647 Files: clang/include/clang/Basic/riscv_vector.td

[PATCH] D117681: [RISCV] Add the policy operand for some masked RVV ternary IR intrinsics.

khchen updated this revision to Diff 401447. khchen added a comment. Address Craig's comment. Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117681/new/ https://reviews.llvm.org/D117681 Files: clang/include/clang/Basic/riscv_vector.td c

[PATCH] D117647: [RISCV] Add destination operand for RVV nomask load intrinsics.

khchen updated this revision to Diff 401899. khchen added a comment. address frasercrmck's comments. rewrite snippet of code to fix potential bug and make more readable. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117647/new/ https://reviews.llvm

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

khchen added a comment. Herald added a subscriber: eopXD. It seems like not only one place need to have a consistent way to process intrinsic. (ex. InitIntrinsicList/createRVVIntrinsics and RVVIntrinsic::RVVIntrinsic/InitRVVIntrinsic) I'm think how to avoid mismatch implementation in the future,

[PATCH] D117913: [Clang][RISCV] Guard vmulh, vsmul correctly

khchen added a comment. why the new test filename extension is `.c.c`? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117913/new/ https://reviews.llvm.org/D117913 ___ cfe-commits mailing list cfe-commits@

[PATCH] D118015: [RISCV][NFC] Rename RequiredExtensions to RequiredFeatures.

khchen accepted this revision. khchen added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D118015/new/ https://reviews.llvm.org/D118015 ___

[PATCH] D113237: [RISCV] Support I extension version 2.1

khchen added a comment. Herald added subscribers: pcwang-thead, eopXD. https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/aE1ZeHHCYf4 RISC-V GNU toolchain are going to bump the default ISA spec to 20191213, which means will default with I 2.1, A 2.1, F 2.2 and D 2.2. I think it will be good

[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

khchen added a comment. Herald added subscribers: pcwang-thead, eopXD. In D115921#3206434 , @luismarques wrote: > I think this would benefit from increased test coverage, namely to show that > the mattr command-line options are properly handled. Some po

[PATCH] D107290: [RISCV] Add support for the vscale_range attribute

khchen added inline comments. Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll:162 + +attributes #0 = { vscale_range(2,1024) } +attributes #1 = { vscale_range(4,1024) } I'm thinking do we need to test zvl and vscale_range in the same attribut

[PATCH] D117647: [RISCV] Add passthru operand for RVV nomask load intrinsics.

khchen updated this revision to Diff 402776. khchen added a comment. Herald added a subscriber: pcwang-thead. rebase and ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117647/new/ https://reviews.llvm.org/D117647 Files: clang/include/clang/

[PATCH] D107290: [RISCV] Add support for the vscale_range attribute

khchen added inline comments. Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll:162 + +attributes #0 = { vscale_range(2,1024) } +attributes #1 = { vscale_range(4,1024) } frasercrmck wrote: > khchen wrote: > > I'm thinking do we need to test zv

[PATCH] D117647: [RISCV] Add passthru operand for RVV nomask load intrinsics.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG9273378b8576: [RISCV] Add the passthru operand for RVV nomask load intrinsics. (authored by khchen). Repository: rG LLVM Github Monorepo CHANGES

[PATCH] D117681: [RISCV] Add the policy operand for some masked RVV ternary IR intrinsics.

khchen updated this revision to Diff 403117. khchen added a comment. rebase and address Craig's comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117681/new/ https://reviews.llvm.org/D117681 Files: clang/include/clang/Basic/riscv_vector.td

[PATCH] D118253: [RISCV] Add the passthru operand for some RVV nomask unary and nullary intrinsics.

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, frasercrmck, kito-cheng, arcbbb, monkchiang, eopXD. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewe

[PATCH] D118333: [RISCV] Update computeTargetABI implementation.

khchen created this revision. khchen added reviewers: craig.topper, jrtc27, frasercrmck, kito-cheng, arcbbb, monkchiang, eopXD. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, armkevincheng, eric-k256, vkmr, dexonsmith, evandro, luismarques, apazos, sameer.abuasal, s

[PATCH] D118333: [RISCV] Update computeTargetABI implementation.

khchen added a comment. In D118333#3275940 , @jrtc27 wrote: > I think this is the same idea as D118333 ? > Other than being a cleaner way of achieving the same goal. I've not looked to > see if there are any functional

[PATCH] D107290: [RISCV] Add support for the vscale_range attribute

khchen added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp:99 + if (VScaleRangeAttr.isValid()) { +RVVBitsMin = VScaleRangeAttr.getVScaleRangeMin() * RISCV::RVVBitsPerBlock; +if (VScaleRangeAttr.getVScaleRangeMax().hasValue())

[PATCH] D107290: [RISCV] Add support for the vscale_range attribute

khchen added inline comments. Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll:162 + +attributes #0 = { vscale_range(2,1024) } +attributes #1 = { vscale_range(4,1024) } frasercrmck wrote: > khchen wrote: > > frasercrmck wrote: > > > khchen wr

[PATCH] D120227: [RISCV] Add policy operand for masked vid and viota IR intrinsics.

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, frasercrmck, kito-cheng, arcbbb, monkchiang, eopXD. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewe

[PATCH] D120228: [RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR intrinsics.

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, frasercrmck, kito-cheng, arcbbb, monkchiang, eopXD. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewe

[PATCH] D118333: [RISCV] Use computeTargetABI from llc as well as clang

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG4e115b7d8811: [RISCV] Update computeTargetABI from llc as well as clang (authored by khchen). Changed prior to commit: https://reviews.llvm.org/D1

[PATCH] D120870: [RISCV][NFC] Refine and refactor RISCVVEmitter and riscv_vector.td.

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, kito-cheng, arcbbb, monkchiang, eopXD. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewe

[PATCH] D120449: [RISCV][RVV] Add strict vfcvt intrinsics that have side effects for dynamically-set rounding mode

khchen added a comment. Makes sense to me, but I'd appreciate someone else for a final LGTM. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4683 +Ops.push_back(VL); +Ops.push_back(DAG.getUNDEF(XLenVT)); // Policy + } arcbbb wrote: > kito-cheng

[PATCH] D100824: [RISCV] Implement the vwcvt{u}.x.x.v/vncvt.x.x.w builtin.

khchen accepted this revision. khchen added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100824/new/ https://reviews.llvm.org/D100824 __

[PATCH] D100821: [RISCV] Implement the vmmv.m/vmnot.m builtin.

khchen accepted this revision. khchen added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100821/new/ https://reviews.llvm.org/D100821 __

[PATCH] D99741: [RISCV][Clang] Add some RVV Floating-Point intrinsic functions. (vfclass, vfmerge, vfrec7, vfrsqrt7, vfsqrt)

khchen added a comment. @thakis https://reviews.llvm.org/D100611 had landed, could you check your bot to see the cycle time? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99741/new/ https://reviews.llvm.org/D99741 ___

[PATCH] D101426: [RISCV] Update subset naming convertion for the latest spec

khchen added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:180 + // as described in RISC-V User-Level ISA 20191213. SmallVector Split; Exts.split(Split, StringRef("_")); If we want to update the arch string rules to ISA 20191213,

[PATCH] D101700: [RISCV] Reorder masked builtin operands. Use clang_builtin_alias for all overloaded vector builtins.

khchen accepted this revision. khchen added a comment. This revision is now accepted and ready to land. LGTM. Thanks for improvement! Comment at: clang/include/clang/Basic/riscv_vector.td:192 - // When the order of the parameters of clang builtin do not match the order of -

[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

khchen added a comment. Herald added a subscriber: vkmr. Hi, I would like to add ilp32e ABI support in llvm Is there anyone working on this? It seem the one thing missed is ilp32e ABI should disallow D ISA extension. Is there anything else? Repository: rG LLVM Github Monorepo CHANGES SINCE LA

[PATCH] D102051: [RISCV] Consider scalar types for required extensions.

khchen accepted this revision. khchen added a comment. This revision is now accepted and ready to land. Good catch! LGTM! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D102051/new/ https://reviews.llvm.org/D102051 __

[PATCH] D102086: [RISCV] Validate the SEW and LMUL operands to __builtin_rvv_vsetvli(max)

khchen accepted this revision. khchen added a comment. This revision is now accepted and ready to land. Good catch, LGTM! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D102086/new/ https://reviews.llvm.org/D102086 __

[PATCH] D117199: [RISCV] Add missing namespace (NFC)

khchen added a comment. > The main reason I want to add the prefix "llvm::" is all None in the files > are "llvm::None" form. It makes sense to me. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117199/new/ https://reviews.llvm.org/D117199 __

[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

khchen added a comment. > Is it (D70401 ) good enough to solve or > complete rv32e issue? It need to 1. disallow ilp32e ABI with D ISA extension. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/3f81fae0412bb9ad4002a4ade508be7aa5e1599b/riscv-cc.adoc#il

[PATCH] D105555: [RISCV][Clang] Compute the default target-abi if it's empty.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG57b5f4b2ecc6: [RISCV][Clang] Compute the default target-abi if it's empty. (authored by khchen). Changed prior to commit: https://reviews.llvm.org

[PATCH] D96843: [Clang][RISCV] Add vsetvl and vsetvlmax.

khchen updated this revision to Diff 331267. khchen marked 2 inline comments as done. khchen added a comment. 1. address Craig's comments. 2. update test by using 2>&1 instead of 2>%t Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D96843/new/ https:/

[PATCH] D98388: [RISCV][Clang] Add RVV vle/vse intrinsic functions.

khchen added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:687 + +unsigned Skew = 0; +if (HasMaskedOffOperand) craig.topper wrote: > ``` > unsigned Skew = HasMaskedOffOperand ? 1 : 0; > ``` > > unless this needs to get more complica

[PATCH] D96843: [Clang][RISCV] Add vsetvl and vsetvlmax.

khchen marked an inline comment as done. khchen added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:169 +Builder.defineMacro("__rvv_e64", "3"); +Builder.defineMacro("__rvv_e128", "4"); + craig.topper wrote: > Are intending to support e128

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