khchen created this revision. khchen added reviewers: craig.topper, rogfer01, evandro, arcbbb, monkchiang. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya. khchen requested review of this revision. Herald added subscribers: llvm-commits, cfe-commits, eopXD, MaskRay. Herald added projects: clang, LLVM.
The goal is support tail and mask policy in RVV builtins. We focus on IR part first. If the destination is undef, we use tail agnostic, otherwise use tail undisturbed. Co-Authored-by: Hsiangkai Wang <[email protected]> Repository: rG LLVM Github Monorepo https://reviews.llvm.org/D117647 Files: clang/include/clang/Basic/riscv_vector.td clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c clang/test/CodeGen/RISCV/rvv-intrinsics/vlse.c clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c llvm/include/llvm/IR/IntrinsicsRISCV.td llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td llvm/test/CodeGen/RISCV/rvv/rv32-vsetvli-intrinsics.ll llvm/test/CodeGen/RISCV/rvv/rv64-vsetvli-intrinsics.ll llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll llvm/test/CodeGen/RISCV/rvv/unmasked-tu-rv32.ll llvm/test/CodeGen/RISCV/rvv/unmasked-tu-rv64.ll llvm/test/CodeGen/RISCV/rvv/vle-rv32.ll llvm/test/CodeGen/RISCV/rvv/vle-rv64.ll llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll llvm/test/CodeGen/RISCV/rvv/vlse-rv32.ll llvm/test/CodeGen/RISCV/rvv/vlse-rv64.ll llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
