khchen created this revision. khchen added reviewers: craig.topper, rogfer01, frasercrmck, kito-cheng, arcbbb, monkchiang, eopXD. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya. khchen requested review of this revision. Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, MaskRay. Herald added projects: clang, LLVM.
The goal is support tail and mask policy in RVV builtins. We focus on IR part first. If the passthru operand is undef, we use tail agnostic, otherwise use tail undisturbed. My plan is to handle more complex operations in follow-up patches. Repository: rG LLVM Github Monorepo https://reviews.llvm.org/D118253 Files: clang/include/clang/Basic/riscv_vector.td clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsext.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vzext.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfclass.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfcvt.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfncvt.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfrec7.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsqrt7.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfsqrt.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c clang/test/CodeGen/RISCV/rvv-intrinsics/vsext.c clang/test/CodeGen/RISCV/rvv-intrinsics/vzext.c llvm/include/llvm/IR/IntrinsicsRISCV.td llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll llvm/test/CodeGen/RISCV/rvv/vfclass.ll llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f.ll llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f.ll llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f.ll llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f.ll llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f.ll llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll llvm/test/CodeGen/RISCV/rvv/vfrec7.ll llvm/test/CodeGen/RISCV/rvv/vfrsqrt7.ll llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f.ll llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f.ll llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll llvm/test/CodeGen/RISCV/rvv/vid.ll llvm/test/CodeGen/RISCV/rvv/viota.ll llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
