[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

khchen added a comment. In D71387#3755056 , @lewis-revill wrote: > I believe this patch is still relevant/necessary when using LTO for RISCV, so > can I ask if @khchen is able to update it to rebase/address the feedback? If > not, are there are any obje

[PATCH] D132843: [RISCV] Ensure target features get passed to the LTO linker for RISC-V

khchen added a comment. > Possible solution/results: > > 1. All functions in `a.o` and `b.o` using same target features during the > first build stage, `-march=rv64gc` for a.o, `-march=rv64g` for `b.o`, and > `-march` option given in LTO CodeGen stage is ignored, it only used for ELF > attribut

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

khchen accepted this revision. khchen added a comment. This revision is now accepted and ready to land. LGTM. Other than that last comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:77 + // Create compressed hsignature table from SemaRecords. + void init(const std::

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

khchen added a comment. @craig.topper @rogfer01 - do you have other comments? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111617/new/ https://reviews.llvm.org/D111617 ___ cfe-commits mailing list cfe-c

[PATCH] D129043: [RISCV][Clang] Teach RISCVEmitter to generate BitCast for pointer operands.

khchen added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:111 +if (I.value()->isPointer()) { + assert(RVVI->getIntrinsicTypes().front() == -1 && + "RVVI should be vector load intrinsic."); I feel this logic is not clear

[PATCH] D122455: Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR"

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, frasercrmck, kito-cheng, arcbbb, monkchiang, eopXD. Herald added subscribers: s, VincentWu, luke957, StephenFan, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o,

[PATCH] D122455: Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR"

This revision was not accepted when it landed; it landed in state "Needs Review". This revision was automatically updated to reflect the committed changes. Closed by commit rG10b2760da0fd: Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR" (authored by khchen). Herald

[PATCH] D126740: [RISCV][Clang] Refactor and rename rvv intrinsic related stuff. (NFC)

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGbc4eef509b21: [RISCV][Clang] Refactor and rename rvv intrinsic related stuff. (NFC) (authored by khchen). Changed prior to commit: https://reviews

[PATCH] D126741: [RISCV][Clang] Refactor RISCVVEmitter. (NFC)

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG93f8657c743b: [RISCV][Clang] Refactor RISCVVEmitter. (NFC) (authored by khchen). Changed prior to commit: https://reviews.llvm.org/D126741?vs=4332

[PATCH] D126743: [RISCV][Clang] Add tests for all supported policy functions. (NFC)

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG8e51917b39cd: [RISCV][Clang] Add tests for all supported policy functions. (NFC) (authored by khchen). Repository: rG LLVM Github Monorepo CHANGE

[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

khchen added a comment. In D126745#3678776 , @nlopes wrote: > While at it, could you switch those UndefValue with PoisonValue if possible? > Thank you! I'm not sure UndefValue will work because the backend would only check isUndef() to generate correc

[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

khchen added a comment. In D126745#3691544 , @craig.topper wrote: > In D126745#3691528 , @khchen wrote: > >> In D126745#3678776 , @nlopes wrote: >> >>> While at it, could

[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

khchen added a comment. oops.. all tests need to updated and include all intrinsic IR tests... Is there any benefit to switch UndefValue to PoisonValue? maybe those changed should be in other follow-up patches? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.ll

[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

khchen added a comment. @nlopes we will update all undef to poison in follow up patches. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D126745/new/ https://reviews.llvm.org/D126745 ___ cfe-commits mailing

[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG7eddeb9e99f3: [RISCV][Clang] Support policy functions for vmerge, vfmerge and (authored by khchen). Changed prior to commit: https://reviews.llvm.

[PATCH] D126746: [RISCV][Clang] Support policy functions for Vector Comparison Instructions.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG9caf2cc05c02: [RISCV][Clang] Support policy functions for Vector Comparison (authored by khchen). Repository: rG LLVM Github Monorepo CHANGES SIN

[PATCH] D126748: [RISCV][Clang] Support policy functions for Vector Reduction Instructions.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGdffdca85ec2d: [RISCV][Clang] Support policy functions for Vector Reduction (authored by khchen). Changed prior to commit: https://reviews.llvm.org

[PATCH] D126749: [RISCV][Clang] Support policy functions for Vector Mask Instructions.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGbb99d4b11d84: [RISCV][Clang] Support policy functions for Vector Mask Instructions. (authored by khchen). Repository: rG LLVM Github Monorepo CHA

[PATCH] D126750: [RISCV][Clang] Support policy function for all vector segment load.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG010f329803c8: [RISCV][Clang] Support policy function for all vector segment load. (authored by khchen). Changed prior to commit: https://reviews.l

[PATCH] D105690: [RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change

khchen added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:10 /// This file describes the RISC-V instructions from the standard 'V' Vector /// extension, version 0.10. /// This version is still experimental as the 'V' extension hasn't been -

[PATCH] D105690: [RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change

khchen added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:10 /// This file describes the RISC-V instructions from the standard 'V' Vector /// extension, version 0.10. /// This version is still experimental as the 'V' extension hasn't been -

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

khchen added a comment. This all looks good to me except some tidy warning. wait for others comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:460 + +addExtension("e"); + } nit: add `break;` to avoid the implicit-fallthrough warning. ===

[PATCH] D105555: [PoC][RISCV][Clang] Compute the default target-abi if it's empty.

khchen updated this revision to Diff 359670. khchen added a comment. rebase on D105168 . Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D10/new/ https://reviews.llvm.org/D10 Files: clang/lib/Basic/Targets/

[PATCH] D106347: [PoC][RISCV] Encode arch information in a new module flag meatadata 'riscv-isa-bits'.

khchen created this revision. khchen added reviewers: jrtc27, MaskRay, kito-cheng. Herald added subscribers: vkmr, frasercrmck, dexonsmith, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng,

[PATCH] D106347: [PoC][RISCV] Encode arch information in a new module flag meatadata 'riscv-isa-bits'.

khchen added a comment. In D106347#2890123 , @jrtc27 wrote: > Why can't we just save target-features itself as a module flag instead of > inventing yet another equivalent encoding? Especially since a long bitfield > is brittle, you can't reorder or remo

[PATCH] D106347: [PoC][RISCV] Encode arch information in a new module flag meatadata 'riscv-isa-bits'.

khchen updated this revision to Diff 360723. khchen added a comment. store target-features string as module flag. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106347/new/ https://reviews.llvm.org/D106347 Files: clang/lib/CodeGen/CodeGenModule.c

[PATCH] D105555: [PoC][RISCV][Clang] Compute the default target-abi if it's empty.

khchen updated this revision to Diff 361216. khchen added a comment. address arichardson's comment, thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D10/new/ https://reviews.llvm.org/D10 Files: clang/lib/Basic/Targets/RISCV.cpp cla

[PATCH] D105555: [PoC][RISCV][Clang] Compute the default target-abi if it's empty.

khchen marked an inline comment as done. khchen added a comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D10/new/ https://reviews.llvm.org/D10 ___ cfe-commits mailing list cfe-commits@lists

[PATCH] D106347: [PoC][RISCV] Encode arch information in a new module flag meatadata 'riscv-isa-features'.

khchen added inline comments. Comment at: clang/lib/CodeGen/CodeGenModule.cpp:835 +llvm::RISCVISAInfo::filterISAStrings(Features); +std::vector Ops; +if (Features.empty()) { jrtc27 wrote: > Why is this building a list? Just use a string so it's in the

[PATCH] D105555: [RISCV][Clang] Compute the default target-abi if it's empty.

khchen updated this revision to Diff 361264. khchen added a comment. address @jrtc27's comment, thanks! I forget RISCVISAInfo include XLen.. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D10/new/ https://reviews.llvm.org/D10 Files: clang/

[PATCH] D105555: [RISCV][Clang] Compute the default target-abi if it's empty.

khchen updated this revision to Diff 361568. khchen marked 6 inline comments as done. khchen added a comment. address @jrtc27's comment, thanks again! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D10/new/ https://reviews.llvm.org/D10 Files

[PATCH] D105555: [RISCV][Clang] Compute the default target-abi if it's empty.

khchen added a comment. This patch depends on D105168 , Please help to review it if you have time. Thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D10/new/ https://reviews.llvm.org/D10 __

[PATCH] D121578: [RISCV][NFC] Add tests to address invalid arch dependencies.

khchen created this revision. khchen added reviewers: craig.topper, kito-cheng. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosb

[PATCH] D121345: [RISCV] Add +experimental-zvfh extension to cover half types in vectors.

khchen added a comment. LGTM. wait @kito-cheng to approve it. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D121345/new/ https://reviews.llvm.org/D121345 ___ cfe-commits mailing list cfe-commits@lists.ll

[PATCH] D120228: [RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR intrinsics.

khchen updated this revision to Diff 416057. khchen added a comment. Herald added subscribers: s, arichardson. rebase on main. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D120228/new/ https://reviews.llvm.org/D120228 Files: clang/include/clang/

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

khchen added a comment. Herald added a subscriber: s. In D70401#3384758 , @pcwang-thead wrote: > In D70401#3250049 , @khchen wrote: > >> 1. please add a check here >>

[PATCH] D121578: [RISCV][NFC] Add tests to address invalid arch dependencies.

This revision was automatically updated to reflect the committed changes. Closed by commit rGf5fea45d09e5: [RISCV][NFC] Add tests to address invalid arch dependencies. (authored by khchen). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D121578/new/ h

[PATCH] D121984: [RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support

khchen accepted this revision. khchen added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D121984/new/ https://reviews.llvm.org/D121984 __

[PATCH] D120227: [RISCV] Add policy operand for masked vid and viota IR intrinsics.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG9ab18cc53537: [RISCV] Add policy operand for masked vid and viota IR intrinsics. (authored by khchen). Herald added subscribers: s, StephenFan, arich

[PATCH] D120228: [RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR intrinsics.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG10fd2822b77e: [RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR (authored by khchen). Herald added a subscriber: StephenFan. Ch

[PATCH] D120870: [RISCV][NFC] Refine and refactor RISCVVEmitter and riscv_vector.td.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG23d60ce164db: [RISCV][NFC] Refine and refactor RISCVVEmitter and riscv_vector.td. (authored by khchen). Herald added subscribers: s, StephenFan, aric

[PATCH] D124062: [RISCV][Clang][NFC] Update vid intrinsic tests.

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, frasercrmck, kito-cheng, arcbbb, monkchiang, eopXD. Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX,

[PATCH] D124062: [RISCV][Clang][NFC] Update vid intrinsic tests.

This revision was automatically updated to reflect the committed changes. Closed by commit rGbd0d126302a8: [RISCV][Clang][NFC] Update vid intrinsic tests. (authored by khchen). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D124062/new/ https://review

[PATCH] D124062: [RISCV][Clang][NFC] Update vid intrinsic tests.

khchen added a comment. In D124062#3461069 , @frasercrmck wrote: > Were they perhaps passing because `i64 [[VL:%.*]]` was matching the `, i64 0` > too? Seems like a flaw in the checks generated by the script, but I can see > how the majority of the tim

[PATCH] D118333: [RISCV] Use computeTargetABI from llc as well as clang

khchen added a comment. clang will calculate the default target-abi if -mabi is empty and encode the it in LLVM IR module flag. then if llc has no target-abi option (`Options.MCOptions.ABIName` is empty), in getSubtargetImpl it uses different way to compute the default target-abi, then the defa

[PATCH] D119250: [RISCV][NFC] Refactor RISCVISAInfo.

khchen created this revision. khchen added reviewers: asb, kito-cheng, craig.topper, jrtc27. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, vkmr, frasercrmck, dexonsmith, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_

[PATCH] D118333: [RISCV] Use computeTargetABI from llc as well as clang

khchen updated this revision to Diff 406842. khchen added a comment. rebase on D119250 to make changes clear. Thanks for kito's suggestion! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D118333/new/ https://review

[PATCH] D119250: [RISCV][NFC] Refactor RISCVISAInfo.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGcfe7f690367b: [RISCV][NFC] Refactor RISCVISAInfo. (authored by khchen). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://r

[PATCH] D117989: [RISCV] Add the passthru operand for RVV nomask binary intrinsics.

khchen added a comment. Gentle ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117989/new/ https://reviews.llvm.org/D117989 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.

[PATCH] D117681: [RISCV] Add the policy operand for some masked RVV ternary IR intrinsics.

khchen added a comment. Gentle ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117681/new/ https://reviews.llvm.org/D117681 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.

[PATCH] D117681: [RISCV] Add the policy operand for some masked RVV ternary IR intrinsics.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGd224be3b999a: [RISCV] Add the policy operand for some masked RVV ternary IR intrinsics. (authored by khchen). Changed prior to commit: https://rev

[PATCH] D119686: [RISCV] Add the passthru operand for vadc/vsbc/vmerge/vfmerge IR intrinsics.

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, frasercrmck, kito-cheng, arcbbb, monkchiang, eopXD. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewe

[PATCH] D119727: [RISCV] Add the policy operand for nomask vector Multiply-Add IR intrinsics.

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, frasercrmck, kito-cheng, arcbbb, monkchiang, eopXD. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewe

[PATCH] D119727: [RISCV] Add the policy operand for nomask vector Multiply-Add IR intrinsics.

khchen updated this revision to Diff 408840. khchen added a comment. Rebase and refine code. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D119727/new/ https://reviews.llvm.org/D119727 Files: clang/include/clang/Basic/riscv_vector.td clang/test

[PATCH] D117989: [RISCV] Add the passthru operand for RVV nomask binary intrinsics.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGb7847199044e: [RISCV] Add the passthru operand for RVV nomask binary intrinsics. (authored by khchen). Herald added a subscriber: qcolombet. Changed

[PATCH] D118253: [RISCV] Add the passthru operand for some RVV nomask unary and nullary intrinsics.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGe8973dd389e7: [RISCV] Add the passthru operand for some RVV nomask unary and nullary… (authored by khchen). Changed prior to commit: https://revie

[PATCH] D119686: [RISCV] Add the passthru operand for nomask vadc/vsbc/vmerge/vfmerge IR intrinsics.

khchen updated this revision to Diff 409156. khchen added a comment. rebase and add more one test. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D119686/new/ https://reviews.llvm.org/D119686 Files: clang/include/clang/Basic/riscv_vector.td clan

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

khchen added a comment. In D70401#3325419 , @zixuan-wu wrote: > It's difficult to run llvm-test-suite in ilp32e abi in Linux. Because there > are no workable environment such as runtime and kernel for ilp32e in GNU > series tools. > And we can not run ll

[PATCH] D119686: [RISCV] Add the passthru operand for nomask vadc/vsbc/vmerge/vfmerge IR intrinsics.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG093ecccdab47: [RISCV] Add the passthru operand for vadc/vsbc/vmerge/vfmerge IR intrinsics. (authored by khchen). Repository: rG LLVM Github Monore

[PATCH] D119727: [RISCV] Add the policy operand for nomask vector Multiply-Add IR intrinsics.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGca783124073f: [RISCV] Add the policy operand for nomask vector Multiply-Add IR intrinsics. (authored by khchen). Changed prior to commit: https://

[PATCH] D124186: [RISCV] Fix incorrect policy implement for unmasked vslidedown and vslideup.

khchen added a comment. In D124186#3465136 , @craig.topper wrote: > The intrinsic interface doesn't care about 0 give user control of vstart. Nearly every instruction is undisturbed for > 0 > But having said that it probably makes sense to keep the vsli

[PATCH] D124186: [RISCV] Fix incorrect policy implement for unmasked vslidedown and vslideup.

khchen updated this revision to Diff 424517. khchen edited the summary of this revision. khchen added a comment. update clang tests. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D124186/new/ https://reviews.llvm.org/D124186 Files: clang/include/

[PATCH] D124186: [RISCV] Fix incorrect policy implement for unmasked vslidedown and vslideup.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGffe03ff75c26: [RISCV] Fix incorrect policy implement for unmasked vslidedown and vslideup. (authored by khchen). Changed prior to commit: https://

[PATCH] D124509: [RISCV] Fix int16 -> __fp16 conversion code gen

khchen added a comment. It's seem like all targets need to return `false` in `useFP16ConversionIntrinsics` for correctness of `int16` -> `__fp16` conversion? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D124509/new/ https://reviews.llvm.org/D12450

[PATCH] D124611: [RISCV][Clang] add more tests for clang driver. (NFC)

khchen created this revision. khchen added reviewers: craig.topper, asb, luismarques. Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01,

[PATCH] D124510: [RISCV] Precommit test for D124509

khchen accepted this revision. khchen added a comment. This revision is now accepted and ready to land. LGTM. Thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D124510/new/ https://reviews.llvm.org/D124510 __

[PATCH] D124611: [RISCV][Clang] add more tests for clang driver. (NFC)

khchen updated this revision to Diff 426587. khchen added a comment. Add zve64* tests. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D124611/new/ https://reviews.llvm.org/D124611 Files: clang/test/Driver/riscv-arch.c Index: clang/test/Driver/ri

[PATCH] D124611: [RISCV][Clang] add more tests for clang driver. (NFC)

This revision was automatically updated to reflect the committed changes. Closed by commit rG6c10014f1de6: [RISCV][Clang] add more tests for clang driver. (NFC) (authored by khchen). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D124611/new/ https://

[PATCH] D125323: [RISCV] Add the passthru operand for RVV unmasked segment load IR intrinsics.

khchen created this revision. khchen added reviewers: craig.topper, rogfer01, frasercrmck, kito-cheng, arcbbb, monkchiang, eopXD. Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX,

[PATCH] D124730: [RISCV][NFC] Refactor RISC-V vector intrinsic utils.

khchen added a comment. Herald added a subscriber: shiva0217. Thanks for refactoring! Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:55 +// basic vector type, used to compute type info of arguments. +enum class PrimitiveType : uint8_t { + Invalid, -

[PATCH] D125323: [RISCV] Add the passthru operand for RVV unmasked segment load IR intrinsics.

khchen updated this revision to Diff 428674. khchen added a comment. address Craig's comments, thanks!! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125323/new/ https://reviews.llvm.org/D125323 Files: clang/include/clang/Basic/riscv_vector.td

[PATCH] D125323: [RISCV] Add the passthru operand for RVV unmasked segment load IR intrinsics.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG7dfc56c10746: [RISCV] Add the passthru operand for RVV unmasked segment load IR intrinsics. (authored by khchen). Changed prior to commit: https:/

[PATCH] D124730: [RISCV][NFC] Refactor RISC-V vector intrinsic utils.

khchen accepted this revision. khchen added a comment. This revision is now accepted and ready to land. Thanks Kito. This all LGTM except some warnings need to fix. Comment at: clang/lib/Support/RISCVVIntrinsicUtils.cpp:384 +return PD; // Handle primitive type transforme

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

khchen added a comment. Do we need to have some tests in `clang/test/PCH/` for new #pragma? Comment at: clang/lib/Sema/SemaLookup.cpp:932 + if (DeclareRVVBuiltins) { +if (GetRVVBuiltinInfo(*this, R, II, PP)) { + return true; Don’t Use Brac

[PATCH] D125886: [RISCV][NFC] Rename variable in RISCVVEmitter.cpp

khchen accepted this revision. khchen added a comment. This revision is now accepted and ready to land. LGTM, thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125886/new/ https://reviews.llvm.org/D125886 __

[PATCH] D125765: [RISCV] Add type aliases float16_t, float32_t and float64_t

khchen added a comment. I think we have no consensus in https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/18#issuecomment-817890161, and most people disagree the current naming, maybe we need to have more followup discussion before landing this patch. For example, maybe `_Float16` shoul

[PATCH] D125875: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h

khchen added a comment. please move those tests to `test/CodeGen/RISCV/rvv-intrinsics` and rename them without `rvv-` prefix. Comment at: clang/include/clang/Basic/riscv_vector.td:1511 +__extension__ extern __inline +__attribute__ ((__always_inline__, __gnu_inline__, __artific

[PATCH] D125765: [RISCV] Add type aliases float16_t, float32_t and float64_t

khchen added a comment. In D125765#3526835 , @pcwang-thead wrote: > In D125765#3524456 , @khchen wrote: > >> I think we have no consensus in >> https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/18#issuec

[PATCH] D126042: [RISCV][NFC] Remove `*=` operator for LMULType

khchen accepted this revision. khchen added a comment. This revision is now accepted and ready to land. LGTM, thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D126042/new/ https://reviews.llvm.org/D126042 __

[PATCH] D93446: [RISCV] Add vadd with mask and without mask builtin.

khchen added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:194 HasV = true; -else if (Feature == "+experimental-zfh") + HasRISCVVTypes = true; +} else if (Feature == "+experimental-zfh") HasRISCVVTypes is an undefined variable

[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

khchen updated this revision to Diff 345712. khchen added a comment. Herald added a subscriber: vkmr. Pass -target-abi option into LTO codegenerator base on D102582 patch. please see D102582 for more detal. Repository: rG

[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

khchen added a comment. In D71387#1820995 , @efriedma wrote: > Okay. Please let me know if you want me to review anything. Hi all, We had encoded the target-abi into module now, but I feel it does not make sense to support overwrite ABI option and data

[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

khchen added a comment. In D71387#2762120 , @jrtc27 wrote: > In D71387#2762115 , @khchen wrote: > >> In D71387#1820995 , @efriedma wrote: >> >>> Okay. Please let me know if

[PATCH] D102582: [RISCV] Report an error when ABI mismatch with target-abi module flag.

khchen updated this revision to Diff 348870. khchen added a comment. Herald added a project: clang. Herald added a subscriber: cfe-commits. Revert to previous revision Diff 347356 and add empty module flag could be empty in test. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen updated this revision to Diff 318423. khchen added a comment. 1. address @craig.topper's comment. 2. rewrite script as python. I'm still have no idea to make generating tests mechanism be more elegant... Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.l

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen marked 7 inline comments as done. khchen added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:191 +defvar suffix = s_p[1]; +defvar prototype = s_p[2]; + Paul-C-Anagnostopoulos wrote: > Well now, thanks for highlighti

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen updated this revision to Diff 318447. khchen marked 2 inline comments as done. khchen added a comment. 1. do not need to manually define new op in gen-rvv-tests.py. 2. do not need to manually add new op define in ALL marco. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen updated this revision to Diff 319000. khchen marked 7 inline comments as done. khchen added a comment. 1. address @HsiangKai's comments 2. remove test generator to make td simpler. 3. remove MangledSuffix, it should be MangledName Repository: rG LLVM Github Monorepo CHANGES SINCE LAST

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:161 + // This builtin is valid for the given exponental LMULs. + list ELMUL = [0, 1, 2, 3, -1, -2, -3]; + HsiangKai wrote: > EMUL according to specification. Here ELMUL means e

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen updated this revision to Diff 319488. khchen marked 21 inline comments as done. khchen added a comment. 1. address @jrtc27's comments. I really appreciate your help very much. 2. use downstream test generator and move all tests to rvv-intrinsics-generic and rvv-intrinsics. Repository:

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen added inline comments. Comment at: clang/test/CodeGen/RISCV/riscv-rvv-intrinsics-generic/vadd.c:10 + +// ASM-NOT: warning +#include jrtc27 wrote: > Asm checks are discouraged in Clang. If you want to check for Clang warnings, > use -verify, and in this c

[PATCH] D105092: [RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.

khchen added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:162 // For unit stride load with mask // Input: (maskedoff, pointer, mask, vl) class RISCVUSLoadMask maybe we could have another NFC patch to update those `argument info` c

[PATCH] D109322: [RISCV] (2/2) Add the tail policy argument to builtins/intrinsics.

khchen added inline comments. Herald added a subscriber: achieveartificialintelligence. Comment at: clang/include/clang/Basic/riscv_vector.td:181 + // no need to specify the tail policy. + bit HasPolicy = true; + Add more comment like: If `HasPolicy`, masked op

[PATCH] D109322: [RISCV] (2/2) Add the tail policy argument to builtins/intrinsics.

khchen accepted this revision. khchen added a comment. This revision is now accepted and ready to land. LGTM. Comment at: clang/include/clang/Basic/riscv_vector.td:2186 +}] in +def policy : RVVHeader; HsiangKai wrote: > khchen wrote: > > It seems like we can re

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen updated this revision to Diff 322297. khchen marked 3 inline comments as done. khchen added a comment. 1. address Jim's comment. 2. remove suffix `_vl` according by https://github.com/riscv/rvv-intrinsic-doc/pull/64 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen added inline comments. Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:2 -RISCVV_BUILTIN(vadd_vv_i8m1_vl, "q8Scq8Scq8Scz", "n") -RISCVV_BUILTIN(vadd_vv_i8m1_m_vl, "q8Scq8bq8Scq8Scq8Scz", "n") -RISCVV_BUILTIN(vadd_vv_i16m1_vl, "q4Ssq4Ssq4Ssz", "n") -RISCVV_BUILTIN

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen updated this revision to Diff 322300. khchen added a comment. Rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95016/new/ https://reviews.llvm.org/D95016 Files: clang/include/clang/Basic/BuiltinsRISCV.def clang/include/clang/Basic/C

[PATCH] D93446: [RISCV] Add vadd with mask and without mask builtin.

khchen added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:89 +#define BUILTIN(ID, TYPE, ATTRS) \ + {"__builtin_rvv_" #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, +#include "clang/Basic/BuiltinsRISCV.def" ---

[PATCH] D96843: [Clang][RISCV] Add vsetvl and vsetvlmax.

khchen created this revision. khchen added reviewers: craig.topper, jrtc27, rogfer01, frasercrmck, HsiangKai, evandro. Herald added subscribers: vkmr, dexonsmith, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zz

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

khchen updated this revision to Diff 324197. khchen added a comment. remove float32_t and float64_t to avoid collisions with other project. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95016/new/ https://reviews.llvm.org/D95016 Files: clang/inc

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