khchen added inline comments.
================ Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:10 /// This file describes the RISC-V instructions from the standard 'V' Vector /// extension, version 0.10. /// This version is still experimental as the 'V' extension hasn't been ---------------- jacquesguan wrote: > khchen wrote: > > Do we need to update 0.10 to 1.0-rc? > > If the answer is yes, I think maybe we also need to update the clang part > > (ex. arch parsing, predefine macro) in follow-up patches. > > > > > Maybe update it after finishing all changes in 1.0-rc? > Maybe update it after finishing all changes in 1.0-rc? Yes. The other questions like how do you encode `rc1` in `march` or predefined architecture extension macro. or maybe we could just use 1.0 directly because v is still an experiential extension. @luismarques @frasercrmck @craig.topper @HsiangKai What do you think? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105690/new/ https://reviews.llvm.org/D105690 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
