khchen created this revision. khchen added reviewers: craig.topper, rogfer01, frasercrmck, kito-cheng, arcbbb, monkchiang, eopXD. Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya, arichardson, qcolombet, MatzeB. Herald added a project: All. khchen requested review of this revision. Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, MaskRay. Herald added projects: clang, LLVM.
The goal is support tail and mask policy in RVV builtins. We focus on IR part first. If the passthru operand is undef, we use tail agnostic, otherwise use tail undisturbed. Repository: rG LLVM Github Monorepo https://reviews.llvm.org/D125323 Files: clang/include/clang/Basic/riscv_vector.td clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg_mf.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg_mf.c clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask.c clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_mf.c clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mf.c clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask.c clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf.c llvm/include/llvm/IR/IntrinsicsRISCV.td llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
