https://github.com/yetingk created
https://github.com/llvm/llvm-project/pull/71513
This patch reference ac1ffd3caca12c254e0b8c847aa8ce8e51b6cfbf to suppot a soft
coding way to identify whether a cpu has a feature `unaligned-scalar-mem` by
`RISCVProcessors.td`.
This patch does not provide test
@@ -44,6 +45,11 @@ static const CPUInfo *getCPUInfoByName(StringRef CPU) {
return nullptr;
}
+bool hasFastUnalignedAccess(StringRef CPU) {
+ const CPUInfo *Info = getCPUInfoByName(CPU);
+ return Info && Info->FastUnalignedAccess;
yetingk wrote:
It's possi
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/71513
>From 1a6da0d00af17ae17e6c569f12f3e34fbbdf611d Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 7 Nov 2023 18:48:04 +0800
Subject: [PATCH 1/2] [RISCV][Clang][TargetParser] Support getting feature
unaligned-s
@@ -60,9 +60,14 @@ static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream
&OS) {
if (MArch.empty())
MArch = getMArch(*Rec);
+bool FastUnalignedAccess =
yetingk wrote:
Done.
https://github.com/llvm/llvm-project/pull/71513
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/66043
>From 91bb1d9884276a37f93515a648aa6ece353fdc70 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/4] [RISCV] Add MC layer support for Zicfiss.
The patch adds the in
https://github.com/yetingk closed
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https://github.com/llvm/llvm-project/pull/75134
Bump to https://github.com/riscv/riscv-cfi/releases/tag/v0.4.0. Actually there
is no functional change here.
>From ec87b87a67acdcb8faedec327e0938476ddb0893 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 1
@@ -2429,15 +2455,32 @@ let HasMasked = false, HasVL = false, IRName = "" in {
SupportOverloading = false,
ManualCodegen = [{
{
-assert(isa(ResultType));
-unsigned NF = cast(ResultType)->getNumElements();
-llvm::Value *ReturnTuple = llv
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https://github.com/llvm/llvm-project/pull/70355
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https://github.com/yetingk approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/70355
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>From 91bb1d9884276a37f93515a648aa6ece353fdc70 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/6] [RISCV] Add MC layer support for Zicfiss.
The patch adds the in
@@ -27,6 +27,11 @@
using namespace llvm;
+static cl::opt
yetingk wrote:
The new commit
[2830d3e](https://github.com/llvm/llvm-project/pull/68075/commits/2830d3ebf9eb9aae758740e6c38359984b8684b2)
adds a new feature to replace this. In the feature, we can ad
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/66043
>From 834bb96261b3e7b65a0bbd8f2651c3d307f1de79 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/6] [RISCV] Add MC layer support for Zicfiss.
The patch adds the in
yetingk wrote:
Rebase and bump to 0.4
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https://github.com/yetingk approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/74280
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@@ -736,7 +736,7 @@ R"(All available -march extensions for RISC-V
xventanacondops 1.0
Experimental extensions
-zicfilp 0.2 This is a long dummy description
+zicfilp 0.4 This is a long dummy description
yeting
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https://github.com/llvm/llvm-project/pull/66043
>From 01222b781e3a0a925d2cdf793c54c7d6050f82af Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH] [RISCV] Add MC layer support for Zicfiss.
The patch adds the instru
yetingk wrote:
Rebase and ping.
https://github.com/llvm/llvm-project/pull/66043
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https://github.com/llvm/llvm-project/pull/66043
>From 01222b781e3a0a925d2cdf793c54c7d6050f82af Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/2] [RISCV] Add MC layer support for Zicfiss.
The patch adds the in
@@ -165,6 +167,10 @@ def SP : GPRRegisterClass<(add X2)>;
def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9),
(sequence "X%u", 18, 23))>;
+def GPRX1X5 : RegisterClass<"RISCV", [XLenVT], 32, (add X1, X5)> {
yetingk wrote:
@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const
llvm::Triple &TargetTriple,
Result.Multilibs = CSKYMultilibs;
}
+/// Extend the multi-lib re-use selection mechanism for RISC-V.
+/// This funciton will try to re-use multi-lib if they are compat
@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const
llvm::Triple &TargetTriple,
Result.Multilibs = CSKYMultilibs;
}
+/// Extend the multi-lib re-use selection mechanism for RISC-V.
+/// This funciton will try to re-use multi-lib if they are compat
@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const
llvm::Triple &TargetTriple,
Result.Multilibs = CSKYMultilibs;
}
+/// Extend the multi-lib re-use selection mechanism for RISC-V.
+/// This funciton will try to re-use multi-lib if they are compat
@@ -1715,6 +1716,129 @@ static void findCSKYMultilibs(const Driver &D, const
llvm::Triple &TargetTriple,
Result.Multilibs = CSKYMultilibs;
}
+/// Extend the multi-lib re-use selection mechanism for RISC-V.
+/// This funciton will try to re-use multi-lib if they are compat
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https://github.com/llvm/llvm-project/pull/73765
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yetingk wrote:
Ping.
https://github.com/llvm/llvm-project/pull/66043
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yetingk wrote:
> It seems that the author of Zimop implementation doesn't have commit access.
> @yetingk Would you mind to commit it and rebase your PR on that? It will make
> this PR simpler.
Sure.
https://github.com/llvm/llvm-project/pull/66043
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>From 99d35bbe5bab93b4a39a436d1bc9626e68c401ef Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH] [RISCV] Add MC layer support for Zicfiss.
The patch adds the instru
yetingk wrote:
Rebase.
> It seems that the author of Zimop implementation doesn't have commit access.
> @yetingk Would you mind to commit it and rebase your PR on that? It will make
> this PR simpler.
It's weird that `SSPUSH` and `SSPOPCHK` are not fit into `mop.r` instruction
now.
https://
https://github.com/yetingk created
https://github.com/llvm/llvm-project/pull/76390
It's unnecessary to defaultly pass feature `-save-restore`, since risc-v
backend defaultly disables save-restore functionality.
>From 97fe56d808f1752ac4b7d26deecabb857e0a4208 Mon Sep 17 00:00:00 2001
From: Yetin
@@ -0,0 +1,71 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
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https://github.com/llvm/llvm-project/pull/76390
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>From 71c202c4f16451f7d0d9e17239f95418ea315c0a Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 26 Dec 2023 02:11:30 -0800
Subject: [PATCH] [RISCV][Clang] Remove default feature -save-restore.
It's unnecessa
@@ -0,0 +1,71 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -0,0 +1,30 @@
+//===-- RISCVInstrInfoZcmop.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
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@@ -693,6 +693,13 @@ def HasStdExtZimop :
Predicate<"Subtarget->hasStdExtZimop()">,
AssemblerPredicate<(all_of FeatureStdExtZimop),
"'Zimop' (May-Be-Operations)">;
+def FeatureStdExtZcmop : SubtargetFeature<"experi
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https://github.com/yetingk approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/76422
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https://github.com/yetingk approved this pull request.
LGTM. But please wait for @topperc's review.
https://github.com/llvm/llvm-project/pull/76395
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>From 4a73535ec7206951c6b843e11c81e6c0c01cc1d0 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/3] [RISCV] Add MC layer support for Zicfiss.
The patch adds the in
yetingk wrote:
Rebase but I didn't use alias to Zimop and Zcmop ways to achieve this code,
since using them will lose some information like `Uses = [SSP]`.
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@@ -60,12 +60,3 @@ defm SSAMOSWAP_W : AMO_rr_aq_rl<0b01001, 0b010,
"ssamoswap.w">;
let Predicates = [HasStdExtZicfiss, IsRV64] in
defm SSAMOSWAP_D : AMO_rr_aq_rl<0b01001, 0b011, "ssamoswap.d">;
-
-//===--==
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/66043
>From 4a73535ec7206951c6b843e11c81e6c0c01cc1d0 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/4] [RISCV] Add MC layer support for Zicfiss.
The patch adds the in
@@ -1024,6 +1024,7 @@ static const char *ImpliedExtsZfinx[] = {"zicsr"};
static const char *ImpliedExtsZhinx[] = {"zhinxmin"};
static const char *ImpliedExtsZhinxmin[] = {"zfinx"};
static const char *ImpliedExtsZicntr[] = {"zicsr"};
+static const char *ImpliedExtsZicfiss[] = {"
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>From be70878169742f7e9cbb276a05254019c586897b Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 3 Oct 2023 16:08:06 +0800
Subject: [PATCH 1/4] [RISCV] Implement shadow stack on shadow stack mode with
Zicfiss
yetingk wrote:
Rebase and ping. I also update the first comment of the first comment of this
pr since the control stack mode is removed and we add new feature
`forced-sw-shadow-stack`.
https://github.com/llvm/llvm-project/pull/68075
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yetingk wrote:
Unwinder could use property `GNU_PROPERTY_RISCV_FEATURE_1_ZICFISS` to know the
binary uses `ssp` as the shadow stack register.
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/417/files
https://github.com/llvm/llvm-project/pull/68075
_
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https://github.com/llvm/llvm-project/pull/68075
>From be70878169742f7e9cbb276a05254019c586897b Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 3 Oct 2023 16:08:06 +0800
Subject: [PATCH 1/5] [RISCV] Implement shadow stack on shadow stack mode with
Zicfiss
@@ -57,11 +57,12 @@ compiled application or the operating system. Integrating
the runtime into
the operating system should be preferred since otherwise all thread creation
and destruction would need to be intercepted by the application.
-The instrumentation makes use of the p
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>From be70878169742f7e9cbb276a05254019c586897b Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 3 Oct 2023 16:08:06 +0800
Subject: [PATCH 1/6] [RISCV] Implement shadow stack on shadow stack mode with
Zicfiss
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/68075
>From faed2ea0b0cd7dc207e0886be8cb1647343793d4 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 3 Oct 2023 16:08:06 +0800
Subject: [PATCH 1/6] [RISCV] Implement shadow stack on shadow stack mode with
Zicfiss
@@ -57,11 +57,14 @@ compiled application or the operating system. Integrating
the runtime into
the operating system should be preferred since otherwise all thread creation
and destruction would need to be intercepted by the application.
-The instrumentation makes use of the p
@@ -151,9 +155,10 @@ Usage
To enable ShadowCallStack, just pass the ``-fsanitize=shadow-call-stack`` flag
to both compile and link command lines. On aarch64, you also need to pass
-``-ffixed-x18`` unless your target already reserves ``x18``. On RISC-V, ``x3``
-(``gp``) is alwa
Author: Yeting Kuo
Date: 2022-07-05T11:02:44+08:00
New Revision: 939352b6ec31db4e8defe07856868438fbc5340d
URL:
https://github.com/llvm/llvm-project/commit/939352b6ec31db4e8defe07856868438fbc5340d
DIFF:
https://github.com/llvm/llvm-project/commit/939352b6ec31db4e8defe07856868438fbc5340d.diff
LO
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yetingk wrote:
> Will
> [riscv-non-isa/riscv-elf-psabi-doc#417](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/417)
> be implemented in a separate patch?
Sure.
https://github.com/llvm/llvm-project/pull/68075
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https://github.com/llvm/llvm-project/pull/68075
>From faed2ea0b0cd7dc207e0886be8cb1647343793d4 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 3 Oct 2023 16:08:06 +0800
Subject: [PATCH 1/9] [RISCV] Implement shadow stack on shadow stack mode with
Zicfiss
@@ -106,9 +112,15 @@ static void emitSCSEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (!STI.hasForcedSWShadowStack() &&
+
@@ -51,9 +51,15 @@ static void emitSCSPrologue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (!STI.hasForcedSWShadowStack() &&
+
yetingk wrote:
Ping.
https://github.com/llvm/llvm-project/pull/68075
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>From faed2ea0b0cd7dc207e0886be8cb1647343793d4 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 3 Oct 2023 16:08:06 +0800
Subject: [PATCH 1/8] [RISCV] Implement shadow stack on shadow stack mode with
Zicfiss
@@ -57,11 +57,16 @@ compiled application or the operating system. Integrating
the runtime into
the operating system should be preferred since otherwise all thread creation
and destruction would need to be intercepted by the application.
-The instrumentation makes use of the p
@@ -151,9 +157,12 @@ Usage
To enable ShadowCallStack, just pass the ``-fsanitize=shadow-call-stack`` flag
to both compile and link command lines. On aarch64, you also need to pass
-``-ffixed-x18`` unless your target already reserves ``x18``. On RISC-V, ``x3``
-(``gp``) is alwa
@@ -27,6 +27,11 @@
// DEFAULT-NOT: "-target-feature" "-save-restore"
// DEFAULT-NOT: "-target-feature" "+save-restore"
+// RUN: %clang --target=riscv32-unknown-elf -### %s -mforced-sw-shadow-stack
2>&1 | FileCheck %s -check-prefix=FORCE-SW-SCS
yetingk wrote:
yetingk wrote:
Ping.
https://github.com/llvm/llvm-project/pull/68075
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>From 91bb1d9884276a37f93515a648aa6ece353fdc70 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/3] [RISCV] Add MC layer support for Zicfiss.
The patch adds the in
@@ -0,0 +1,86 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -0,0 +1,86 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -0,0 +1,86 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -0,0 +1,86 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
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https://github.com/llvm/llvm-project/pull/65756
>From 391711dd39e2ee2e8f5d3dac6f466649238f4517 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Fri, 8 Sep 2023 19:46:03 +0800
Subject: [PATCH 1/2] [RISCV] Support predefined marcro
__riscv_misaligned_{fast,avoid
@@ -1228,3 +1228,15 @@
// RUN: -march=rv64i_zve32x_zvkt1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKT-EXT %s
// CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}}
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
https://github.com/yetingk closed
https://github.com/llvm/llvm-project/pull/65756
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Author: Yeting Kuo
Date: 2022-12-28T23:57:54-08:00
New Revision: bd9c0f082b20d96ced1e5f5ddc1506afffc0f8d3
URL:
https://github.com/llvm/llvm-project/commit/bd9c0f082b20d96ced1e5f5ddc1506afffc0f8d3
DIFF:
https://github.com/llvm/llvm-project/commit/bd9c0f082b20d96ced1e5f5ddc1506afffc0f8d3.diff
LO
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/66043
>From 91bb1d9884276a37f93515a648aa6ece353fdc70 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/2] [RISCV] Add MC layer support for Zicfiss.
The patch adds the in
@@ -165,6 +167,10 @@ def SP : GPRRegisterClass<(add X2)>;
def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9),
(sequence "X%u", 18, 23))>;
+def GPRRA : RegisterClass<"RISCV", [XLenVT], 32, (add X1, X5)> {
yetingk wrote:
Do
https://github.com/yetingk created
https://github.com/llvm/llvm-project/pull/68075
There are two shadow stack implements with Zicfiss in [spec] now.
In Shadow stack mode, programs still store the return address to regular
address.
In Control stack mode, programs only store the return address to
yetingk wrote:
This is based on #66762.
https://github.com/llvm/llvm-project/pull/68075
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Author: Yeting Kuo
Date: 2023-08-16T08:52:51+08:00
New Revision: 818e76d6f2dd90362e71e84f492c167958ef3257
URL:
https://github.com/llvm/llvm-project/commit/818e76d6f2dd90362e71e84f492c167958ef3257
DIFF:
https://github.com/llvm/llvm-project/commit/818e76d6f2dd90362e71e84f492c167958ef3257.diff
LO
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/68075
>From 91bb1d9884276a37f93515a648aa6ece353fdc70 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/4] [RISCV] Add MC layer support for Zicfiss.
The patch adds the in
yetingk wrote:
> The patch basically changes the ShadowCallStack back-end to emit an
> sspush/sspopchk instead of the usual SCS push/pop, which seems like a
> reasonable approach to me. However, it would be helpful to mention the
> dependency on `-fsanitize=shadow-call-stack` in the commit mes
@@ -106,9 +111,14 @@ static void emitSCSEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (STI.hasFeature(RISCV::FeatureStdExt
@@ -106,9 +111,14 @@ static void emitSCSEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (STI.hasFeature(RISCV::FeatureStdExt
https://github.com/yetingk edited
https://github.com/llvm/llvm-project/pull/68075
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https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/68075
>From 91bb1d9884276a37f93515a648aa6ece353fdc70 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/5] [RISCV] Add MC layer support for Zicfiss.
The patch adds the in
@@ -106,9 +111,14 @@ static void emitSCSEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (STI.hasFeature(RISCV::FeatureStdExt
https://github.com/yetingk edited
https://github.com/llvm/llvm-project/pull/68075
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yetingk wrote:
Ping.
https://github.com/llvm/llvm-project/pull/65756
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